Henrik Rydgard
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490d8be4df
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Some cleanup, enable CRT memory tracker in debug builds
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2015-10-04 14:11:34 +02:00 |
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Henrik Rydgard
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68fc776fa7
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Work around some crashes I got trying to load a GTA:LCS savestate from 2014.
However, the savestate still loads to a black screen, although background audio is working.
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2015-10-04 10:34:15 +02:00 |
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Unknown W. Brackets
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ea271dd61d
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Kill FINAL ifdef entirely.
We've never turned off the disasm pointer and it's probably not worthwhile
at this point...
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2015-09-20 11:39:46 -07:00 |
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Unknown W. Brackets
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3301a347b3
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arm64: Dumb typo, oops.
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2015-09-12 11:56:33 -07:00 |
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Unknown W. Brackets
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dd548ba12c
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arm64: Check for unordered in vmin/vmax.
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2015-09-08 20:07:10 -07:00 |
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Henrik Rydgard
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1c67de0c21
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We don't need a third set of sized integer typedefs, get rid of it.
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2015-09-06 19:10:08 +02:00 |
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Unknown W. Brackets
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9b94266c4a
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arm64: Avoid overflow in imm math.
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2015-08-30 13:00:18 -07:00 |
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Unknown W. Brackets
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9262ddfc13
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Avoid any possible shifts by 32.
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2015-07-19 13:25:50 -07:00 |
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Unknown W. Brackets
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cd842ac21f
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Validate blocklinking in icache invalidate all.
Normally blocks are invalidated on entry. But when blocklinking is on,
we don't validate on all entries.
This fixes Tales of Rebirth crashes (#7868.)
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2015-07-19 13:08:32 -07:00 |
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Unknown W. Brackets
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96b01e4999
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Make sure we don't clean up proxy blocks.
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2015-07-19 13:04:06 -07:00 |
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Henrik Rydgard
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47f68ae3a3
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ARM64 store optimization bugfix
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2015-07-16 00:25:32 +02:00 |
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Henrik Rydgard
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aaa8350591
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Windows: Fix some remaining ASLR issues
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2015-07-15 22:25:24 +02:00 |
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Henrik Rydgard
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ccd77cfb7a
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ARM64 stores: Use WZR for any zero immediates.
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2015-07-15 20:01:36 +02:00 |
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Henrik Rydgard
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8b05e27259
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ARM64 regalloc: Map more registers
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2015-07-11 23:53:06 +02:00 |
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Henrik Rydgard
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9fe382ad18
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ARM64: Shortcut moves between gpr and vfpu when not mapped
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2015-07-11 23:53:06 +02:00 |
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Henrik Rydgard
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56f9aaa164
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ARM64: Store zeroes using WZR
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2015-07-11 23:53:05 +02:00 |
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Henrik Rydgård
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1ba2b1cfae
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Merge pull request #7855 from hrydgard/static-alloc
ARM64 jit: Statically allocate a few registers, including SP
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2015-07-11 18:13:47 +02:00 |
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Henrik Rydgard
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2e937b2d10
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use the DiscardR function. Remove an old TODO
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2015-07-11 17:17:54 +02:00 |
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Henrik Rydgard
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b73920fcba
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ARM64: Cleanups in regcache and jit
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2015-07-11 17:00:01 +02:00 |
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Henrik Rydgard
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444fc0885c
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Fix the crash bug (need to mark static non-pointer regs as depointerified on flush)
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2015-07-11 16:59:14 +02:00 |
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Henrik Rydgard
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2a8560e522
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ARM64: Another pair of fixes for static alloc. Still crashes in many games...
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2015-07-11 16:59:14 +02:00 |
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Henrik Rydgard
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d1bbc1d3c0
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More regcache fixes. ML_IMM works now although there is another stability issue somewhere.
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2015-07-11 16:59:13 +02:00 |
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Henrik Rydgard
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568e2abb2b
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Save/load static registers around replacement funcs
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2015-07-11 16:59:13 +02:00 |
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Henrik Rydgard
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1b8549b26f
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Couple more regcache fixes
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2015-07-11 16:59:12 +02:00 |
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Henrik Rydgard
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4920f3e3c1
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Work towards handling ML_IMM in static registers but doesn't work yet (enable on line 649)
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2015-07-11 16:59:11 +02:00 |
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Henrik Rydgard
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f42f81a4da
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ARM64: Optimize small adjustments of pointerified registers
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2015-07-11 16:59:11 +02:00 |
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Henrik Rydgard
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9af6abd8a1
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ARM64: Support pointerified static allocs, statically allocate SP
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2015-07-11 16:59:10 +02:00 |
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Henrik Rydgard
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844a3f19a9
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Fix bugs and issues in ARM64 static alloc. Thanks unknown for finding the problem.
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2015-07-11 16:59:09 +02:00 |
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Henrik Rydgard
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a0bf934796
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ARM64: Some work on static allocation. Close to working, cube.elf runs 700 blocks but then hangs (?!)
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2015-07-11 16:59:09 +02:00 |
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Henrik Rydgard
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698ef82452
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ARM64: Fix vrot
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2015-07-11 16:56:26 +02:00 |
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Henrik Rydgard
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9937b41461
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ARM64: Fix vi2uc and vi2us and enable them.
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2015-07-11 16:46:11 +02:00 |
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Henrik Rydgard
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dc2f6a30fb
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ARM64: Fix joining of lwl/lwr and swl/swr. "implement" the cache instruction.
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2015-07-11 16:25:22 +02:00 |
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Henrik Rydgard
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1575025b3d
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ARM64: Store back fp registers in pairs where possible
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2015-07-11 13:52:46 +02:00 |
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Henrik Rydgard
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35c65973c1
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ARM64 jit: implement vuc2i, vc2i, vus2i, vs2i instructions
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2015-07-11 13:25:58 +02:00 |
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Henrik Rydgard
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4a7ee6d6cd
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ARM64 jit: Implement vi2uc, vi2c, vi2us, vi2s instructions
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2015-07-11 12:37:23 +02:00 |
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Henrik Rydgard
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f50828a66a
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ARM32 JIT: Implement vs2i, vus2i, vc2i (but not vuc2i)
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2015-07-11 00:37:57 +02:00 |
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Henrik Rydgard
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cd1665e8f6
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ARM32 jit: Implement vi2s, vi2c (but not the unsigned variants yet). uses the new shifts from the last commit
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2015-07-09 00:27:12 +02:00 |
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Henrik Rydgard
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a3b728dd1b
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ARM64 jit: Minor optimization of lv.q and sv.q
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2015-07-08 11:59:48 +02:00 |
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Henrik Rydgård
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f3c5af570c
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Merge pull request #7849 from unknownbrackets/arm64-micro
Fix discarding imms and flushing zero in arm64
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2015-07-05 21:11:28 +02:00 |
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Unknown W. Brackets
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db3dffb44d
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arm64: Oops, fix flushing zero from an armreg.
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2015-07-05 11:57:18 -07:00 |
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Unknown W. Brackets
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204c1dc8dd
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arm64: Optimize 3ops against zero.
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2015-07-05 09:52:53 -07:00 |
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Henrik Rydgard
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7011758e83
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Move misplaced FlushIcache() in Arm64Asm.cpp
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2015-07-05 10:03:52 +02:00 |
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Unknown W. Brackets
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003668fe66
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armjit: Fix discarding imms.
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2015-07-04 07:30:32 -07:00 |
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Unknown W. Brackets
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8ea7f99072
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arm64: Fix imm wasting when STP doesn't work out.
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2015-07-04 07:09:47 -07:00 |
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Unknown W. Brackets
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e6a7ba3fae
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arm64: Bring imms along for the STP ride.
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2015-07-03 16:51:33 -07:00 |
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Unknown W. Brackets
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ca1e482a56
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arm64: Avoid setting a reg to zero to store it.
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2015-07-03 16:05:25 -07:00 |
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Henrik Rydgård
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82c66bc463
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Merge pull request #7840 from unknownbrackets/arm64-micro
Flush using STP where possible in ARM64
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2015-07-03 23:20:43 +02:00 |
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Unknown W. Brackets
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8fdceba7ca
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Add timing for all the basics.
This way we can see overall stats for a frame.
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2015-07-03 12:05:08 -07:00 |
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Unknown W. Brackets
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90b7d135cb
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arm64: Flush in pairs if possible.
On an A57, this is around twice as fast (for just the STR/STR vs STP.)
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2015-07-03 11:07:09 -07:00 |
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Unknown W. Brackets
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ddb955a527
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arm64: Try to optimize imm stores.
If we already have a reg, we can use it. This can happen when immediate
addresses are loaded and used as bases, although it's not super common.
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2015-07-03 10:48:11 -07:00 |
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