5751e202a5
Remove redundant .c_str()
2025-08-31 13:37:43 +02:00
037e89fdd1
RISCV: enable some cpu extensions for spacemit k1
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spacemit vendor linux kernel is spacemit,k1-x:
k1-x is from spacemit https://gitee.com/bianbu-linux/linux-6.6/blob/k1-bl-v2.1.y/arch/riscv/boot/dts/spacemit/k1-x.dtsi#L17
while upstream linux kernel is spacemit,k1:
https://github.com/torvalds/linux/blob/a5806cd506af5a7c19bcd596e4708b5c464bfd21/arch/riscv/boot/dts/spacemit/k1.dtsi#L11
2025-05-20 16:11:42 +08:00
e1916bf1fe
CMake: Add checks for getauxval and elf_aux_info
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Add support for CPU feature detection on OpenBSD and FreeBSD riscv64.
2025-01-26 22:44:04 -05:00
59ba9ab973
Fix building on OpenBSD/riscv64.
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Unbreak on riscv64, we don't have sys/auxv.h or getauxval().
OpenBSD/riscv64 assumes RV64GC, aka RV64IMAFDC.
Our kernel provides no support for the V extension.
2024-04-27 07:44:37 -04:00
1f129b6dca
Replace "ReadFileToString" with a few semantically clearer wrappers.
2024-01-25 09:55:54 +01:00
46b25d20a4
Merge pull request #18637 from unknownbrackets/riscv-more
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Add some more RISC-V extensions to emitter
2023-12-29 19:03:49 +01:00
52db66e7ad
riscv: Add vector bitmanip encoding.
2023-12-29 09:42:23 -08:00
83dc1c9705
riscv: Add detect flags, not detected yet.
2023-12-29 09:42:23 -08:00
e3177ac870
Make some global string pointers const, not just the strings.
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Minor cleanup.
2023-12-29 14:09:45 +01:00
030a27f15d
riscv: Stop considering bitmanip "B".
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Apparently it's not being called B anymore and B is still reserved.
2023-07-23 14:41:08 -07:00
0c99d6d3fa
riscv: Workaround Zicsr detection issue.
2023-07-23 14:41:08 -07:00
ac40721a64
riscv: Use cpu_features for V detection.
2023-04-29 10:07:50 -07:00
63f370916b
riscv: Enable Zba/Zbb by soc compatible.
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Instead of u74, because apparently some older u74 don't support it.
2023-03-03 03:37:58 +00:00
04ce3a0572
riscv: Allow subset of B extension to be used.
2023-02-16 16:09:22 -08:00
dcd83c1e47
riscv: Detect Zicsr with cpu_features.
2023-01-29 15:24:41 -08:00
09eb509df4
Common: Expose CPU extension list directly.
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A bit silly to rely on the specific string formatting of a summary.
2023-01-29 15:13:44 -08:00
3bc2450b5e
riscv: Add bitmanip instructions to emitter ( #16832 )
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* riscv: Cleanup emitter, add bitmanip detect.
Better to encode using Funct7::ZERO, and obviously for SRA.
* riscv: Add bitmanip instructions to emitter.
2023-01-22 21:37:47 +01:00
82f0502b4e
riscv: Implement CPU feature detection.
2022-12-21 03:12:16 +00:00
9ac4931636
Fix get CPU & CPU Brand
2021-07-31 03:03:13 +10:00
bd8759853b
Fix ABI
2021-07-31 01:50:48 +10:00
0d0e2c44e0
Fix copied mips bugs
2021-07-29 07:47:09 +10:00
d452b0c1f7
No CPU part for RISC-V
2021-07-29 03:26:18 +10:00
d9a3741fcb
RISC-V CPU detect
2021-07-28 21:58:56 +10:00
Henrik Rydgård