 Henrik Rydgård
|
ba148e5ec7
|
JIT/IRJit: Delete an old "function preloading" experiment
This caused some confusion while trying to debug #20502
|
2025-06-11 15:45:18 +02:00 |
|
|
Henrik Rydgård
|
5526ef012c
|
Store IR instructions in a large arena vector instead of loosely in each block.
|
2024-06-07 09:28:27 +02:00 |
|
|
Unknown W. Brackets
|
9b2fa46861
|
IR: Add mini native jit MIPS block profiler.
|
2023-09-24 23:04:29 -07:00 |
|
|
Unknown W. Brackets
|
f9bf7de701
|
riscv: Use a single reg cache.
|
2023-08-20 12:42:11 -07:00 |
|
|
Unknown W. Brackets
|
b30daa5760
|
riscv: Centralize state of regcaches.
|
2023-08-15 21:51:38 -07:00 |
|
|
Unknown W. Brackets
|
2bb67db43c
|
riscv: Switch to the logBlocks model for disasm.
|
2023-08-13 10:37:21 -07:00 |
|
|
Unknown W. Brackets
|
fcc90095f7
|
riscv: Enable block linking.
|
2023-08-12 09:37:02 -07:00 |
|
|
Unknown W. Brackets
|
3757ebca2d
|
irjit: Invalidate/finalize target blocks.
Doesn't actually do anything yet, but adds plumbing.
|
2023-08-12 09:37:02 -07:00 |
|
|
Unknown W. Brackets
|
ad4cbbab8e
|
riscv: Don't cache mipState on backend.
Bad sign if we're trying to use it, anyway.
|
2023-08-08 23:17:32 -07:00 |
|
|
Unknown W. Brackets
|
93e3d35f5d
|
irjit: Move more to IRNativeBackend, split.
|
2023-08-06 00:16:43 -07:00 |
|
|
Unknown W. Brackets
|
691799a0ca
|
irjit: Centralize native jit compile dispatch.
|
2023-08-03 23:14:58 -07:00 |
|
|
Unknown W. Brackets
|
45d44c1d4f
|
riscv: Implement block debug interface.
This gives us the target disasm in jit compare, bloat, etc.
|
2023-07-30 14:21:43 -07:00 |
|
|
Henrik RydgårdandGitHub
|
b93275bb35
|
Merge pull request #17800 from unknownbrackets/riscv-jit
More RISC-V jit ops
|
2023-07-30 09:26:22 +02:00 |
|
|
Unknown W. Brackets
|
a5671bc716
|
riscv: Add simple debug log of missed ops.
|
2023-07-30 00:02:10 -07:00 |
|
|
Unknown W. Brackets
|
8d60c10a64
|
riscv: Use jit address offsets directly.
We'll have IR able to use block number or target offset.
|
2023-07-29 19:02:15 -07:00 |
|
|
Unknown W. Brackets
|
df2462b1d9
|
irjit: Implement ll/sc.
These occur more than I expected in LittleBigPlanet while loading.
|
2023-07-29 17:57:44 -07:00 |
|
|
Unknown W. Brackets
|
5122b0c78e
|
riscv: Cleanup unnecessary fcr31 func.
Don't need this, we use DYNAMIC.
|
2023-07-25 20:33:56 -07:00 |
|
|
Unknown W. Brackets
|
bb6fdd0246
|
riscv: Add floating point load/stores.
|
2023-07-25 20:33:56 -07:00 |
|
|
Unknown W. Brackets
|
7071884a47
|
riscv: Handle rounding mode and ctrl transfers.
|
2023-07-25 20:33:56 -07:00 |
|
|
Unknown W. Brackets
|
067a033dc0
|
riscv: Add FPU regcache.
|
2023-07-25 20:33:56 -07:00 |
|
|
Unknown W. Brackets
|
f7f7531500
|
riscv: Fix min/max normalization.
|
2023-07-23 18:01:00 -07:00 |
|
|
Unknown W. Brackets
|
34bfe93ea5
|
riscv: Fix block lookup issues.
|
2023-07-23 18:01:00 -07:00 |
|
|
Unknown W. Brackets
|
624caa2dea
|
riscv: Implement the simplest exits.
|
2023-07-23 18:01:00 -07:00 |
|
|
Unknown W. Brackets
|
165169eb31
|
riscv: Implement load and store ops.
|
2023-07-23 18:01:00 -07:00 |
|
|
Unknown W. Brackets
|
c2da7d18bb
|
riscv: Stub out more IR compilation categories.
|
2023-07-23 18:01:00 -07:00 |
|
|
Unknown W. Brackets
|
bf7a6eb2cd
|
riscv: Add jit for some initial instructions.
|
2023-07-23 18:01:00 -07:00 |
|
|
Unknown W. Brackets
|
4c1cc2dfdc
|
riscv: Add a register cache for jit.
Not yet actually used. Might be buggy.
|
2023-07-23 18:01:00 -07:00 |
|
|
Unknown W. Brackets
|
47b81985bd
|
riscv: Initial untested dispatcher.
The minimum to actually, probably, running code. Pretty slow.
|
2023-07-23 18:01:00 -07:00 |
|
|
Unknown W. Brackets
|
e271e43ec5
|
riscv: Initial staffolding for IR based jit.
|
2023-07-23 18:01:00 -07:00 |
|