83af54950f
Move more core-related stuff into Core.cpp/h
2024-12-08 11:54:58 +01:00
e01ca5b057
Logging API change (refactor) ( #19324 )
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* Rename LogType to Log
* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.
* Mac/ARM64 buildfix
* Do the same with the hle result log macros
* Rename the log names to mixed case while at it.
* iOS buildfix
* Qt buildfix attempt, ARM32 buildfix
2024-07-14 14:42:59 +02:00
9b2fa46861
IR: Add mini native jit MIPS block profiler.
2023-09-24 23:04:29 -07:00
0452b8b57a
riscv: Account for emuhack in JITBASEREG.
2023-09-03 13:29:05 -07:00
f9bf7de701
riscv: Use a single reg cache.
2023-08-20 12:42:11 -07:00
4b9011e475
riscv: Reduce call bloat using temps.
2023-08-08 23:17:32 -07:00
ad4cbbab8e
riscv: Don't cache mipState on backend.
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Bad sign if we're trying to use it, anyway.
2023-08-08 23:17:32 -07:00
93e3d35f5d
irjit: Move more to IRNativeBackend, split.
2023-08-06 00:16:43 -07:00
c24dca12bb
Build: Fix link issue for rv64 disasm.
2023-07-30 16:06:55 -07:00
f65b6fdb20
riscv: Remove incomplete block check.
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It shouldn't be necessary and bad things would happen anyway if it did.
2023-07-29 19:02:15 -07:00
8d60c10a64
riscv: Use jit address offsets directly.
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We'll have IR able to use block number or target offset.
2023-07-29 19:02:15 -07:00
7071884a47
riscv: Handle rounding mode and ctrl transfers.
2023-07-25 20:33:56 -07:00
34bfe93ea5
riscv: Fix block lookup issues.
2023-07-23 18:01:00 -07:00
5ed2f0d559
riscv: Implement logic ops.
2023-07-23 18:01:00 -07:00
720f868a10
riscv: Use R_RA as a temporary for calls.
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This is the most logical thing, since we're about to write it anyway.
2023-07-23 18:01:00 -07:00
1dfedde741
riscv: Avoid needless save/load around compile.
2023-07-23 18:01:00 -07:00
4c1cc2dfdc
riscv: Add a register cache for jit.
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Not yet actually used. Might be buggy.
2023-07-23 18:01:00 -07:00
47b81985bd
riscv: Initial untested dispatcher.
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The minimum to actually, probably, running code. Pretty slow.
2023-07-23 18:01:00 -07:00
Henrik Rydgård