1e57d8110f
Minor blockcache improvement
2026-02-25 00:52:25 +01:00
1c049b63d5
Throw in a safety check in JitBlockCache::DestroyBlock.
2026-02-19 00:30:39 +01:00
8897b5914a
Improve integrity checks in JIT (trying to catch an elusive crash)
2026-02-17 22:42:04 +01:00
1b0e701c87
Expose some more pointers in the ImDebugger UI
2026-02-17 22:40:00 +01:00
f0ba391a4e
Remove the whole concept of proxy blocks from the block cache, and experimental uses of it.
2026-02-17 09:40:27 +01:00
2797cfca56
Remove more vestiges of old experiments
2026-02-12 01:23:48 +01:00
44a2585753
Rename some function, remove an unused return value
2026-02-12 01:23:45 +01:00
d5444a7f46
Remove old rudimentary start at a MIPS->MIPS jit
2026-02-11 23:33:41 +01:00
b999c51a1a
Code cleanup. Don't use gpr.SetRegImm where all we do is write to a scratch register
2026-02-10 19:28:53 +01:00
4a8aeac38a
Jit: Remove unused x86-only feature continueBranches.
2026-01-29 17:41:57 +01:00
ed5a052258
Remove unused initial work for adding NEON support to ARM JITs.
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Our SIMD strategy for ARM is the JitUsingIR.
2026-01-29 17:41:57 +01:00
8631e77db2
Delete some outdated profiler integrations
2026-01-01 13:55:30 +01:00
1facc4d485
Remove obsolete hidden setting Browse
2025-11-04 23:39:56 +01:00
a170f40927
Qt buildfix
2025-10-10 08:45:09 -06:00
a72fc6f79c
Support showing (and sorting by) IR profiler info in the JIT viewer
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This will help future work on #19143 .
2025-10-09 17:02:52 -06:00
5751e202a5
Remove redundant .c_str()
2025-08-31 13:37:43 +02:00
1d910b81ff
loongarch: Add emitter, JIT and disassembler support for LoongArch64
2025-07-12 03:21:23 +08:00
ffb1e01e7e
Fix shutdown performance regression
2025-06-26 11:06:21 +02:00
6df9e513c1
Logging, comments and debugger fixes, plus simple dumping of the first block of streaming Atrac3
2025-06-25 01:08:47 +02:00
b51c5da003
Fix order of operations when clearing JitBlockCaches.
2025-06-12 10:05:19 +02:00
ba148e5ec7
JIT/IRJit: Delete an old "function preloading" experiment
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This caused some confusion while trying to debug #20502
2025-06-11 15:45:18 +02:00
0e3c1df9b3
Add a way to access the ImDebugger from the DevMenu
2024-11-21 15:48:18 +01:00
cf678a1aa6
JIT: Allow more blocks to be stored in the cache. Also, add margin to the IsFull check.
2024-10-28 17:02:03 +01:00
c1d6b62625
Add a couple of asserts to the JitBlockCache.
2024-10-23 13:23:38 +02:00
e01ca5b057
Logging API change (refactor) ( #19324 )
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* Rename LogType to Log
* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.
* Mac/ARM64 buildfix
* Do the same with the hle result log macros
* Rename the log names to mixed case while at it.
* iOS buildfix
* Qt buildfix attempt, ARM32 buildfix
2024-07-14 14:42:59 +02:00
0ea9120ca5
Add a stats view
2024-06-06 19:21:50 +02:00
294593f741
Fix IR profiling
2024-06-05 19:12:08 +02:00
3bb74ea9ad
Rework the JitCompare window to hold a list of blocks, and allow some filtering and browsing
2024-06-05 18:16:33 +02:00
ba1ced77c3
IRJit block profiling basics
2024-06-05 13:02:40 +02:00
f2837e3b55
JIT compare screen with IR blocks - fix some crashing issues
2024-05-26 14:10:50 +02:00
e75e7a0e43
Add an optimizeForInterpreter flag
2024-05-26 13:41:31 +02:00
17ecee1715
Fixed return copies from functions and const ref params
2024-04-02 18:37:00 +03:00
7e427e41d1
Remove a bunch of dead code from CoreTiming ("threadsafe" events)
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We haven't used these "threadsafe" events since we removed our first attempt
at GPU threading, so like 10 years, and maybe some experimentation in the
networking code according to some comments. It's unlikely that any
savestates that used these events would load anyway.
2024-01-16 09:06:03 +01:00
3deabaeb04
JitBlockCache: Add a debug assert
2024-01-15 23:28:59 +01:00
b871e76d05
[Core/Debugger/FileLoaders/FileSystems/MIPS] Using reserve if possible
2023-12-15 13:59:19 +03:00
4c0077fd84
Protect against weirdness in UnlinkBlocks (hopefully not needed after prev fix)
2023-09-27 12:31:17 +02:00
dd2b1ace88
BlockCache on ARM/ARM64: Allow two more exits
2023-09-26 19:44:05 +02:00
c0ee711cb9
In the FinalizeBlock assert, extract some more info
2023-09-26 13:37:40 +02:00
e7c0b41867
Improve an assert
2023-09-22 10:58:43 +02:00
3acbeb3073
Add an assert in JitBlockCache
2023-09-11 13:59:04 +02:00
1b756ff8c1
arm64jit: Add initial base for IR jit.
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This works, but very slowly at this point.
2023-09-03 12:14:28 -07:00
74e5e43fdc
jit: Skip known prefix writes.
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If we already know what's in memory and it's default, we can skip
overwriting with default values. This is common, actually.
2023-08-22 23:26:31 -07:00
622c69dbb9
x86jit: Expose option to select new IR based jit.
2023-08-20 22:28:54 -07:00
2e6dbab5fa
irjit: Add flag to prefer Vec4, use for add/sub.
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This will improve things when using SIMD.
2023-08-13 18:10:40 -07:00
fcc90095f7
riscv: Enable block linking.
2023-08-12 09:37:02 -07:00
0d0029fc9d
riscv: Add bitmanip ops to disasm.
2023-07-30 17:45:36 -07:00
9f917488c3
riscv: Fix PC in disassembly.
2023-07-30 14:19:28 -07:00
df2462b1d9
irjit: Implement ll/sc.
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These occur more than I expected in LittleBigPlanet while loading.
2023-07-29 17:57:44 -07:00
e271e43ec5
riscv: Initial staffolding for IR based jit.
2023-07-23 18:01:00 -07:00
9db9fec898
VFPU: Some micro-optimizations. Don't fall back to interpreter path for vexp/vlog/vrexp.
2023-06-04 11:28:33 +02:00
Henrik Rydgård