 Henrik Rydgård
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0c077acc74
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Do some include untangling, to limit the spread of the Windows.h include from SevenZipFileReader.h
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2026-03-27 14:34:18 -06:00 |
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Henrik Rydgård
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1a89c26dc0
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Warning fixes
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2024-10-03 18:19:11 +02:00 |
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Henrik Rydgård
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5526ef012c
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Store IR instructions in a large arena vector instead of loosely in each block.
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2024-06-07 09:28:27 +02:00 |
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Unknown W. Brackets
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685d2acffe
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x86jit: Retain old lanes when there's space.
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2023-09-24 17:31:25 -07:00 |
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Unknown W. Brackets
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88b6442527
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irjit: Add facility for native reg transfer.
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2023-09-24 16:28:29 -07:00 |
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Unknown W. Brackets
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9bac755491
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x86jit: Avoid pointerify if clobbered.
For x86, it's not worth it for one.
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2023-09-01 22:34:22 -07:00 |
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Unknown W. Brackets
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f10444eb42
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x86jit: Special case broadcast shuffles.
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2023-08-27 23:24:30 -07:00 |
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Unknown W. Brackets
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61a99b4bac
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x86jit: Implement trig/reciprocals.
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2023-08-27 23:24:30 -07:00 |
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Unknown W. Brackets
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363f2b68e1
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x86jit: Implement shifts.
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2023-08-25 00:01:03 -07:00 |
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Unknown W. Brackets
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07fa1ed573
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x86jit: Automatically flush incompatible regs.
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2023-08-21 21:16:54 -07:00 |
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Unknown W. Brackets
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db34b85107
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irjit: Allow flag-based allocation order.
Sometimes backends have needs, like XMM0/v0-only, or similar.
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2023-08-21 20:46:05 -07:00 |
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Henrik Rydgård
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629d46ef5b
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Merge pull request #17938 from unknownbrackets/riscv-centralize
Centralize IR regcache from RISC-V
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2023-08-20 23:47:02 +02:00 |
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Unknown W. Brackets
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36b6aa4728
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riscv: Allow GPR "SIMD" without FPR SIMD.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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6a75e6712e
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riscv: Use automapping for special cases too.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a190793ad2
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riscv: Simplify mapping for more instructions.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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e40ae60029
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riscv: Mark normalized32 after mapping.
It's less confusing to separate it.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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f9bf7de701
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riscv: Use a single reg cache.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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a23ade8f75
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riscv: Map IR regs based on metadata.
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
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2023-08-20 12:42:11 -07:00 |
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Unknown W. Brackets
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32d8f6196f
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irjit: Cut time flushing imm regs.
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2023-08-20 08:59:47 -07:00 |
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Unknown W. Brackets
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161465ab66
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riscv: Centralize register FlushAll().
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2023-08-19 21:30:03 -07:00 |
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Unknown W. Brackets
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f3d4bd8c11
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riscv: Centralize reg-as-pointer.
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2023-08-19 21:24:36 -07:00 |
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Unknown W. Brackets
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92f7374c89
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riscv: Centralize reg mapping itself.
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2023-08-19 16:15:49 -07:00 |
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Unknown W. Brackets
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718a1b3944
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riscv: Centralize MarkDirty flagging.
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2023-08-19 16:15:49 -07:00 |
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Unknown W. Brackets
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4e41f83ecc
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riscv: Centralize IR reg cache metadata checks.
These are all largely the same between backends.
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2023-08-17 23:03:31 -07:00 |
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Unknown W. Brackets
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ebab0e1591
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riscv: Centralize reg allocation.
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2023-08-17 18:50:33 -07:00 |
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Unknown W. Brackets
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b30daa5760
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riscv: Centralize state of regcaches.
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2023-08-15 21:51:38 -07:00 |
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Unknown W. Brackets
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5f9a8fd1a1
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irjit: Rename IRRegCache to IRImmRegCache.
For clarity, since it's not a native regcache.
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2023-08-08 23:05:14 -07:00 |
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Unknown W. Brackets
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b2d3c750f1
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irjit: Define a specific IRReg type.
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2023-07-23 18:01:00 -07:00 |
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Henrik Rydgard
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d4480d50fd
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jit-ir: Less instructions cause flushing in constant propagation.
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2016-05-08 23:25:08 +02:00 |
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Henrik Rydgard
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14df39d7c9
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Fix IRTEMP clash bug. Add more cases to the constant propagation pass.
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2016-05-08 10:36:37 +02:00 |
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Henrik Rydgard
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09969c0156
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Use the regcache in a new (incomplete) pass, PropagateConstants.
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2016-05-08 01:06:07 +02:00 |
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Henrik Rydgard
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d399c4a470
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Initial commit for IRJit
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2016-05-07 13:58:29 +02:00 |
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