85e7ff7ac3
Target->Native renaming. More intuitive (at least to me)
2024-07-22 01:24:34 +02:00
e01ca5b057
Logging API change (refactor) ( #19324 )
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* Rename LogType to Log
* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.
* Mac/ARM64 buildfix
* Do the same with the hle result log macros
* Rename the log names to mixed case while at it.
* iOS buildfix
* Qt buildfix attempt, ARM32 buildfix
2024-07-14 14:42:59 +02:00
6ebec02f05
Fix crash in JITIR after disassembly improvement.
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Fixes #19292
2024-06-22 15:16:27 +02:00
5526ef012c
Store IR instructions in a large arena vector instead of loosely in each block.
2024-06-07 09:28:27 +02:00
4e0761b104
irjit: Fix regcache disable for FPRs.
2023-09-30 15:54:54 -07:00
685d2acffe
x86jit: Retain old lanes when there's space.
2023-09-24 17:31:25 -07:00
88b6442527
irjit: Add facility for native reg transfer.
2023-09-24 16:28:29 -07:00
24da5a3ba2
irjit: Small simplification to regcache.
2023-09-23 22:00:49 -07:00
9439a43323
riscv: Correct an overlap case, fix assert.
2023-09-03 13:29:57 -07:00
9bac755491
x86jit: Avoid pointerify if clobbered.
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For x86, it's not worth it for one.
2023-09-01 22:34:22 -07:00
d5a51da95e
x86jit: Fix pointer modify when masked.
2023-08-30 22:04:26 -07:00
742dc0a0c7
x86jit: Fix vec4 clobber issue.
2023-08-30 22:04:25 -07:00
1bfa054a41
irjit: Correct GetFPRLaneCount().
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Oops, this was just wrong...
2023-08-28 21:09:56 -07:00
0ecfb6b112
Merge pull request #17992 from unknownbrackets/x86-jit-float
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x86jit: Implement trig instructions, couple other FPU
2023-08-28 10:20:38 +02:00
f10444eb42
x86jit: Special case broadcast shuffles.
2023-08-27 23:24:30 -07:00
61a99b4bac
x86jit: Implement trig/reciprocals.
2023-08-27 23:24:30 -07:00
7d8dc0f8ab
irjit: Detect clobber in lane change.
2023-08-27 12:27:05 -07:00
d1a30334bf
x86jit: Implement multiplies.
2023-08-25 00:01:03 -07:00
363f2b68e1
x86jit: Implement shifts.
2023-08-25 00:01:03 -07:00
efaf14a19f
x86jit: Fix spilling zero register.
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We can't flush it, but it's likely not to get "clobbered".
2023-08-22 23:29:13 -07:00
c397e2e4da
x86jit: Flush reg if dirty on map as ptr.
2023-08-22 23:29:13 -07:00
edcb156897
x86jit: Add Vec4 and Float load/store.
2023-08-22 10:39:46 +02:00
07fa1ed573
x86jit: Automatically flush incompatible regs.
2023-08-21 21:16:54 -07:00
db34b85107
irjit: Allow flag-based allocation order.
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Sometimes backends have needs, like XMM0/v0-only, or similar.
2023-08-21 20:46:05 -07:00
5045cf012e
x86jit: Fix flushing of zero register.
2023-08-20 22:28:54 -07:00
629d46ef5b
Merge pull request #17938 from unknownbrackets/riscv-centralize
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Centralize IR regcache from RISC-V
2023-08-20 23:47:02 +02:00
36b6aa4728
riscv: Allow GPR "SIMD" without FPR SIMD.
2023-08-20 12:42:11 -07:00
6a75e6712e
riscv: Use automapping for special cases too.
2023-08-20 12:42:11 -07:00
a190793ad2
riscv: Simplify mapping for more instructions.
2023-08-20 12:42:11 -07:00
e40ae60029
riscv: Mark normalized32 after mapping.
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It's less confusing to separate it.
2023-08-20 12:42:11 -07:00
f9bf7de701
riscv: Use a single reg cache.
2023-08-20 12:42:11 -07:00
a23ade8f75
riscv: Map IR regs based on metadata.
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Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
2023-08-20 12:42:11 -07:00
32d8f6196f
irjit: Cut time flushing imm regs.
2023-08-20 08:59:47 -07:00
161465ab66
riscv: Centralize register FlushAll().
2023-08-19 21:30:03 -07:00
f3d4bd8c11
riscv: Centralize reg-as-pointer.
2023-08-19 21:24:36 -07:00
92f7374c89
riscv: Centralize reg mapping itself.
2023-08-19 16:15:49 -07:00
718a1b3944
riscv: Centralize MarkDirty flagging.
2023-08-19 16:15:49 -07:00
4e41f83ecc
riscv: Centralize IR reg cache metadata checks.
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These are all largely the same between backends.
2023-08-17 23:03:31 -07:00
ebab0e1591
riscv: Centralize reg allocation.
2023-08-17 18:50:33 -07:00
b30daa5760
riscv: Centralize state of regcaches.
2023-08-15 21:51:38 -07:00
5f9a8fd1a1
irjit: Rename IRRegCache to IRImmRegCache.
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For clarity, since it's not a native regcache.
2023-08-08 23:05:14 -07:00
a32889d3ca
irjit: Consistently dirty vfpuctrl in IR.
2023-08-06 08:36:19 -07:00
b2d3c750f1
irjit: Define a specific IRReg type.
2023-07-23 18:01:00 -07:00
8f23025209
irjit: Add tests for IR passes.
2022-07-24 11:35:54 -07:00
d4480d50fd
jit-ir: Less instructions cause flushing in constant propagation.
2016-05-08 23:25:08 +02:00
5dbac165f4
Qt, gcc, and Symbian buildfixes.
2016-05-08 14:10:07 -07:00
98113edbd4
More simplify pass
2016-05-08 11:29:11 +02:00
14df39d7c9
Fix IRTEMP clash bug. Add more cases to the constant propagation pass.
2016-05-08 10:36:37 +02:00
09969c0156
Use the regcache in a new (incomplete) pass, PropagateConstants.
2016-05-08 01:06:07 +02:00
4acf85aa06
It's kind of starting to run
2016-05-07 17:37:19 +02:00
Henrik Rydgård