f0ba391a4e
Remove the whole concept of proxy blocks from the block cache, and experimental uses of it.
2026-02-17 09:40:27 +01:00
ba148e5ec7
JIT/IRJit: Delete an old "function preloading" experiment
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This caused some confusion while trying to debug #20502
2025-06-11 15:45:18 +02:00
02e767866a
fix compiler warnings
2025-02-22 14:15:15 +01:00
7992ff4627
Make CBreakpoints an object
2024-11-25 00:22:53 +01:00
08b20ce9c8
Buildfix for std::back_inserter
2024-09-14 20:16:17 +03:00
ff5877e993
Renamed the IR instruction, new UI button added
2024-09-14 19:46:05 +03:00
a26afb4c2f
Implemented the trace reconstruction + bugs fixed
2024-09-14 19:46:05 +03:00
e3b09bea59
Ported the MIPSLogger's UI + basic integration of MIPSTracer
2024-09-14 19:46:05 +03:00
e01ca5b057
Logging API change (refactor) ( #19324 )
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* Rename LogType to Log
* Explicitly use the Log:: enum when logging. Allows for autocomplete when editing.
* Mac/ARM64 buildfix
* Do the same with the hle result log macros
* Rename the log names to mixed case while at it.
* iOS buildfix
* Qt buildfix attempt, ARM32 buildfix
2024-07-14 14:42:59 +02:00
0080f71ca4
Implement FPU rounding mode support in the IR interpreter for x86/x64
2024-06-19 18:09:38 +02:00
bd0beb68a4
Add new IR optimization pass, OptimizeLoadsAfterStores
2024-06-07 19:32:37 +02:00
da88011805
Specialize a few arithmetic instructions for the interpreter.
2024-06-07 19:32:37 +02:00
e75e7a0e43
Add an optimizeForInterpreter flag
2024-05-26 13:41:31 +02:00
053831bf4d
HLE: Add mechanics for sliced replacements.
2023-12-16 09:08:58 -08:00
7fb67bbb1f
irjit: Fix breakpoints with block linking.
2023-09-17 09:33:16 -07:00
daa0586641
Merge pull request #18059 from unknownbrackets/arm64-ir-jit
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arm64jit: Add initial base for IR jit
2023-09-03 22:33:24 +02:00
259734bd47
irjit: Fix likely delay slot breakpoints.
2023-09-03 12:27:10 -07:00
e1a1f56f4c
irjit: Cleanup breakpoint ops.
2023-09-03 12:27:10 -07:00
1b756ff8c1
arm64jit: Add initial base for IR jit.
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This works, but very slowly at this point.
2023-09-03 12:14:28 -07:00
5f84887dea
irjit: Add a pass to keep Vec4s in Vec4s.
2023-09-01 22:35:59 -07:00
75e20af886
x86jit: Fix default prefix on core switch.
2023-08-28 21:09:56 -07:00
74e5e43fdc
jit: Skip known prefix writes.
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If we already know what's in memory and it's default, we can skip
overwriting with default values. This is common, actually.
2023-08-22 23:26:31 -07:00
46101581c0
Core: Cleanup disasm buffer usage.
2023-04-29 09:07:25 -07:00
90517ace59
irjit: Validate alignment in slow memory mode.
2022-08-21 13:24:10 -07:00
6715f41410
irjit: Add constructs for validing mem access.
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Basically to allow slow/fast memory to work with IR, including for
alignment checks.
2022-08-21 13:01:23 -07:00
b43698a13d
Remove most instances of base/logging.h from Common, Core, GPU, more
2020-08-15 19:08:44 +02:00
b8342fb8ec
SaveState: Rename ChunkFile files to Serialize.
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Makes more sense and less weird than ChunkFileDoMap, etc.
2020-08-10 08:04:05 +00:00
4b4e3432cd
SaveState: Split Do() into a separate header.
2020-08-10 08:03:41 +00:00
ab809bd19e
jit: Apply hasSetRounding at compile time.
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Otherwise, the block will be executed with the wrong rounding mode the
first time rounding is set. This could be important if it was set for a
single operation.
This is only a problem the first time it's set.
2018-04-01 10:36:16 -07:00
4a32ec3102
Merge pull request #10516 from unknownbrackets/irjit-lwr
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irjit: Optimize out more temps and lwl/lwr operations
2018-01-10 09:11:10 +01:00
b11f00cead
irjit: Combine lwl/lwr and swl/swr, like before.
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Still want to inline the operation, because the backend shouldn't have to
redo it every time, and we want the temps cleaned up if possible.
2018-01-07 21:05:58 -08:00
97674b80bd
irjit: Skip preloading blocks with jump to 0.
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These will be changed before executing anyway.
2018-01-06 17:23:53 -08:00
bc541bd020
irjit: Encode downcount directly as a constant.
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Simpler this way, now.
2018-01-03 23:32:31 -08:00
cffb2d61a7
irjit: Embed constant inside IRInst.
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This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
2018-01-03 23:24:04 -08:00
b11858d9a0
irjit: Properly account for delay slots in size.
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Otherwise we think blocks are 4 bytes too short, which can affect
invalidation.
2018-01-01 22:54:40 -08:00
b37ba9e599
irjit: Add options for compile/optimize steps.
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This way the backend can set flags for the type of IR it wants. It's
seems too complex to combine certain things like lwl/lwr in a pass.
2018-01-01 08:38:12 -08:00
905d2c2da6
irjit: Cleanup some invalid op handling.
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And log blocks the same way as other backends.
2018-01-01 08:38:11 -08:00
8ffb0101fe
jit: Report blocks with uneaten VFPU prefixes.
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There may be options to avoid, like continuing these blocks, especially if
they're likely or something.
2018-01-01 08:38:10 -08:00
4578c3cb54
jit-ir: Implement memory breakpoints.
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These generally work, but likely delay slots will make downcount slightly
off, and won't resume when you hit run again without manually stepping
through them.
2016-07-02 16:38:30 -07:00
1df08518ae
jit-ir: Implement basic icache clear.
2016-07-01 17:27:24 -07:00
6fb34d0bee
jit-ir: Add initial breakpoint support.
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No memory breakpoints yet, and cache isn't cleared yet so these don't work
exactly the way you might expect...
2016-07-01 17:15:57 -07:00
5534fba72c
jit-ir: Add load/store reorder and merge passes.
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Can do more in merge, potentially. Maybe it's not useful...
2016-05-17 21:24:13 -07:00
fff898b526
Log the block when "uneaten prefix" happens
2016-05-16 00:05:03 +02:00
efc8a8e353
Hack to make Symbian build.
2016-05-13 23:56:17 -07:00
91a6cf5e44
Add a couple more passes (2-op, optimize f<->v fp moves)
2016-05-13 20:14:03 +02:00
f636b2a315
Minor build and other fixes
2016-05-13 19:31:27 +02:00
29ed8d2201
jit-ir: ExitToReg doesn't write to registers.
2016-05-12 18:34:27 -07:00
99468c6fc1
jit-ir: Optimize out unused temp regs.
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This way, if constants have made the temp obsolete (common with ins, for
example), it won't even get set anymore.
2016-05-12 18:30:53 -07:00
850d0abc91
IR: More VFPU. Support normal fp compares.
2016-05-12 20:16:15 +02:00
558bb197c7
More VFPU
2016-05-09 23:47:56 +02:00
Henrik Rydgård