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ARM JIT: Add and simplify some half-word load/store instructions.

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Sacha committed 2013-02-27 17:09:47 +10:00
1 parent 76433a4fad
commit fe8b80c12e
3 files changed
+30 -16
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Core/MIPS/ARM/ArmCompLoadStore.cpp
+10 -13
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@@ -94,12 +94,9 @@ namespace MIPSComp
}
switch (o)
{
case 37: //R(rt) = ReadMem16(addr); break; //lhu
Comp_Generic(op);
return;
case 35: //R(rt) = ReadMem32(addr); //lw
case 35: //R(rt) = ReadMem32(addr); break; //lw
case 36: //R(rt) = ReadMem8 (addr); break; //lbu
case 37: //R(rt) = ReadMem16(addr); break; //lhu
if (g_Config.bFastMemory) {
if (gpr.IsImm(rs)) {
// We can compute the full address at compile time. Kickass.
@@ -113,8 +110,10 @@ namespace MIPSComp
if (o == 35) {
LDR(gpr.R(rt), R11, R0, true, true);
} else if (o == 36) {
LDRB(gpr.R(rt), R11, R0, true, true);
} else if (o == 37) {
ADD(R0, R0, R11); // TODO: Merge with next instruction
LDRB(gpr.R(rt), R0);
LDRH(gpr.R(rt), R0);
}
} else {
Comp_Generic(op);
@@ -122,11 +121,8 @@ namespace MIPSComp
}
break;
case 40: //WriteMem8 (addr, R(rt)); break; //sb
case 41: //WriteMem16(addr, R(rt)); break; //sh
Comp_Generic(op);
return;
case 40: //sb
case 43: //WriteMem32(addr, R(rt)); break; //sw
if (g_Config.bFastMemory) {
if (gpr.IsImm(rs)) {
@@ -141,15 +137,16 @@ namespace MIPSComp
if (o == 43) {
STR(R0, gpr.R(rt), R11, true, true);
} else if (o == 40) {
ADD(R0, R0, R11);
STRB(R0, gpr.R(rt));
STRB(R0, gpr.R(rt), R11, true, true);
} else if (o == 41) {
ADD(R0, R0, R11); // TODO: Merge with next instruction
STRH(gpr.R(rt), R0);
}
} else {
Comp_Generic(op);
return;
}
break;
// break;
/*
case 34: //lwl
{