From 742dc0a0c7e8c300e573f1b7b9a2bedbe4296eae Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Wed, 30 Aug 2023 22:02:40 -0700 Subject: [PATCH 1/2] x86jit: Fix vec4 clobber issue. --- Core/MIPS/IR/IRRegCache.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Core/MIPS/IR/IRRegCache.cpp b/Core/MIPS/IR/IRRegCache.cpp index 30b4131aea..89dff99b8f 100644 --- a/Core/MIPS/IR/IRRegCache.cpp +++ b/Core/MIPS/IR/IRRegCache.cpp @@ -443,7 +443,7 @@ IRNativeReg IRNativeRegCacheBase::FindBestToSpill(MIPSLoc type, MIPSMap flags, b // Note: mipsReg points to the lowest numbered IRReg. bool canClobber = true; for (IRReg m = mipsReg + 1; mr[m].nReg == nreg && m < IRREG_INVALID && canClobber; ++m) - canClobber = getUsage(mipsReg) == IRUsage::CLOBBERED; + canClobber = getUsage(m) == IRUsage::CLOBBERED; // Okay, if all can be clobbered, we're good to go. if (canClobber) { From d5a51da95e287c5316127ed141195d5fc51db20d Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Wed, 30 Aug 2023 22:02:59 -0700 Subject: [PATCH 2/2] x86jit: Fix pointer modify when masked. --- Core/MIPS/IR/IRRegCache.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Core/MIPS/IR/IRRegCache.cpp b/Core/MIPS/IR/IRRegCache.cpp index 89dff99b8f..8c7b6a437f 100644 --- a/Core/MIPS/IR/IRRegCache.cpp +++ b/Core/MIPS/IR/IRRegCache.cpp @@ -1058,9 +1058,14 @@ void IRNativeRegCacheBase::MapNativeReg(MIPSLoc type, IRNativeReg nreg, IRReg fi case MIPSLoc::REG_AS_PTR: _assert_msg_(lanes == 1, "Should have flushed before getting here"); _assert_msg_(type == MIPSLoc::REG, "Should have flushed this reg already"); +#ifndef MASKED_PSP_MEMORY AdjustNativeRegAsPtr(nreg, false); +#endif for (int i = 0; i < lanes; ++i) mr[first + i].loc = type; +#ifdef MASKED_PSP_MEMORY + LoadNativeReg(nreg, first, lanes); +#endif break; case MIPSLoc::REG: