From 23e3916a77dfa9fdc62477fb89c073859e80e104 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sun, 30 Nov 2014 17:42:02 -0800 Subject: [PATCH 1/3] x86jit: Fix a stupid typo. --- Core/MIPS/x86/RegCacheFPU.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Core/MIPS/x86/RegCacheFPU.cpp b/Core/MIPS/x86/RegCacheFPU.cpp index e6cbe416d9..da98db8d82 100644 --- a/Core/MIPS/x86/RegCacheFPU.cpp +++ b/Core/MIPS/x86/RegCacheFPU.cpp @@ -439,7 +439,7 @@ X64Reg FPURegCache::LoadRegsVS(const u8 *v, int n) { } else if (n == 4) { if (!vregs[v[2]].location.IsSimpleReg(xr2)) emit->MOVSS(xr2, vregs[v[2]].location); - if (!vregs[v[3]].location.IsSimpleReg(xr2)) + if (!vregs[v[3]].location.IsSimpleReg(xr1)) emit->MOVSS(xr1, vregs[v[3]].location); emit->UNPCKLPS(xr2, Gen::R(xr1)); emit->MOVSS(xr1, vregs[v[1]].location); From 9cfe801075eec4cf6172e0cf181f07287d806012 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sun, 30 Nov 2014 17:42:43 -0800 Subject: [PATCH 2/3] x86jit: Ensure we don't sequence temps+regs. --- Core/MIPS/x86/RegCacheFPU.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Core/MIPS/x86/RegCacheFPU.cpp b/Core/MIPS/x86/RegCacheFPU.cpp index da98db8d82..d25e0a48be 100644 --- a/Core/MIPS/x86/RegCacheFPU.cpp +++ b/Core/MIPS/x86/RegCacheFPU.cpp @@ -611,9 +611,9 @@ void FPURegCache::StoreFromRegister(int i) { if (mri[j] == -1) { break; } - if (mri[j] - 32 >= 128 && mri[j] == mri[j - 1] + 1) { + if (mri[j] - 32 >= 128 && mri[j - 1] - 32 >= 128 && mri[j] == mri[j - 1] + 1) { seq++; - } else if (mri[j] - 32 < 128 && voffset[mri[j] - 32] == voffset[mri[j - 1] - 32] + 1) { + } else if (mri[j] - 32 < 128 && mri[j - 1] - 32 < 128 && voffset[mri[j] - 32] == voffset[mri[j - 1] - 32] + 1) { seq++; } else { break; From 48b3a292d71091d6694c4e9b897e5725ba5e42ea Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sun, 30 Nov 2014 17:43:07 -0800 Subject: [PATCH 3/3] x86jit: Add more sanity checks. --- Core/MIPS/x86/RegCacheFPU.cpp | 53 +++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/Core/MIPS/x86/RegCacheFPU.cpp b/Core/MIPS/x86/RegCacheFPU.cpp index d25e0a48be..fcea3084ac 100644 --- a/Core/MIPS/x86/RegCacheFPU.cpp +++ b/Core/MIPS/x86/RegCacheFPU.cpp @@ -852,6 +852,34 @@ void FPURegCache::Invariant() const { #endif } +static int GetMRMtx(int mr) { + if (mr < 32) + return -1; + if (mr >= 128 + 32) + return -1; + return ((mr - 32) >> 2) & 7; +} + +static int GetMRRow(int mr) { + if (mr < 32) + return -1; + if (mr >= 128 + 32) + return -1; + return ((mr - 32) >> 0) & 3; +} + +static int GetMRCol(int mr) { + if (mr < 32) + return -1; + if (mr >= 128 + 32) + return -1; + return ((mr - 32) >> 5) & 3; +} + +static bool IsMRTemp(int mr) { + return mr >= 128 + 32; +} + int FPURegCache::SanityCheck() const { for (int i = 0; i < NUM_MIPS_FPRS; i++) { const MIPSCachedFPReg &mr = regs[i]; @@ -892,6 +920,11 @@ int FPURegCache::SanityCheck() const { return 8; bool hasMoreRegs = hasReg; + int mtx = -2; + int row = -2; + int col = -2; + bool rowMatched = true; + bool colMatched = true; for (int j = 0; j < 4; ++j) { if (xr.mipsRegs[j] == -1) { hasMoreRegs = false; @@ -904,6 +937,26 @@ int FPURegCache::SanityCheck() const { const MIPSCachedFPReg &mr = regs[xr.mipsRegs[j]]; if (!mr.location.IsSimpleReg(X64Reg(i))) return 10; + + if (!IsMRTemp(xr.mipsRegs[j])) { + if (mtx == -2) + mtx = GetMRMtx(xr.mipsRegs[j]); + else if (mtx != GetMRMtx(xr.mipsRegs[j])) + return 11; + + if (row == -2) + row = GetMRRow(xr.mipsRegs[j]); + else if (row != GetMRRow(xr.mipsRegs[j])) + rowMatched = false; + + if (col == -2) + col = GetMRCol(xr.mipsRegs[j]); + else if (col != GetMRCol(xr.mipsRegs[j])) + colMatched = false; + } + } + if (!rowMatched && !colMatched) { + return 12; } }