diff --git a/Core/MIPS/MIPS.cpp b/Core/MIPS/MIPS.cpp
index 2108cde51b..528f189011 100644
--- a/Core/MIPS/MIPS.cpp
+++ b/Core/MIPS/MIPS.cpp
@@ -77,7 +77,6 @@ void MIPSState::Reset()
 	SetWriteMask(b);
 
 	pc = 0;
-	prevPC = 0;
 	hi = 0;
 	lo = 0;
 	fpcond = 0;
@@ -157,7 +156,6 @@ void MIPSState::RunLoopUntil(u64 globalTicks)
 						break;
 					}
 #endif
-					prevPC = pc;
 					if (inDelaySlot)
 					{
 						MIPSInterpret(op);
@@ -172,6 +170,7 @@ void MIPSState::RunLoopUntil(u64 globalTicks)
 						MIPSInterpret(op);
 					}
 
+					/*
 					if (!Memory::IsValidAddress(pc))
 					{
 						pc = pc;
@@ -179,9 +178,12 @@ void MIPSState::RunLoopUntil(u64 globalTicks)
 					if (r[MIPS_REG_RA] != 0 && !Memory::IsValidAddress(r[MIPS_REG_RA]))
 					{
 					//	pc = pc;
-					}
+					}*/
 					if (inDelaySlot)
+					{
+						CoreTiming::downcount -= 1;
 						goto again;
+					}
 				}
 
 				CoreTiming::downcount -= 1;
@@ -190,11 +192,9 @@ void MIPSState::RunLoopUntil(u64 globalTicks)
 					DEBUG_LOG(CPU, "Hit the max ticks, bailing : %llu, %llu", globalTicks, CoreTiming::GetTicks());
 					break;
 				}
-
 			}
 
 			CoreTiming::Advance();
-			// if (exceptions) checkExceptions();
 			if (CoreTiming::GetTicks() > globalTicks)
 			{
 				DEBUG_LOG(CPU, "Hit the max ticks, bailing : %llu, %llu", globalTicks, CoreTiming::GetTicks());
diff --git a/Core/MIPS/MIPS.h b/Core/MIPS/MIPS.h
index 48d86499c3..2d4e4ca4aa 100644
--- a/Core/MIPS/MIPS.h
+++ b/Core/MIPS/MIPS.h
@@ -112,7 +112,6 @@ public:
 
 	u32 pc;
 	u32 nextPC;
-	u32 prevPC;
 	u32 hi;
 	u32 lo;
 
diff --git a/Core/MIPS/MIPSTables.cpp b/Core/MIPS/MIPSTables.cpp
index c8940bfb49..80bf608052 100644
--- a/Core/MIPS/MIPSTables.cpp
+++ b/Core/MIPS/MIPSTables.cpp
@@ -225,8 +225,8 @@ const MIPSInstruction tableSpecial[64] = /// 000000 ...... ...... .......... xxx
 	{-2},
 	INSTR("slt",  &Jit::Comp_RType3, Dis_RType3, Int_RType3,IN_RS|IN_RT|OUT_RD),
 	INSTR("sltu", &Jit::Comp_RType3, Dis_RType3, Int_RType3,IN_RS|IN_RT|OUT_RD),
-	INSTR("max",  &Jit::Comp_Generic, Dis_RType3, Int_RType3,IN_RS|IN_RT|OUT_RD),
-	INSTR("min",  &Jit::Comp_Generic, Dis_RType3, Int_RType3,IN_RS|IN_RT|OUT_RD),
+	INSTR("max",  &Jit::Comp_RType3, Dis_RType3, Int_RType3,IN_RS|IN_RT|OUT_RD),
+	INSTR("min",  &Jit::Comp_RType3, Dis_RType3, Int_RType3,IN_RS|IN_RT|OUT_RD),
 	INSTR("msub",  &Jit::Comp_Generic, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|OUT_OTHER),
 	INSTR("msubu", &Jit::Comp_Generic, Dis_MulDivType, Int_MulDivType, IN_RS|IN_RT|OUT_OTHER),
 
diff --git a/Core/MIPS/x86/CompALU.cpp b/Core/MIPS/x86/CompALU.cpp
index c86551baf2..674d685c16 100644
--- a/Core/MIPS/x86/CompALU.cpp
+++ b/Core/MIPS/x86/CompALU.cpp
@@ -161,17 +161,17 @@ namespace MIPSComp
 		case 33: //R(rd) = R(rs) + R(rt);		break; //addu
 			CompTriArith(op, &XEmitter::ADD);
 			break;
-		case 134: //R(rd) = R(rs) - R(rt);		break; //sub
-		case 135:
+		case 34: //R(rd) = R(rs) - R(rt);		break; //sub
+		case 35:
 			CompTriArith(op, &XEmitter::SUB);
 			break;
-		case 136: //R(rd) = R(rs) & R(rt);		break; //and
+		case 36: //R(rd) = R(rs) & R(rt);		break; //and
 			CompTriArith(op, &XEmitter::AND);
 			break;
-		case 137: //R(rd) = R(rs) | R(rt);		break; //or
+		case 37: //R(rd) = R(rs) | R(rt);		break; //or
 			CompTriArith(op, &XEmitter::OR);
 			break;
-		case 138: //R(rd) = R(rs) ^ R(rt);		break; //xor
+		case 38: //R(rd) = R(rs) ^ R(rt);		break; //xor
 			CompTriArith(op, &XEmitter::XOR);
 			break;
 
diff --git a/Core/MemMapFunctions.cpp b/Core/MemMapFunctions.cpp
index 78f8262f0e..561e7fb93e 100644
--- a/Core/MemMapFunctions.cpp
+++ b/Core/MemMapFunctions.cpp
@@ -82,7 +82,7 @@ inline void ReadFromHardware(T &var, const u32 address)
 	}
 	else
 	{
-		WARN_LOG(MEMMAP, "ReadFromHardware: Invalid address %08x	PC %08x PPC %08x LR %08x", address, currentMIPS->pc, currentMIPS->prevPC, currentMIPS->r[MIPS_REG_RA]);
+		WARN_LOG(MEMMAP, "ReadFromHardware: Invalid address %08x	PC %08x LR %08x", address, currentMIPS->pc, currentMIPS->r[MIPS_REG_RA]);
 		if (!g_Config.bIgnoreBadMemAccess) {
 			// TODO: Not sure what the best way to crash is...
 			exit(0);