diff --git a/Core/MIPS/PPC/PpcAsm.cpp b/Core/MIPS/PPC/PpcAsm.cpp
index f32ff874b9..4d8405f171 100644
--- a/Core/MIPS/PPC/PpcAsm.cpp
+++ b/Core/MIPS/PPC/PpcAsm.cpp
@@ -121,23 +121,7 @@ void Jit::GenerateFixedCode() {
 	INFO_LOG(HLE, "enterCode: 0x%08p", enterCode);	
 	INFO_LOG(HLE, "GetBasePtr: 0x%08p", GetBasePtr());
 
-	// Write Prologue (setup stack frame etc ...)
-	// Save Lr
-	MFLR(R12);
-
-	// Save regs
-	u32 regSize = 8; // 4 in 32bit system
-	u32 stackFrameSize = 32*32;//(35 - 12) * regSize;
-
-	for(int i = 14; i < 32; i ++) {
-		STD((PPCReg)i, R1, -((33 - i) * regSize));
-	}
-
-	// Save r12
-	STW(R12, R1, -0x8);
-
-	// allocate stack
-	STWU(R1, R1, -stackFrameSize);
+	Prologue();
 	
 	// Map fixed register
 	MOVI2R(BASEREG,	(u32)Memory::base);
@@ -289,20 +273,7 @@ void Jit::GenerateFixedCode() {
 	// mips->downcount = DCNTREG
 	SaveDowncount(DCNTREG);
 
-	// Write Epilogue (restore stack frame, return)
-	// free stack
-	ADDI(R1, R1, stackFrameSize);	
-
-	// Restore regs
-	for(int i = 14; i < 32; i ++) {
-		LD((PPCReg)i, R1, -((33 - i) * regSize));
-	}
-
-	// recover r12 (LR saved register)
-	LWZ (R12, R1, -0x8);
-
-	// Restore Lr
-	MTLR(R12);
+	Epilogue();
 
 	// Go back to caller
 	BLR();
diff --git a/Core/MIPS/PPC/PpcCompAlu.cpp b/Core/MIPS/PPC/PpcCompAlu.cpp
index 10fd3c84a4..bb8ddc9cea 100644
--- a/Core/MIPS/PPC/PpcCompAlu.cpp
+++ b/Core/MIPS/PPC/PpcCompAlu.cpp
@@ -10,25 +10,108 @@
 #include "ppcEmitter.h"
 #include "PpcJit.h"
 
-#include <ppcintrinsics.h>
+using namespace MIPSAnalyst;
+#define _RS ((op>>21) & 0x1F)
+#define _RT ((op>>16) & 0x1F)
+#define _RD ((op>>11) & 0x1F)
+#define _FS ((op>>11) & 0x1F)
+#define _FT ((op>>16) & 0x1F)
+#define _FD ((op>>6 ) & 0x1F)
+#define _SA ((op>>6 ) & 0x1F)
+#define _POS	((op>>6 ) & 0x1F)
+#define _SIZE ((op>>11 ) & 0x1F)
 
-using namespace PpcGen;
+// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
+// Currently known non working ones should have DISABLE.
 
-extern volatile CoreState coreState;
+//#define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
+#define CONDITIONAL_DISABLE ;
+#define DISABLE { Comp_Generic(op); return; }
 
 namespace MIPSComp
 {
 
-void Jit::Comp_IType(u32 op) {
-	Comp_Generic(op);
-}
+	static u32 EvalOr(u32 a, u32 b) { return a | b; }
+	static u32 EvalEor(u32 a, u32 b) { return a ^ b; }
+	static u32 EvalAnd(u32 a, u32 b) { return a & b; }
+	static u32 EvalAdd(u32 a, u32 b) { return a + b; }
+	static u32 EvalSub(u32 a, u32 b) { return a - b; }
+
+	void Jit::Comp_IType(u32 op)
+	{
+		CONDITIONAL_DISABLE;
+		s32 simm = (s32)(s16)(op & 0xFFFF);  // sign extension
+		u32 uimm = op & 0xFFFF;
+		u32 suimm = (u32)(s32)simm;
+
+		int rt = _RT;
+		int rs = _RS;
+
+		// noop, won't write to ZERO.
+		if (rt == 0)
+			return;
+
+		switch (op >> 26) 
+		{
+			
+		case 8:	// same as addiu?
+		case 9:	// R(rt) = R(rs) + simm; break;	//addiu
+			{
+				if (gpr.IsImm(rs)) {
+					gpr.SetImm(rt, gpr.GetImm(rs) + simm);
+				} else {
+					gpr.MapDirtyIn(rt, rs);
+					ADDI(gpr.R(rt), gpr.R(rs), simm);
+				}
+				break;
+			}
+		case 15: // R(rt) = uimm << 16;	 //lui
+			gpr.SetImm(rt, uimm << 16);
+			break;
+		default:
+			Comp_Generic(op);
+			break;
+		}
+	}
 
 void Jit::Comp_RType2(u32 op) {
 	Comp_Generic(op);
 }
 
 void Jit::Comp_RType3(u32 op) {
+#if 0
+	CONDITIONAL_DISABLE;
+	int rt = _RT;
+	int rs = _RS;
+	int rd = _RD;
+
+	// noop, won't write to ZERO.
+	if (rd == 0)
+		return;
+
+	switch (op & 63) 
+	{
+	
+	case 32: //R(rd) = R(rs) + R(rt);           break; //add
+	case 33: //R(rd) = R(rs) + R(rt);           break; //addu
+		// Some optimized special cases
+		if (gpr.IsImm(rs) && gpr.GetImm(rs) == 0) {
+			gpr.MapDirtyIn(rd, rt);
+			MR(gpr.R(rd), gpr.R(rt));
+		} else if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0) {
+			gpr.MapDirtyIn(rd, rs);
+			MR(gpr.R(rd), gpr.R(rs));
+		} else {
+			CompType3(rd, rs, rt, &ARMXEmitter::ADD, &EvalAdd);
+		}
+		break;
+	default:
+		Comp_Generic(op);
+		break;
+	}
+#else
 	Comp_Generic(op);
+#endif
 }
 
 void Jit::Comp_ShiftType(u32 op) {
diff --git a/Core/MIPS/PPC/PpcCompLoadStore.cpp b/Core/MIPS/PPC/PpcCompLoadStore.cpp
index 36001d17b5..936d51135b 100644
--- a/Core/MIPS/PPC/PpcCompLoadStore.cpp
+++ b/Core/MIPS/PPC/PpcCompLoadStore.cpp
@@ -23,8 +23,8 @@
 // All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
 // Currently known non working ones should have DISABLE.
 
-#define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
-//#define CONDITIONAL_DISABLE ;
+//#define CONDITIONAL_DISABLE { Comp_Generic(op); return; }
+#define CONDITIONAL_DISABLE ;
 #define DISABLE { Comp_Generic(op); return; }
 
 using namespace PpcGen;
@@ -33,48 +33,14 @@ namespace MIPSComp
 {
 
 void Jit::SetRegToEffectiveAddress(PpcGen::PPCReg r, int rs, s16 offset) {
-	if (offset == 0xa24) {
-		printf("Rs : %02x\n", rs);
-		Break();
-	}
-	/*
 	if (offset) {
-		bool negated;
-		if (TryMakeOperand2_AllowNegation(offset, op2, &negated)) {
-			if (!negated)
-				ADD(R0, gpr.R(rs), op2);
-			else
-				SUB(R0, gpr.R(rs), op2);
-		} else {
-			// Try to avoid using MOVT
-			if (offset < 0) {
-				MOVI2R(R0, (u32)(-offset));
-				SUB(R0, gpr.R(rs), R0);
-			} else {
-				MOVI2R(R0, (u32)offset);
-				ADD(R0, gpr.R(rs), R0);
-			}
-		}
-		BIC(R0, R0, Operand2(0xC0, 4));   // &= 0x3FFFFFFF
-	} else {
-		BIC(R0, gpr.R(rs), Operand2(0xC0, 4));   // &= 0x3FFFFFFF
-	}
-	*/
-	if (offset) {
-		// optimize ...
-		
-		//MOVI2R(SREG, (u32)offset);
-		//ADD(SREG, gpr.R(rs), SREG);
 		ADDI(SREG, gpr.R(rs), offset);
-		
-		//Break();
 		RLWINM(SREG, SREG, 0, 2, 31); // &= 0x3FFFFFFF
 	} else {
 		RLWINM(SREG, gpr.R(rs), 0, 2, 31); // &= 0x3FFFFFFF
 	}
 		
 }
-
 void Jit::Comp_ITypeMem(u32 op) {
 	CONDITIONAL_DISABLE;
 		int offset = (signed short)(op&0xFFFF);
@@ -101,6 +67,7 @@ void Jit::Comp_ITypeMem(u32 op) {
 		case 40: //sb
 		case 41: //sh
 		case 43: //sw
+
 			if (gpr.IsImm(rs) && Memory::IsValidAddress(iaddr)) {
 				// We can compute the full address at compile time. Kickass.
 				u32 addr = iaddr & 0x3FFFFFFF;
@@ -112,17 +79,13 @@ void Jit::Comp_ITypeMem(u32 op) {
 				load ? gpr.MapDirtyIn(rt, rs) : gpr.MapInIn(rt, rs);
 				
 				SetRegToEffectiveAddress(SREG, rs, offset);
-				//DISABLE;
 			}
 			switch (o)
 			{
 			// Load
 			case 32:  //lb
-				Break();
-
-				LBZ(gpr.R(rt), BASEREG, SREG); 
+				LBZX(gpr.R(rt), BASEREG, SREG); 
 				EXTSB(gpr.R(rt), gpr.R(rt));
-				
 				break;
 			case 33:  //lh
 				LHBRX(gpr.R(rt), BASEREG, SREG); 
@@ -132,34 +95,23 @@ void Jit::Comp_ITypeMem(u32 op) {
 				LWBRX(gpr.R(rt), BASEREG, SREG); 
 				break;
 			case 36: //lbu
-				LBZ (gpr.R(rt), BASEREG, SREG); 
+				LBZX (gpr.R(rt), BASEREG, SREG); 
 				break;
 			case 37: //lhu
 				LHBRX (gpr.R(rt), BASEREG, SREG); 
 				break;
 			// Store
 			case 40:  //sb
-				Break();
-				STB (gpr.R(rt), BASEREG, SREG); 
+				STBX (gpr.R(rt), BASEREG, SREG); 
 				break;
 			case 41: //sh
-				STHBRX(gpr.R(rt), BASEREG, SREG); 
+				STHBRX(gpr.R(rt), BASEREG, SREG); 		
 				break;
 			case 43: //sw
 				STWBRX(gpr.R(rt), BASEREG, SREG); 
 				break;
 			}
-			/*
-			if (doCheck) {
-				if (load) {
-					SetCC(CC_EQ);
-					MOVI2R(gpr.R(rt), 0);
-				}
-				SetCC(CC_AL);
-			}
-			*/
 			break;
-			/*
 		case 34: //lwl
 		case 38: //lwr
 			load = true;
@@ -182,11 +134,9 @@ void Jit::Comp_ITypeMem(u32 op) {
 
 			DISABLE; // Disabled until crashes are resolved.
 			break;
-			*/
 		default:
 			Comp_Generic(op);
 			return ;
 		}
-
 	}
 }
diff --git a/Core/MIPS/PPC/PpcJit.cpp b/Core/MIPS/PPC/PpcJit.cpp
index 24b1443e6d..46b0c6c025 100644
--- a/Core/MIPS/PPC/PpcJit.cpp
+++ b/Core/MIPS/PPC/PpcJit.cpp
@@ -117,6 +117,8 @@ void Jit::WriteDownCount(int offset)
 }
 
 void Jit::Comp_Generic(u32 op) {
+	FlushAll();
+
 	// basic jit !!
 	MIPSInterpretFunc func = MIPSGetInterpretFunc(op);
 	if (func)