From 87434e8dada87a768de7c402b168d68291141647 Mon Sep 17 00:00:00 2001 From: raven02 Date: Sun, 18 Aug 2013 21:36:31 +0800 Subject: [PATCH 001/237] softgpu : Fix depth issue in FF Type-0 --- GPU/Software/Rasterizer.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/GPU/Software/Rasterizer.cpp b/GPU/Software/Rasterizer.cpp index c7741663de..04f89a6329 100644 --- a/GPU/Software/Rasterizer.cpp +++ b/GPU/Software/Rasterizer.cpp @@ -750,7 +750,8 @@ void DrawTriangle(const VertexData& v0, const VertexData& v1, const VertexData& } // TODO: Is it safe to ignore gstate.isDepthTestEnabled() when clear mode is enabled? - if ((gstate.isDepthTestEnabled() && !gstate.isModeThrough()) || gstate.isModeClear()) { + // TODO: Verify that through mode does not disable depth testing + if (gstate.isDepthTestEnabled() || gstate.isModeClear()) { // TODO: Verify that stencil op indeed needs to be applied here even if stencil testing is disabled if (!DepthTestPassed(p.x, p.y, z)) { ApplyStencilOp(gstate.getStencilOpZFail(), p.x, p.y); From 690c11e590321ef14d5fda7808af38ad4984f28b Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 11:33:32 -0700 Subject: [PATCH 002/237] Oops, quick warning fix. --- Core/HLE/sceKernelEventFlag.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Core/HLE/sceKernelEventFlag.cpp b/Core/HLE/sceKernelEventFlag.cpp index fc36df8f95..f1a81ea92b 100644 --- a/Core/HLE/sceKernelEventFlag.cpp +++ b/Core/HLE/sceKernelEventFlag.cpp @@ -654,7 +654,7 @@ int sceKernelPollEventFlag(SceUID id, u32 bits, u32 wait, u32 outBitsPtr) // Can't wait on 0, it never matches. if (bits == 0) { - DEBUG_LOG(HLE, "sceKernelPollEventFlag(%i, %08x, %i, %08x, %08x): bad pattern", id, bits, wait, outBitsPtr); + DEBUG_LOG(HLE, "sceKernelPollEventFlag(%i, %08x, %i, %08x): bad pattern", id, bits, wait, outBitsPtr); return SCE_KERNEL_ERROR_EVF_ILPAT; } @@ -669,23 +669,23 @@ int sceKernelPollEventFlag(SceUID id, u32 bits, u32 wait, u32 outBitsPtr) if (e->waitingThreads.size() > 0 && (e->nef.attr & PSP_EVENT_WAITMULTIPLE) == 0) { - DEBUG_LOG(HLE, "SCE_KERNEL_ERROR_EVF_MULTI=sceKernelPollEventFlag(%i, %08x, %i, %08x, %08x)", id, bits, wait, outBitsPtr); + DEBUG_LOG(HLE, "SCE_KERNEL_ERROR_EVF_MULTI=sceKernelPollEventFlag(%i, %08x, %i, %08x)", id, bits, wait, outBitsPtr); return SCE_KERNEL_ERROR_EVF_MULTI; } // No match - return that, this is polling, not waiting. - DEBUG_LOG(HLE, "SCE_KERNEL_ERROR_EVF_COND=sceKernelPollEventFlag(%i, %08x, %i, %08x, %08x)", id, bits, wait, outBitsPtr); + DEBUG_LOG(HLE, "SCE_KERNEL_ERROR_EVF_COND=sceKernelPollEventFlag(%i, %08x, %i, %08x)", id, bits, wait, outBitsPtr); return SCE_KERNEL_ERROR_EVF_COND; } else { - DEBUG_LOG(HLE, "0=sceKernelPollEventFlag(%i, %08x, %i, %08x, %08x)", id, bits, wait, outBitsPtr); + DEBUG_LOG(HLE, "0=sceKernelPollEventFlag(%i, %08x, %i, %08x)", id, bits, wait, outBitsPtr); return 0; } } else { - DEBUG_LOG(HLE, "sceKernelPollEventFlag(%i, %08x, %i, %08x, %08x): invalid event flag", id, bits, wait, outBitsPtr); + DEBUG_LOG(HLE, "sceKernelPollEventFlag(%i, %08x, %i, %08x): invalid event flag", id, bits, wait, outBitsPtr); return error; } } From d7c58956d53535040dff700e200741e5d3d419d2 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 11:33:40 -0700 Subject: [PATCH 003/237] Android buildfix. --- UI/CwCheatScreen.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/UI/CwCheatScreen.cpp b/UI/CwCheatScreen.cpp index 5297c6c339..51e90400d2 100644 --- a/UI/CwCheatScreen.cpp +++ b/UI/CwCheatScreen.cpp @@ -138,7 +138,7 @@ UI::EventReturn CwCheatScreen::OnImportCheat(UI::EventParams ¶ms) bool finished = false, skip = false; std::vector newList; #ifdef ANDROID - is.open (g_Config.memCardDirectory + "PSP/Cheats/cheat.db"; + is.open(g_Config.memCardDirectory + "PSP/Cheats/cheat.db"); #else is.open("cheats/cheat.db"); #endif From 55e02369a58dea48a4c3632787d77e294a4ece7d Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 11:33:49 -0700 Subject: [PATCH 004/237] Workaround an ICE in some versions of gcc. --- GPU/Software/Rasterizer.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/GPU/Software/Rasterizer.cpp b/GPU/Software/Rasterizer.cpp index 62a9137d12..7693957c98 100644 --- a/GPU/Software/Rasterizer.cpp +++ b/GPU/Software/Rasterizer.cpp @@ -726,7 +726,8 @@ void DrawTriangle(const VertexData& v0, const VertexData& v1, const VertexData& // TODO: Fogging // TODO: Is that the correct way to interpolate? - u16 z = (u16)(((float)v0.screenpos.z * w0 + (float)v1.screenpos.z * w1 + (float)v2.screenpos.z * w2) / (w0+w1+w2)); + // With the (u32), this causes an ICE in some versions of gcc. + u16 z = (u16)(u32)(((float)v0.screenpos.z * w0 + (float)v1.screenpos.z * w1 + (float)v2.screenpos.z * w2) / (w0+w1+w2)); // Depth range test if (!gstate.isModeThrough()) From c141e94fe9b433282c9a9f6527d0eef52f8448d6 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 10:20:07 -0700 Subject: [PATCH 005/237] Use gstate.* accessors in a few more places. --- GPU/GLES/Framebuffer.cpp | 2 +- GPU/GLES/GLES_GPU.cpp | 2 +- GPU/GLES/Spline.cpp | 2 +- GPU/GLES/StateMapping.cpp | 2 +- GPU/GLES/TextureCache.cpp | 4 ++-- GPU/GLES/TransformPipeline.cpp | 15 ++++++++------- GPU/GLES/TransformPipeline.h | 2 +- GPU/GPUState.h | 1 + GPU/Software/SoftGpu.cpp | 2 +- GPU/Software/TransformUnit.cpp | 4 ++-- GPU/Software/TransformUnit.h | 2 +- 11 files changed, 20 insertions(+), 18 deletions(-) diff --git a/GPU/GLES/Framebuffer.cpp b/GPU/GLES/Framebuffer.cpp index 8af1994c49..6d7f7a8e02 100644 --- a/GPU/GLES/Framebuffer.cpp +++ b/GPU/GLES/Framebuffer.cpp @@ -475,7 +475,7 @@ void FramebufferManager::SetRenderFrameBuffer() { // As there are no clear "framebuffer width" and "framebuffer height" registers, // we need to infer the size of the current framebuffer somehow. Let's try the viewport. - GEBufferFormat fmt = static_cast(gstate.framebufpixformat & 3); + GEBufferFormat fmt = gstate.FrameBufFormat(); int drawing_width, drawing_height; GuessDrawingSize(drawing_width, drawing_height); diff --git a/GPU/GLES/GLES_GPU.cpp b/GPU/GLES/GLES_GPU.cpp index 2f9391eecb..b9b73cd8a6 100644 --- a/GPU/GLES/GLES_GPU.cpp +++ b/GPU/GLES/GLES_GPU.cpp @@ -729,7 +729,7 @@ void GLES_GPU::ExecuteOp(u32 op, u32 diff) { int sp_vcount = (data >> 8) & 0xFF; int sp_utype = (data >> 16) & 0x3; int sp_vtype = (data >> 18) & 0x3; - int patchPrim = gstate.patchprimitive & 3; + GEPatchPrimType patchPrim = gstate.getPatchPrimitiveType(); transformDraw_.SubmitSpline(control_points, indices, sp_ucount, sp_vcount, sp_utype, sp_vtype, patchPrim, gstate.vertType); } break; diff --git a/GPU/GLES/Spline.cpp b/GPU/GLES/Spline.cpp index 83c1614072..9e033078d7 100644 --- a/GPU/GLES/Spline.cpp +++ b/GPU/GLES/Spline.cpp @@ -92,7 +92,7 @@ void CopyTriangle(u8 *&dest, u8 *v1, u8 *v2, u8 * v3, int vertexSize) { dest += vertexSize; } -void TransformDrawEngine::SubmitSpline(void* control_points, void* indices, int count_u, int count_v, int type_u, int type_v, u32 prim_type, u32 vertex_type) +void TransformDrawEngine::SubmitSpline(void* control_points, void* indices, int count_u, int count_v, int type_u, int type_v, GEPatchPrimType prim_type, u32 vertex_type) { Flush(); diff --git a/GPU/GLES/StateMapping.cpp b/GPU/GLES/StateMapping.cpp index 54ec9358eb..37ddbe6bfc 100644 --- a/GPU/GLES/StateMapping.cpp +++ b/GPU/GLES/StateMapping.cpp @@ -330,7 +330,7 @@ void TransformDrawEngine::ApplyDrawState(int prim) { renderHeightFactor = renderHeight / 272.0f; } - bool throughmode = (gstate.vertType & GE_VTYPE_THROUGH_MASK) != 0; + bool throughmode = gstate.isModeThrough(); // Scissor int scissorX1 = gstate.getScissorX1(); diff --git a/GPU/GLES/TextureCache.cpp b/GPU/GLES/TextureCache.cpp index 3a7b55ab4c..1f10637a1d 100644 --- a/GPU/GLES/TextureCache.cpp +++ b/GPU/GLES/TextureCache.cpp @@ -550,8 +550,8 @@ static const GLuint MagFiltGL[2] = { void TextureCache::UpdateSamplingParams(TexCacheEntry &entry, bool force) { int minFilt = gstate.texfilter & 0x7; int magFilt = (gstate.texfilter>>8) & 1; - bool sClamp = gstate.texwrap & 1; - bool tClamp = (gstate.texwrap>>8) & 1; + bool sClamp = gstate.isTexCoordClampedS(); + bool tClamp = gstate.isTexCoordClampedT(); bool noMip = (gstate.texlevel & 0xFFFFFF) == 0x000001 || (gstate.texlevel & 0xFFFFFF) == 0x100001 ; // Fix texlevel at 0 diff --git a/GPU/GLES/TransformPipeline.cpp b/GPU/GLES/TransformPipeline.cpp index cac49d7f9d..de3e423aca 100644 --- a/GPU/GLES/TransformPipeline.cpp +++ b/GPU/GLES/TransformPipeline.cpp @@ -150,7 +150,7 @@ private: }; Lighter::Lighter() { - doShadeMapping_ = (gstate.texmapmode & 0x3) == 2; + doShadeMapping_ = gstate.getUVGenMode() == GE_TEXMAP_ENVIRONMENT_MAP; materialEmissive.GetFromRGB(gstate.materialemissive); materialEmissive.a = 0.0f; globalAmbient.GetFromRGB(gstate.ambientcolor); @@ -677,16 +677,17 @@ void TransformDrawEngine::SoftwareTransformAndDraw( ((clearColor & 0xFF0000) >> 16) / 255.0f, ((clearColor & 0xFF000000) >> 24) / 255.0f, }; - int target = 0; - if ((gstate.clearmode >> 8) & 3) target |= GL_COLOR_BUFFER_BIT | GL_STENCIL_BUFFER_BIT; - if ((gstate.clearmode >> 10) & 1) target |= GL_DEPTH_BUFFER_BIT; - bool colorMask = (gstate.clearmode >> 8) & 1; - bool alphaMask = (gstate.clearmode >> 9) & 1; + bool colorMask = gstate.isClearModeColorMask(); + bool alphaMask = gstate.isClearModeAlphaMask(); glstate.colorMask.set(colorMask, colorMask, colorMask, alphaMask); glstate.stencilTest.set(false); glstate.scissorTest.set(false); - bool depthMask = (gstate.clearmode >> 10) & 1; + bool depthMask = gstate.isClearModeDepthMask(); + + int target = 0; + if (colorMask || alphaMask) target |= GL_COLOR_BUFFER_BIT | GL_STENCIL_BUFFER_BIT; + if (depthMask) target |= GL_DEPTH_BUFFER_BIT; glClearColor(col[0], col[1], col[2], col[3]); #ifdef USING_GLES2 diff --git a/GPU/GLES/TransformPipeline.h b/GPU/GLES/TransformPipeline.h index 7fea4f640d..f80c25bf2c 100644 --- a/GPU/GLES/TransformPipeline.h +++ b/GPU/GLES/TransformPipeline.h @@ -98,7 +98,7 @@ public: virtual ~TransformDrawEngine(); void SubmitPrim(void *verts, void *inds, int prim, int vertexCount, u32 vertexType, int forceIndexType, int *bytesRead); void DrawBezier(int ucount, int vcount); - void SubmitSpline(void* control_points, void* indices, int count_u, int count_v, int type_u, int type_v, u32 prim_type, u32 vertex_type); + void SubmitSpline(void* control_points, void* indices, int count_u, int count_v, int type_u, int type_v, GEPatchPrimType prim_type, u32 vertex_type); void DecodeVerts(); void SetShaderManager(ShaderManager *shaderManager) { diff --git a/GPU/GPUState.h b/GPU/GPUState.h index f63424d31a..4d5cee44d1 100644 --- a/GPU/GPUState.h +++ b/GPU/GPUState.h @@ -225,6 +225,7 @@ struct GPUgstate bool isClearModeDepthWriteEnabled() const { return (clearmode&0x400) != 0; } bool isClearModeColorMask() const { return (clearmode&0x100) != 0; } bool isClearModeAlphaMask() const { return (clearmode&0x200) != 0; } + bool isClearModeDepthMask() const { return (clearmode&0x400) != 0; } u32 getClearModeColorMask() const { return ((clearmode&0x100) ? 0xFFFFFF : 0) | ((clearmode&0x200) ? 0xFF000000 : 0); } // TODO: Different convention than getColorMask, confusing! // Blend diff --git a/GPU/Software/SoftGpu.cpp b/GPU/Software/SoftGpu.cpp index 756fbad877..a3ff3945d5 100644 --- a/GPU/Software/SoftGpu.cpp +++ b/GPU/Software/SoftGpu.cpp @@ -363,7 +363,7 @@ void SoftGPU::ExecuteOp(u32 op, u32 diff) break; } - TransformUnit::SubmitSpline(control_points, indices, sp_ucount, sp_vcount, sp_utype, sp_vtype, gstate.patchprimitive&3, gstate.vertType); + TransformUnit::SubmitSpline(control_points, indices, sp_ucount, sp_vcount, sp_utype, sp_vtype, gstate.getPatchPrimitiveType(), gstate.vertType); DEBUG_LOG(G3D,"DL DRAW SPLINE: %i x %i, %i x %i", sp_ucount, sp_vcount, sp_utype, sp_vtype); } break; diff --git a/GPU/Software/TransformUnit.cpp b/GPU/Software/TransformUnit.cpp index b76d8fc10c..1de4c23617 100644 --- a/GPU/Software/TransformUnit.cpp +++ b/GPU/Software/TransformUnit.cpp @@ -102,7 +102,7 @@ static VertexData ReadVertex(VertexReader& vreader) float pos[3]; vreader.ReadPos(pos); - if (!gstate.isModeClear() && gstate.textureMapEnable && vreader.hasUV()) { + if (!gstate.isModeClear() && gstate.isTextureMapEnabled() && vreader.hasUV()) { float uv[2]; vreader.ReadUV(uv); vertex.texturecoords = Vec2(uv[0], uv[1]); @@ -186,7 +186,7 @@ struct SplinePatch { int type; }; -void TransformUnit::SubmitSpline(void* control_points, void* indices, int count_u, int count_v, int type_u, int type_v, u32 prim_type, u32 vertex_type) +void TransformUnit::SubmitSpline(void* control_points, void* indices, int count_u, int count_v, int type_u, int type_v, GEPatchPrimType prim_type, u32 vertex_type) { VertexDecoder vdecoder; vdecoder.SetVertexType(vertex_type); diff --git a/GPU/Software/TransformUnit.h b/GPU/Software/TransformUnit.h index 32ee05ee40..b36cfb49c0 100644 --- a/GPU/Software/TransformUnit.h +++ b/GPU/Software/TransformUnit.h @@ -115,6 +115,6 @@ public: static DrawingCoords ScreenToDrawing(const ScreenCoords& coords); static ScreenCoords DrawingToScreen(const DrawingCoords& coords); - static void SubmitSpline(void* control_points, void* indices, int count_u, int count_v, int type_u, int type_v, u32 prim_type, u32 vertex_type); + static void SubmitSpline(void* control_points, void* indices, int count_u, int count_v, int type_u, int type_v, GEPatchPrimType prim_type, u32 vertex_type); static void SubmitPrimitive(void* vertices, void* indices, u32 prim_type, int vertex_count, u32 vertex_type); }; From 6227fe0754734ccd45ae335d57fd72013ba48c4a Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 10:20:31 -0700 Subject: [PATCH 006/237] Add some reporting of spline issues. --- GPU/GLES/GLES_GPU.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/GPU/GLES/GLES_GPU.cpp b/GPU/GLES/GLES_GPU.cpp index b9b73cd8a6..b685d410fb 100644 --- a/GPU/GLES/GLES_GPU.cpp +++ b/GPU/GLES/GLES_GPU.cpp @@ -714,14 +714,14 @@ void GLES_GPU::ExecuteOp(u32 op, u32 diff) { void *indices = NULL; if ((gstate.vertType & GE_VTYPE_IDX_MASK) != GE_VTYPE_IDX_NONE) { if (!Memory::IsValidAddress(gstate_c.indexAddr)) { - ERROR_LOG(G3D, "Bad index address %08x!", gstate_c.indexAddr); + ERROR_LOG_REPORT(G3D, "Bad index address %08x!", gstate_c.indexAddr); break; } indices = Memory::GetPointer(gstate_c.indexAddr); } if (gstate.getPatchPrimitiveType() != GE_PATCHPRIM_TRIANGLES) { - ERROR_LOG(G3D, "Unsupported patch primitive %x", gstate.patchprimitive&3); + ERROR_LOG_REPORT(G3D, "Unsupported patch primitive %x", gstate.patchprimitive&3); break; } From 0a217a12541fb3d7ed1e0b0fbfc92a2355a46053 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 10:41:45 -0700 Subject: [PATCH 007/237] Use accessors better for block transfers. --- GPU/GLES/GLES_GPU.cpp | 22 +++++++------- GPU/GPUState.h | 13 ++++++++ GPU/GeDisasm.cpp | 20 +++++++----- GPU/Null/NullGpu.cpp | 8 ++--- GPU/Software/SoftGpu.cpp | 66 +++++++++++----------------------------- 5 files changed, 58 insertions(+), 71 deletions(-) diff --git a/GPU/GLES/GLES_GPU.cpp b/GPU/GLES/GLES_GPU.cpp index b685d410fb..82cd951b2d 100644 --- a/GPU/GLES/GLES_GPU.cpp +++ b/GPU/GLES/GLES_GPU.cpp @@ -1300,22 +1300,22 @@ void GLES_GPU::DoBlockTransfer() { // // etc.... - u32 srcBasePtr = (gstate.transfersrc & 0xFFFFF0) | ((gstate.transfersrcw & 0xFF0000) << 8); - u32 srcStride = gstate.transfersrcw & 0x3F8; + u32 srcBasePtr = gstate.getTransferSrcAddress(); + u32 srcStride = gstate.getTransferSrcStride(); - u32 dstBasePtr = (gstate.transferdst & 0xFFFFF0) | ((gstate.transferdstw & 0xFF0000) << 8); - u32 dstStride = gstate.transferdstw & 0x3F8; + u32 dstBasePtr = gstate.getTransferDstAddress(); + u32 dstStride = gstate.getTransferDstStride(); - int srcX = gstate.transfersrcpos & 0x3FF; - int srcY = (gstate.transfersrcpos >> 10) & 0x3FF; + int srcX = gstate.getTransferSrcX(); + int srcY = gstate.getTransferSrcY(); - int dstX = gstate.transferdstpos & 0x3FF; - int dstY = (gstate.transferdstpos >> 10) & 0x3FF; + int dstX = gstate.getTransferDstX(); + int dstY = gstate.getTransferDstY(); - int width = (gstate.transfersize & 0x3FF) + 1; - int height = ((gstate.transfersize >> 10) & 0x3FF) + 1; + int width = gstate.getTransferWidth(); + int height = gstate.getTransferHeight(); - int bpp = (gstate.transferstart & 1) ? 4 : 2; + int bpp = gstate.getTransferBpp(); DEBUG_LOG(G3D, "Block transfer: %08x/%x -> %08x/%x, %ix%ix%i (%i,%i)->(%i,%i)", srcBasePtr, srcStride, dstBasePtr, dstStride, width, height, bpp, srcX, srcY, dstX, dstY); diff --git a/GPU/GPUState.h b/GPU/GPUState.h index 4d5cee44d1..377f0638e4 100644 --- a/GPU/GPUState.h +++ b/GPU/GPUState.h @@ -356,6 +356,19 @@ struct GPUgstate GEPatchPrimType getPatchPrimitiveType() const { return static_cast(patchprimitive & 3); } + // Transfers + u32 getTransferSrcAddress() const { return (transfersrc & 0xFFFFF0) | ((transfersrcw & 0xFF0000) << 8); } + u32 getTransferSrcStride() const { return transfersrcw & 0x3F8; } + int getTransferSrcX() const { return (transfersrcpos >> 0) & 0x3FF; } + int getTransferSrcY() const { return (transfersrcpos >> 10) & 0x3FF; } + u32 getTransferDstAddress() const { return (transferdst & 0xFFFFF0) | ((transferdstw & 0xFF0000) << 8); } + u32 getTransferDstStride() const { return transferdstw & 0x3F8; } + int getTransferDstX() const { return (transferdstpos >> 0) & 0x3FF; } + int getTransferDstY() const { return (transferdstpos >> 10) & 0x3FF; } + int getTransferWidth() const { return ((transfersize >> 0) & 0x3FF) + 1; } + int getTransferHeight() const { return ((transfersize >> 10) & 0x3FF) + 1; } + int getTransferBpp() const { return (transferstart & 1) ? 4 : 2; } + // Real data in the context ends here }; diff --git a/GPU/GeDisasm.cpp b/GPU/GeDisasm.cpp index e7e34f7864..8c4b92aeeb 100644 --- a/GPU/GeDisasm.cpp +++ b/GPU/GeDisasm.cpp @@ -437,7 +437,10 @@ void GeDisassembleOp(u32 pc, u32 op, u32 prev, char *buffer) { case GE_CMD_TRANSFERSRC: { - sprintf(buffer, "Block transfer src: %06x", data); + if (data & 0xF) + sprintf(buffer, "Block transfer src: %06x (extra: %x)", data & ~0xF, data & 0xF); + else + sprintf(buffer, "Block transfer src: %06x", data); // Nothing to do, the next one prints } break; @@ -445,7 +448,7 @@ void GeDisassembleOp(u32 pc, u32 op, u32 prev, char *buffer) { case GE_CMD_TRANSFERSRCW: { u32 xferSrc = (gstate.transfersrc & 0x00FFFFFF) | ((data & 0xFF0000) << 8); - u32 xferSrcW = gstate.transfersrcw & 1023; + u32 xferSrcW = data & 0x3FF; if (data & ~0xFF03FF) sprintf(buffer, "Block transfer src: %08x W: %i (extra %x)", xferSrc, xferSrcW, data); else @@ -456,14 +459,17 @@ void GeDisassembleOp(u32 pc, u32 op, u32 prev, char *buffer) { case GE_CMD_TRANSFERDST: { // Nothing to do, the next one prints - sprintf(buffer, "Block transfer dst: %06x", data); + if (data & 0xF) + sprintf(buffer, "Block transfer dst: %06x (extra: %x)", data & ~0xF, data & 0xF); + else + sprintf(buffer, "Block transfer dst: %06x", data); } break; case GE_CMD_TRANSFERDSTW: { u32 xferDst = (gstate.transferdst & 0x00FFFFFF) | ((data & 0xFF0000) << 8); - u32 xferDstW = gstate.transferdstw & 1023; + u32 xferDstW = data & 0x3FF; if (data & ~0xFF03FF) sprintf(buffer, "Block transfer dest: %08x W: %i (extra %x)", xferDst, xferDstW, data); else @@ -505,10 +511,10 @@ void GeDisassembleOp(u32 pc, u32 op, u32 prev, char *buffer) { } case GE_CMD_TRANSFERSTART: // Orphis calls this TRXKICK - if (data) - sprintf(buffer, "Block transfer start: %x", data); + if (data & ~1) + sprintf(buffer, "Block transfer start: %d (extra %x)", data & 1, data & ~1); else - sprintf(buffer, "Block transfer start"); + sprintf(buffer, "Block transfer start: %d", data); break; case GE_CMD_TEXSIZE0: diff --git a/GPU/Null/NullGpu.cpp b/GPU/Null/NullGpu.cpp index 3543ad37b1..14761a89ea 100644 --- a/GPU/Null/NullGpu.cpp +++ b/GPU/Null/NullGpu.cpp @@ -282,8 +282,8 @@ void NullGPU::ExecuteOp(u32 op, u32 diff) case GE_CMD_TRANSFERSRCW: { - u32 xferSrc = gstate.transfersrc | ((data&0xFF0000)<<8); - u32 xferSrcW = gstate.transfersrcw & 1023; + u32 xferSrc = (gstate.transfersrc & 0x00FFFFFF) | ((data & 0xFF0000) << 8); + u32 xferSrcW = data & 0x3FF; DEBUG_LOG(G3D,"Block Transfer Src: %08x W: %i", xferSrc, xferSrcW); break; } @@ -291,8 +291,8 @@ void NullGPU::ExecuteOp(u32 op, u32 diff) case GE_CMD_TRANSFERDSTW: { - u32 xferDst= gstate.transferdst | ((data&0xFF0000)<<8); - u32 xferDstW = gstate.transferdstw & 1023; + u32 xferDst = (gstate.transferdst & 0x00FFFFFF) | ((data & 0xFF0000) << 8); + u32 xferDstW = data & 0x3FF; DEBUG_LOG(G3D,"Block Transfer Dest: %08x W: %i", xferDst, xferDstW); break; } diff --git a/GPU/Software/SoftGpu.cpp b/GPU/Software/SoftGpu.cpp index a3ff3945d5..972066b455 100644 --- a/GPU/Software/SoftGpu.cpp +++ b/GPU/Software/SoftGpu.cpp @@ -549,67 +549,36 @@ void SoftGPU::ExecuteOp(u32 op, u32 diff) } break; -//case GE_CMD_TRANSFERSRC: - + // Don't need to do anything, just state for transferstart. + case GE_CMD_TRANSFERSRC: case GE_CMD_TRANSFERSRCW: - { - u32 xferSrc = gstate.transfersrc | ((data&0xFF0000)<<8); - u32 xferSrcW = gstate.transfersrcw & 1023; - DEBUG_LOG(G3D,"Block Transfer Src: %08x W: %i", xferSrc, xferSrcW); - break; - } -// case GE_CMD_TRANSFERDST: - + case GE_CMD_TRANSFERDST: case GE_CMD_TRANSFERDSTW: - { - u32 xferDst= gstate.transferdst | ((data&0xFF0000)<<8); - u32 xferDstW = gstate.transferdstw & 1023; - DEBUG_LOG(G3D,"Block Transfer Dest: %08x W: %i", xferDst, xferDstW); - break; - } - case GE_CMD_TRANSFERSRCPOS: - { - u32 x = (data & 1023)+1; - u32 y = ((data>>10) & 1023)+1; - DEBUG_LOG(G3D, "DL Block Transfer Src Rect TL: %i, %i", x, y); - break; - } - case GE_CMD_TRANSFERDSTPOS: - { - u32 x = (data & 1023)+1; - u32 y = ((data>>10) & 1023)+1; - DEBUG_LOG(G3D, "DL Block Transfer Dest Rect TL: %i, %i", x, y); - break; - } - case GE_CMD_TRANSFERSIZE: - { - u32 w = (data & 1023)+1; - u32 h = ((data>>10) & 1023)+1; - DEBUG_LOG(G3D, "DL Block Transfer Rect Size: %i x %i", w, h); - break; - } + break; case GE_CMD_TRANSFERSTART: { - u32 srcBasePtr = (gstate.transfersrc & 0xFFFFF0) | ((gstate.transfersrcw & 0xFF0000) << 8); - u32 srcStride = gstate.transfersrcw & 0x3F8; + u32 srcBasePtr = gstate.getTransferSrcAddress(); + u32 srcStride = gstate.getTransferSrcStride(); - u32 dstBasePtr = (gstate.transferdst & 0xFFFFF0) | ((gstate.transferdstw & 0xFF0000) << 8); - u32 dstStride = gstate.transferdstw & 0x3F8; + u32 dstBasePtr = gstate.getTransferDstAddress(); + u32 dstStride = gstate.getTransferDstStride(); - int srcX = gstate.transfersrcpos & 0x3FF; - int srcY = (gstate.transfersrcpos >> 10) & 0x3FF; + int srcX = gstate.getTransferSrcX(); + int srcY = gstate.getTransferSrcY(); - int dstX = gstate.transferdstpos & 0x3FF; - int dstY = (gstate.transferdstpos >> 10) & 0x3FF; + int dstX = gstate.getTransferDstX(); + int dstY = gstate.getTransferDstY(); - int width = (gstate.transfersize & 0x3FF) + 1; - int height = ((gstate.transfersize >> 10) & 0x3FF) + 1; + int width = gstate.getTransferWidth(); + int height = gstate.getTransferHeight(); - int bpp = (gstate.transferstart & 1) ? 4 : 2; + int bpp = gstate.getTransferBpp(); + + DEBUG_LOG(G3D, "Block transfer: %08x/%x -> %08x/%x, %ix%ix%i (%i,%i)->(%i,%i)", srcBasePtr, srcStride, dstBasePtr, dstStride, width, height, bpp, srcX, srcY, dstX, dstY); for (int y = 0; y < height; y++) { const u8 *src = Memory::GetPointer(srcBasePtr + ((y + srcY) * srcStride + srcX) * bpp); @@ -617,7 +586,6 @@ void SoftGPU::ExecuteOp(u32 op, u32 diff) memcpy(dst, src, width * bpp); } - DEBUG_LOG(G3D, "DL Texture Transfer Start: PixFormat %i", data); break; } From 7f6cf3ec29d5ea62e9525bb971d40cf2c302c6d0 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 10:51:17 -0700 Subject: [PATCH 008/237] Add a few gstate accessors for texture type stuff. --- GPU/GLES/GLES_GPU.cpp | 2 +- GPU/GLES/ShaderManager.cpp | 4 ++-- GPU/GLES/Spline.cpp | 2 +- GPU/GLES/TextureCache.cpp | 12 ++++++------ GPU/GLES/VertexShaderGenerator.cpp | 2 +- GPU/GPUState.h | 2 ++ GPU/Software/Rasterizer.cpp | 2 +- 7 files changed, 14 insertions(+), 12 deletions(-) diff --git a/GPU/GLES/GLES_GPU.cpp b/GPU/GLES/GLES_GPU.cpp index 82cd951b2d..d5ac3613de 100644 --- a/GPU/GLES/GLES_GPU.cpp +++ b/GPU/GLES/GLES_GPU.cpp @@ -721,7 +721,7 @@ void GLES_GPU::ExecuteOp(u32 op, u32 diff) { } if (gstate.getPatchPrimitiveType() != GE_PATCHPRIM_TRIANGLES) { - ERROR_LOG_REPORT(G3D, "Unsupported patch primitive %x", gstate.patchprimitive&3); + ERROR_LOG_REPORT(G3D, "Unsupported patch primitive %x", gstate.getPatchPrimitiveType()); break; } diff --git a/GPU/GLES/ShaderManager.cpp b/GPU/GLES/ShaderManager.cpp index 37b5b7d0a8..e6bc95f768 100644 --- a/GPU/GLES/ShaderManager.cpp +++ b/GPU/GLES/ShaderManager.cpp @@ -113,7 +113,7 @@ LinkedShader::LinkedShader(Shader *vs, Shader *fs, bool useHWTransform) u_view = glGetUniformLocation(program, "u_view"); u_world = glGetUniformLocation(program, "u_world"); u_texmtx = glGetUniformLocation(program, "u_texmtx"); - if (gstate.getWeightMask() != 0) + if (gstate.getWeightMask() != GE_VTYPE_WEIGHT_NONE) numBones = TranslateNumBones(gstate.getNumBoneWeights()); else numBones = 0; @@ -338,7 +338,7 @@ void LinkedShader::updateUniforms() { // Not sure what GE_TEXMAP_UNKNOWN is, but seen in Riviera. Treating the same as GE_TEXMAP_TEXTURE_COORDS works. if (gstate.getUVGenMode() == GE_TEXMAP_TEXTURE_COORDS || gstate.getUVGenMode() == GE_TEXMAP_UNKNOWN) { static const float rescale[4] = {1.0f, 2*127.5f/128.f, 2*32767.5f/32768.f, 1.0f}; - float factor = rescale[(gstate.vertType & GE_VTYPE_TC_MASK) >> GE_VTYPE_TC_SHIFT]; + float factor = rescale[gstate.getTexCoordMask() >> GE_VTYPE_TC_SHIFT]; uvscaleoff[0] = gstate_c.uv.uScale * factor * widthFactor; uvscaleoff[1] = gstate_c.uv.vScale * factor * heightFactor; uvscaleoff[2] = gstate_c.uv.uOff * widthFactor; diff --git a/GPU/GLES/Spline.cpp b/GPU/GLES/Spline.cpp index 9e033078d7..4bc1c9b053 100644 --- a/GPU/GLES/Spline.cpp +++ b/GPU/GLES/Spline.cpp @@ -57,7 +57,7 @@ void TransformDrawEngine::DrawBezier(int ucount, int vcount) { } } - if (!(gstate.vertType & GE_VTYPE_TC_MASK)) { + if (!gstate.getTexCoordMask()) { VertexDecoder *dec = GetVertexDecoder(gstate.vertType); dec->SetVertexType(gstate.vertType); u32 newVertType = dec->InjectUVs(decoded2, Memory::GetPointer(gstate_c.vertexAddr), customUV, 16); diff --git a/GPU/GLES/TextureCache.cpp b/GPU/GLES/TextureCache.cpp index 1f10637a1d..5dd752c252 100644 --- a/GPU/GLES/TextureCache.cpp +++ b/GPU/GLES/TextureCache.cpp @@ -424,7 +424,7 @@ void *TextureCache::readIndexedTex(int level, u32 texaddr, int bytesPerIndex, GL tmpTexBuf16.resize(std::max(bufw, w) * h); tmpTexBufRearrange.resize(std::max(bufw, w) * h); const u16 *clut = GetCurrentClut(); - if (!(gstate.texmode & 1)) { + if (!gstate.isTextureSwizzled()) { switch (bytesPerIndex) { case 1: DeIndexTexture(tmpTexBuf16.data(), texaddr, length, clut); @@ -464,7 +464,7 @@ void *TextureCache::readIndexedTex(int level, u32 texaddr, int bytesPerIndex, GL tmpTexBuf32.resize(std::max(bufw, w) * h); tmpTexBufRearrange.resize(std::max(bufw, w) * h); const u32 *clut = GetCurrentClut(); - if (!(gstate.texmode & 1)) { + if (!gstate.isTextureSwizzled()) { switch (bytesPerIndex) { case 1: DeIndexTexture(tmpTexBuf32.data(), texaddr, length, clut); @@ -1285,7 +1285,7 @@ void *TextureCache::DecodeTextureLevel(GETextureFormat format, GEPaletteFormat c tmpTexBufRearrange.resize(std::max(bufw, w) * h); const u16 *clut = GetCurrentClut() + clutSharingOffset; texByteAlign = 2; - if (!(gstate.texmode & 1)) { + if (!gstate.isTextureSwizzled()) { if (clutAlphaLinear_ && mipmapShareClut) { DeIndexTexture4Optimal(tmpTexBuf16.data(), texaddr, bufw * h, clutAlphaLinearColor_); } else { @@ -1309,7 +1309,7 @@ void *TextureCache::DecodeTextureLevel(GETextureFormat format, GEPaletteFormat c tmpTexBuf32.resize(std::max(bufw, w) * h); tmpTexBufRearrange.resize(std::max(bufw, w) * h); const u32 *clut = GetCurrentClut() + clutSharingOffset; - if (!(gstate.texmode & 1)) { + if (!gstate.isTextureSwizzled()) { DeIndexTexture4(tmpTexBuf32.data(), texaddr, bufw * h, clut); finalBuf = tmpTexBuf32.data(); } else { @@ -1366,7 +1366,7 @@ void *TextureCache::DecodeTextureLevel(GETextureFormat format, GEPaletteFormat c dstFmt = GL_UNSIGNED_SHORT_5_6_5; texByteAlign = 2; - if (!(gstate.texmode & 1)) { + if (!gstate.isTextureSwizzled()) { int len = std::max(bufw, w) * h; tmpTexBuf16.resize(len); tmpTexBufRearrange.resize(len); @@ -1383,7 +1383,7 @@ void *TextureCache::DecodeTextureLevel(GETextureFormat format, GEPaletteFormat c if (bufw < 4) bufw = 4; dstFmt = GL_UNSIGNED_BYTE; - if (!(gstate.texmode & 1)) { + if (!gstate.isTextureSwizzled()) { // Special case: if we don't need to deal with packing, we don't need to copy. if (w == bufw) { finalBuf = Memory::GetPointer(texaddr); diff --git a/GPU/GLES/VertexShaderGenerator.cpp b/GPU/GLES/VertexShaderGenerator.cpp index d7b155046c..9fb597b68c 100644 --- a/GPU/GLES/VertexShaderGenerator.cpp +++ b/GPU/GLES/VertexShaderGenerator.cpp @@ -60,7 +60,7 @@ void ComputeVertexShaderID(VertexShaderID *id, int prim, bool useHWTransform) { bool hasColor = (vertType & GE_VTYPE_COL_MASK) != 0; bool hasNormal = (vertType & GE_VTYPE_NRM_MASK) != 0; - bool hasBones = gstate.getWeightMask() != 0; + bool hasBones = gstate.getWeightMask() != GE_VTYPE_WEIGHT_NONE; bool enableFog = gstate.isFogEnabled() && !gstate.isModeThrough() && !gstate.isModeClear(); bool lmode = gstate.isUsingSecondaryColor() && gstate.isLightingEnabled(); diff --git a/GPU/GPUState.h b/GPU/GPUState.h index 377f0638e4..d757246acd 100644 --- a/GPU/GPUState.h +++ b/GPU/GPUState.h @@ -289,6 +289,7 @@ struct GPUgstate int getClutIndexMask() const { return (clutformat >> 8) & 0xFF; } int getClutIndexStartPos() const { return ((clutformat >> 16) & 0x1F) << 4; } bool isClutIndexSimple() const { return (clutformat & ~3) == 0xC500FF00; } // Meaning, no special mask, shift, or start pos. + bool isTextureSwizzled() const { return texmode & 1; } // Lighting bool isLightingEnabled() const { return lightingEnable & 1; } @@ -353,6 +354,7 @@ struct GPUgstate int getWeightMask() const { return vertType & GE_VTYPE_WEIGHT_MASK; } int getNumBoneWeights() const { return 1 + ((vertType & GE_VTYPE_WEIGHTCOUNT_MASK) >> GE_VTYPE_WEIGHTCOUNT_SHIFT); } bool isSkinningEnabled() const { return ((vertType & GE_VTYPE_WEIGHT_MASK) != GE_VTYPE_WEIGHT_NONE); } + int getTexCoordMask() const { return vertType & GE_VTYPE_TC_MASK; } GEPatchPrimType getPatchPrimitiveType() const { return static_cast(patchprimitive & 3); } diff --git a/GPU/Software/Rasterizer.cpp b/GPU/Software/Rasterizer.cpp index 7693957c98..034fd4954f 100644 --- a/GPU/Software/Rasterizer.cpp +++ b/GPU/Software/Rasterizer.cpp @@ -46,7 +46,7 @@ static inline int orient2dIncY(int dX01) static inline int GetPixelDataOffset(unsigned int texel_size_bits, unsigned int row_pitch_bits, unsigned int u, unsigned int v) { - if (!(gstate.texmode & 1)) + if (!gstate.isTextureSwizzled()) return v * row_pitch_bits *texel_size_bits/8 / 8 + u * texel_size_bits / 8; int tile_size_bits = 32; From 5ab04a3076a0a945eeb7683414b1ca849b63501c Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 11:10:56 -0700 Subject: [PATCH 009/237] Centralize CLUT handling form gstate values. --- GPU/GLES/TextureCache.cpp | 17 +++++------------ GPU/GPUState.h | 3 +++ GPU/Null/NullGpu.cpp | 2 +- GPU/Software/Rasterizer.cpp | 17 +++++------------ GPU/Software/SoftGpu.cpp | 8 ++++---- 5 files changed, 18 insertions(+), 29 deletions(-) diff --git a/GPU/GLES/TextureCache.cpp b/GPU/GLES/TextureCache.cpp index 5dd752c252..7c36755c33 100644 --- a/GPU/GLES/TextureCache.cpp +++ b/GPU/GLES/TextureCache.cpp @@ -254,13 +254,6 @@ void TextureCache::NotifyFramebuffer(u32 address, VirtualFramebuffer *framebuffe } } -static u32 GetClutIndex(u32 index) { - const u32 clutBase = gstate.getClutIndexStartPos(); - const u32 clutMask = gstate.getClutIndexMask(); - const u8 clutShift = gstate.getClutIndexShift(); - return ((index >> clutShift) & clutMask) | clutBase; -} - void *TextureCache::UnswizzleFromMem(u32 texaddr, u32 bufw, u32 bytesPerPixel, u32 level) { const u32 rowWidth = (bytesPerPixel > 0) ? (bufw * bytesPerPixel) : (bufw / 2); const u32 pitch = rowWidth / 4; @@ -346,7 +339,7 @@ inline void DeIndexTexture(ClutT *dest, const IndexT *indexed, int length, const } } else { for (int i = 0; i < length; ++i) { - *dest++ = clut[GetClutIndex(*indexed++)]; + *dest++ = clut[gstate.transformClutIndex(*indexed++)]; } } } @@ -371,8 +364,8 @@ inline void DeIndexTexture4(ClutT *dest, const u8 *indexed, int length, const Cl } else { for (int i = 0; i < length; i += 2) { u8 index = *indexed++; - dest[i + 0] = clut[GetClutIndex((index >> 0) & 0xf)]; - dest[i + 1] = clut[GetClutIndex((index >> 4) & 0xf)]; + dest[i + 0] = clut[gstate.transformClutIndex((index >> 0) & 0xf)]; + dest[i + 1] = clut[gstate.transformClutIndex((index >> 4) & 0xf)]; } } } @@ -873,8 +866,8 @@ inline bool TextureCache::TexCacheEntry::Matches(u16 dim2, u8 format2, int maxLe } void TextureCache::LoadClut() { - u32 clutAddr = ((gstate.clutaddr & 0xFFFFFF) | ((gstate.clutaddrupper << 8) & 0x0F000000)); - clutTotalBytes_ = (gstate.loadclut & 0x3f) * 32; + u32 clutAddr = gstate.getClutAddress(); + clutTotalBytes_ = gstate.getClutLoadBytes(); if (Memory::IsValidAddress(clutAddr)) { Memory::MemcpyUnchecked(clutBufRaw_, clutAddr, clutTotalBytes_); } else { diff --git a/GPU/GPUState.h b/GPU/GPUState.h index d757246acd..672d8e8025 100644 --- a/GPU/GPUState.h +++ b/GPU/GPUState.h @@ -284,10 +284,13 @@ struct GPUgstate int getTextureEnvColR() const { return texenvcolor&0xFF; } int getTextureEnvColG() const { return (texenvcolor>>8)&0xFF; } int getTextureEnvColB() const { return (texenvcolor>>16)&0xFF; } + u32 getClutAddress() const { return (clutaddr & 0x00FFFFFF) | ((clutaddrupper << 8) & 0x0F000000); } + int getClutLoadBytes() const { return (loadclut & 0x3F) * 32; } GEPaletteFormat getClutPaletteFormat() { return static_cast(clutformat & 3); } int getClutIndexShift() const { return (clutformat >> 2) & 0x1F; } int getClutIndexMask() const { return (clutformat >> 8) & 0xFF; } int getClutIndexStartPos() const { return ((clutformat >> 16) & 0x1F) << 4; } + int transformClutIndex(int index) const { return ((index >> getClutIndexShift()) & getClutIndexMask()) | getClutIndexStartPos(); } bool isClutIndexSimple() const { return (clutformat & ~3) == 0xC500FF00; } // Meaning, no special mask, shift, or start pos. bool isTextureSwizzled() const { return texmode & 1; } diff --git a/GPU/Null/NullGpu.cpp b/GPU/Null/NullGpu.cpp index 14761a89ea..58c02dbe66 100644 --- a/GPU/Null/NullGpu.cpp +++ b/GPU/Null/NullGpu.cpp @@ -265,7 +265,7 @@ void NullGPU::ExecuteOp(u32 op, u32 diff) case GE_CMD_LOADCLUT: // This could be used to "dirty" textures with clut. { - u32 clutAddr = ((gstate.clutaddrupper & 0xFF0000)<<8) | (gstate.clutaddr & 0xFFFFFF); + u32 clutAddr = gstate.getClutAddress(); if (clutAddr) { DEBUG_LOG(G3D,"DL Clut load: %08x", clutAddr); diff --git a/GPU/Software/Rasterizer.cpp b/GPU/Software/Rasterizer.cpp index 034fd4954f..94f2d58318 100644 --- a/GPU/Software/Rasterizer.cpp +++ b/GPU/Software/Rasterizer.cpp @@ -90,13 +90,6 @@ static inline u32 LookupColor(unsigned int index, unsigned int level) } } -static inline u32 GetClutIndex(u32 index) { - const u32 clutBase = gstate.getClutIndexStartPos(); - const u32 clutMask = gstate.getClutIndexMask(); - const u8 clutShift = gstate.getClutIndexShift(); - return ((index >> clutShift) & clutMask) | clutBase; -} - static inline void GetTexelCoordinates(int level, float s, float t, unsigned int& u, unsigned int& v) { s *= getFloat24(gstate.texscaleu); @@ -185,25 +178,25 @@ static inline u32 SampleNearest(int level, unsigned int u, unsigned int v) u32 val = srcptr[0] + (srcptr[1] << 8) + (srcptr[2] << 16) + (srcptr[3] << 24); - return LookupColor(GetClutIndex(val), level); + return LookupColor(gstate.transformClutIndex(val), level); } else if (texfmt == GE_TFMT_CLUT16) { srcptr += GetPixelDataOffset(16, texbufwidth*8, u, v); u16 val = srcptr[0] + (srcptr[1] << 8); - return LookupColor(GetClutIndex(val), level); + return LookupColor(gstate.transformClutIndex(val), level); } else if (texfmt == GE_TFMT_CLUT8) { srcptr += GetPixelDataOffset(8, texbufwidth*8, u, v); u8 val = *srcptr; - return LookupColor(GetClutIndex(val), level); + return LookupColor(gstate.transformClutIndex(val), level); } else if (texfmt == GE_TFMT_CLUT4) { srcptr += GetPixelDataOffset(4, texbufwidth*8, u, v); u8 val = (u & 1) ? (srcptr[0] >> 4) : (srcptr[0] & 0xF); - return LookupColor(GetClutIndex(val), level); + return LookupColor(gstate.transformClutIndex(val), level); } else { ERROR_LOG(G3D, "Unsupported texture format: %x", texfmt); return 0; @@ -404,7 +397,7 @@ static inline Vec4 GetTextureFunctionOutput(const Vec3& prim_color_rgb Vec3 out_rgb; int out_a; - bool rgba = (gstate.texfunc & 0x100) != 0; + bool rgba = gstate.isTextureAlphaUsed(); switch (gstate.getTextureFunction()) { case GE_TEXFUNC_MODULATE: diff --git a/GPU/Software/SoftGpu.cpp b/GPU/Software/SoftGpu.cpp index 972066b455..9c89a31e26 100644 --- a/GPU/Software/SoftGpu.cpp +++ b/GPU/Software/SoftGpu.cpp @@ -528,14 +528,14 @@ void SoftGPU::ExecuteOp(u32 op, u32 diff) case GE_CMD_LOADCLUT: { - u32 clutAddr = ((gstate.clutaddr & 0xFFFFF0) | ((gstate.clutaddrupper << 8) & 0xFF000000)); - u32 clutTotalBytes_ = (gstate.loadclut & 0x3f) * 32; + u32 clutAddr = gstate.getClutAddress(); + u32 clutTotalBytes = gstate.getClutLoadBytes(); if (Memory::IsValidAddress(clutAddr)) { - Memory::Memcpy(clut, clutAddr, clutTotalBytes_); + Memory::MemcpyUnchecked(clut, clutAddr, clutTotalBytes); } else { // TODO: Does this make any sense? - memset(clut, 0xFF, clutTotalBytes_); + memset(clut, 0xFF, clutTotalBytes); } if (clutAddr) From cd70250d8c9241d26a0de9944b0bd856af26e946 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 11:11:34 -0700 Subject: [PATCH 010/237] Use more accessors, simplify softgpu colortest. --- GPU/GLES/VertexDecoder.cpp | 12 ++++++------ GPU/GPUState.h | 1 + GPU/Software/Rasterizer.cpp | 18 +++++++++--------- GPU/Software/TransformUnit.cpp | 2 +- 4 files changed, 17 insertions(+), 16 deletions(-) diff --git a/GPU/GLES/VertexDecoder.cpp b/GPU/GLES/VertexDecoder.cpp index e912b19b11..d28a41db0e 100644 --- a/GPU/GLES/VertexDecoder.cpp +++ b/GPU/GLES/VertexDecoder.cpp @@ -336,7 +336,7 @@ void VertexDecoder::Step_NormalS8() const { s8 *normal = (s8 *)(decoded_ + decFmt.nrmoff); u8 xorval = 0; - if (gstate.reversenormals & 1) + if (gstate.areNormalsReversed()) xorval = 0xFF; // Using xor instead of - to handle -128 const s8 *sv = (const s8*)(ptr_ + nrmoff); for (int j = 0; j < 3; j++) @@ -348,7 +348,7 @@ void VertexDecoder::Step_NormalS16() const { s16 *normal = (s16 *)(decoded_ + decFmt.nrmoff); u16 xorval = 0; - if (gstate.reversenormals & 1) + if (gstate.areNormalsReversed()) xorval = 0xFFFF; const s16 *sv = (const s16*)(ptr_ + nrmoff); for (int j = 0; j < 3; j++) @@ -360,7 +360,7 @@ void VertexDecoder::Step_NormalFloat() const { float *normal = (float *)(decoded_ + decFmt.nrmoff); float multiplier = 1.0f; - if (gstate.reversenormals & 1) + if (gstate.areNormalsReversed()) multiplier = -multiplier; const float *fv = (const float*)(ptr_ + nrmoff); for (int j = 0; j < 3; j++) @@ -374,7 +374,7 @@ void VertexDecoder::Step_NormalS8Morph() const for (int n = 0; n < morphcount; n++) { float multiplier = gstate_c.morphWeights[n]; - if (gstate.reversenormals & 1) { + if (gstate.areNormalsReversed()) { multiplier = -multiplier; } const s8 *bv = (const s8*)(ptr_ + onesize_*n + nrmoff); @@ -391,7 +391,7 @@ void VertexDecoder::Step_NormalS16Morph() const for (int n = 0; n < morphcount; n++) { float multiplier = gstate_c.morphWeights[n]; - if (gstate.reversenormals & 1) { + if (gstate.areNormalsReversed()) { multiplier = -multiplier; } const s16 *sv = (const s16 *)(ptr_ + onesize_*n + nrmoff); @@ -408,7 +408,7 @@ void VertexDecoder::Step_NormalFloatMorph() const for (int n = 0; n < morphcount; n++) { float multiplier = gstate_c.morphWeights[n]; - if (gstate.reversenormals & 1) { + if (gstate.areNormalsReversed()) { multiplier = -multiplier; } const float *fv = (const float*)(ptr_ + onesize_*n + nrmoff); diff --git a/GPU/GPUState.h b/GPU/GPUState.h index 672d8e8025..e061eeaf0a 100644 --- a/GPU/GPUState.h +++ b/GPU/GPUState.h @@ -358,6 +358,7 @@ struct GPUgstate int getNumBoneWeights() const { return 1 + ((vertType & GE_VTYPE_WEIGHTCOUNT_MASK) >> GE_VTYPE_WEIGHTCOUNT_SHIFT); } bool isSkinningEnabled() const { return ((vertType & GE_VTYPE_WEIGHT_MASK) != GE_VTYPE_WEIGHT_NONE); } int getTexCoordMask() const { return vertType & GE_VTYPE_TC_MASK; } + bool areNormalsReversed() const { return reversenormals & 1; } GEPatchPrimType getPatchPrimitiveType() const { return static_cast(patchprimitive & 3); } diff --git a/GPU/Software/Rasterizer.cpp b/GPU/Software/Rasterizer.cpp index 94f2d58318..62b57c5eb0 100644 --- a/GPU/Software/Rasterizer.cpp +++ b/GPU/Software/Rasterizer.cpp @@ -445,10 +445,10 @@ static inline Vec4 GetTextureFunctionOutput(const Vec3& prim_color_rgb static inline bool ColorTestPassed(Vec3 color) { - u32 mask = gstate.colormask&0xFFFFFF; - color = Vec3::FromRGB(color.ToRGB() & mask); - Vec3 ref = Vec3::FromRGB(gstate.colorref & mask); - switch (gstate.colortest & 0x3) { + const u32 mask = gstate.getColorTestMask(); + const u32 c = color.ToRGB() & mask; + const u32 ref = gstate.getColorTestRef() & mask; + switch (gstate.getColorTestFunction()) { case GE_COMP_NEVER: return false; @@ -456,21 +456,21 @@ static inline bool ColorTestPassed(Vec3 color) return true; case GE_COMP_EQUAL: - return (color.r() == ref.r() && color.g() == ref.g() && color.b() == ref.b()); + return c == ref; case GE_COMP_NOTEQUAL: - return (color.r() != ref.r() || color.g() != ref.g() || color.b() != ref.b()); + return c != ref; } return true; } static inline bool AlphaTestPassed(int alpha) { - u8 mask = (gstate.alphatest >> 16) & 0xFF; - u8 ref = (gstate.alphatest >> 8) & mask; + const u8 mask = gstate.getAlphaTestMask() & 0xFF; + const u8 ref = gstate.getAlphaTestRef() & mask; alpha &= mask; - switch (gstate.alphatest & 0x7) { + switch (gstate.getAlphaTestFunction()) { case GE_COMP_NEVER: return false; diff --git a/GPU/Software/TransformUnit.cpp b/GPU/Software/TransformUnit.cpp index 1de4c23617..8069bba8fe 100644 --- a/GPU/Software/TransformUnit.cpp +++ b/GPU/Software/TransformUnit.cpp @@ -113,7 +113,7 @@ static VertexData ReadVertex(VertexReader& vreader) vreader.ReadNrm(normal); vertex.normal = Vec3(normal[0], normal[1], normal[2]); - if (gstate.reversenormals & 1) + if (gstate.areNormalsReversed()) vertex.normal = -vertex.normal; } From 8dbcf6572e2241cdcb6272d1b9bef50c98f08a78 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 11:19:35 -0700 Subject: [PATCH 011/237] Add some additional reporting. --- GPU/GLES/GLES_GPU.cpp | 10 ++++++++-- GPU/GPUCommon.cpp | 2 +- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/GPU/GLES/GLES_GPU.cpp b/GPU/GLES/GLES_GPU.cpp index d5ac3613de..75c7da9b6b 100644 --- a/GPU/GLES/GLES_GPU.cpp +++ b/GPU/GLES/GLES_GPU.cpp @@ -662,7 +662,7 @@ void GLES_GPU::ExecuteOp(u32 op, u32 diff) { } if (!Memory::IsValidAddress(gstate_c.vertexAddr)) { - ERROR_LOG(G3D, "Bad vertex address %08x!", gstate_c.vertexAddr); + ERROR_LOG_REPORT(G3D, "Bad vertex address %08x!", gstate_c.vertexAddr); break; } @@ -672,12 +672,18 @@ void GLES_GPU::ExecuteOp(u32 op, u32 diff) { void *inds = 0; if ((gstate.vertType & GE_VTYPE_IDX_MASK) != GE_VTYPE_IDX_NONE) { if (!Memory::IsValidAddress(gstate_c.indexAddr)) { - ERROR_LOG(G3D, "Bad index address %08x!", gstate_c.indexAddr); + ERROR_LOG_REPORT(G3D, "Bad index address %08x!", gstate_c.indexAddr); break; } inds = Memory::GetPointer(gstate_c.indexAddr); } +#ifndef USING_GLES2 + if (prim > GE_PRIM_RECTANGLES) { + ERROR_LOG_REPORT_ONCE(reportPrim, G3D, "Unexpected prim type: %d", prim); + } +#endif + int bytesRead; transformDraw_.SubmitPrim(verts, inds, prim, count, gstate.vertType, -1, &bytesRead); diff --git a/GPU/GPUCommon.cpp b/GPU/GPUCommon.cpp index d2b5f2bd75..de6ab4d1a5 100644 --- a/GPU/GPUCommon.cpp +++ b/GPU/GPUCommon.cpp @@ -566,7 +566,7 @@ void GPUCommon::ProcessEvent(GPUEvent ev) { break; default: - ERROR_LOG(G3D, "Unexpected GPU event type: %d", (int)ev); + ERROR_LOG_REPORT(G3D, "Unexpected GPU event type: %d", (int)ev); } } From 6e8d318322d7e4afab8f56a92b91e4155369129f Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 11:36:01 -0700 Subject: [PATCH 012/237] Bugger typo. --- GPU/Software/Rasterizer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/GPU/Software/Rasterizer.cpp b/GPU/Software/Rasterizer.cpp index 62b57c5eb0..4bb22d9a07 100644 --- a/GPU/Software/Rasterizer.cpp +++ b/GPU/Software/Rasterizer.cpp @@ -719,7 +719,7 @@ void DrawTriangle(const VertexData& v0, const VertexData& v1, const VertexData& // TODO: Fogging // TODO: Is that the correct way to interpolate? - // With the (u32), this causes an ICE in some versions of gcc. + // Without the (u32), this causes an ICE in some versions of gcc. u16 z = (u16)(u32)(((float)v0.screenpos.z * w0 + (float)v1.screenpos.z * w1 + (float)v2.screenpos.z * w2) / (w0+w1+w2)); // Depth range test From e837fd13bd807d3f37dbb4cecb78458bafb51a4a Mon Sep 17 00:00:00 2001 From: Zetro Date: Sat, 24 Aug 2013 04:07:33 +0200 Subject: [PATCH 013/237] Initialize UI theme in Qt --- Qt/QtHost.cpp | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Qt/QtHost.cpp b/Qt/QtHost.cpp index d79a17142f..c1ca575fd6 100644 --- a/Qt/QtHost.cpp +++ b/Qt/QtHost.cpp @@ -20,6 +20,8 @@ #include "GPU/ge_constants.h" #include "EmuThread.h" +static UI::Theme ui_theme; + const char *stateToLoad = NULL; std::string boot_filename = ""; @@ -357,6 +359,30 @@ void NativeInitGraphics() theme.checkOn = I_CHECKEDBOX; theme.checkOff = I_SQUARE; + ui_theme.uiFont = UBUNTU24; + ui_theme.uiFontSmall = UBUNTU24; + ui_theme.uiFontSmaller = UBUNTU24; + ui_theme.checkOn = I_CHECKEDBOX; + ui_theme.checkOff = I_SQUARE; + ui_theme.whiteImage = I_SOLIDWHITE; + ui_theme.sliderKnob = I_CIRCLE; + ui_theme.dropShadow4Grid = I_DROP_SHADOW; + + ui_theme.itemStyle.background = UI::Drawable(0x55000000); + ui_theme.itemStyle.fgColor = 0xFFFFFFFF; + ui_theme.itemFocusedStyle.background = UI::Drawable(0xFFedc24c); + ui_theme.itemDownStyle.background = UI::Drawable(0xFFbd9939); + ui_theme.itemDownStyle.fgColor = 0xFFFFFFFF; + ui_theme.itemDisabledStyle.background = UI::Drawable(0x55E0D4AF); + ui_theme.itemDisabledStyle.fgColor = 0xFFcccccc; + + ui_theme.buttonStyle = ui_theme.itemStyle; + ui_theme.buttonFocusedStyle = ui_theme.itemFocusedStyle; + ui_theme.buttonDownStyle = ui_theme.itemDownStyle; + ui_theme.buttonDisabledStyle = ui_theme.itemDisabledStyle; + + ui_theme.popupTitle.fgColor = 0xFFE3BE59; + ui_draw2d.Init(); ui_draw2d_front.Init(); @@ -370,6 +396,7 @@ void NativeInitGraphics() uiTexture->Bind(0); uiContext = new UIContext(); + uiContext->theme = &ui_theme; uiContext->Init(UIShader_Get(), UIShader_GetPlain(), uiTexture, &ui_draw2d, &ui_draw2d_front); screenManager->setUIContext(uiContext); From b37f09cedf9cbad73ff6de7159783c7313422047 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 13:22:10 -0700 Subject: [PATCH 014/237] Make MIPSInfo a struct for typesafety. Found a bug in ReadsFromReg(). --- Core/MIPS/ARM/ArmJit.cpp | 4 +-- Core/MIPS/MIPSAnalyst.cpp | 20 +++++------ Core/MIPS/MIPSAnalyst.h | 1 - Core/MIPS/MIPSCodeUtils.cpp | 8 ++--- Core/MIPS/MIPSInt.cpp | 2 +- Core/MIPS/MIPSTables.cpp | 14 ++++---- Core/MIPS/MIPSTables.h | 64 ++++++++++++++++++++++-------------- Core/MIPS/x86/CompBranch.cpp | 2 +- Core/MIPS/x86/Jit.cpp | 4 +-- 9 files changed, 66 insertions(+), 53 deletions(-) diff --git a/Core/MIPS/ARM/ArmJit.cpp b/Core/MIPS/ARM/ArmJit.cpp index 9ff285102a..48f34e3401 100644 --- a/Core/MIPS/ARM/ArmJit.cpp +++ b/Core/MIPS/ARM/ArmJit.cpp @@ -132,7 +132,7 @@ void Jit::CompileAt(u32 addr) void Jit::EatInstruction(u32 op) { - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); _dbg_assert_msg_(JIT, !(info & DELAYSLOT), "Never eat a branch op."); _dbg_assert_msg_(JIT, !js.inDelaySlot, "Never eat an instruction inside a delayslot."); @@ -286,7 +286,7 @@ void Jit::Comp_Generic(u32 op) RestoreDowncount(); } - const int info = MIPSGetInfo(op); + const MIPSInfo info = MIPSGetInfo(op); if ((info & IS_VFPU) != 0 && (info & VFPU_NO_PREFIX) == 0) { // If it does eat them, it'll happen in MIPSCompileOp(). diff --git a/Core/MIPS/MIPSAnalyst.cpp b/Core/MIPS/MIPSAnalyst.cpp index 63e8300b2e..84eeb729e9 100644 --- a/Core/MIPS/MIPSAnalyst.cpp +++ b/Core/MIPS/MIPSAnalyst.cpp @@ -36,7 +36,7 @@ namespace MIPSAnalyst int GetOutReg(u32 op) { - u32 opinfo = MIPSGetInfo(op); + MIPSInfo opinfo = MIPSGetInfo(op); if (opinfo & OUT_RT) return MIPS_GET_RT(op); if (opinfo & OUT_RD) @@ -48,15 +48,15 @@ namespace MIPSAnalyst bool ReadsFromReg(u32 op, u32 reg) { - u32 opinfo = MIPSGetInfo(op); + MIPSInfo opinfo = MIPSGetInfo(op); if (opinfo & IN_RT) { - if (MIPS_GET_RT(opinfo) == reg) + if (MIPS_GET_RT(op) == reg) return true; } if (opinfo & IN_RS) { - if (MIPS_GET_RS(opinfo) == reg) + if (MIPS_GET_RS(op) == reg) return true; } return false; //TODO: there are more cases! @@ -132,7 +132,7 @@ namespace MIPSAnalyst while (true) { u32 op = Memory::Read_Instruction(addr); - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); for (int reg=0; reg < 32; reg++) { @@ -241,7 +241,7 @@ namespace MIPSAnalyst while (true) { u32 op = Memory::Read_Instruction(addr); - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); if ((info & IN_RS) && (MIPS_GET_RS(op) == reg)) return true; @@ -272,7 +272,7 @@ namespace MIPSAnalyst { u32 validbits = 0xFFFFFFFF; u32 instr = Memory::Read_Instruction(addr); - u32 flags = MIPSGetInfo(instr); + MIPSInfo flags = MIPSGetInfo(instr); if (flags & IN_IMM16) validbits&=~0xFFFF; if (flags & IN_IMM26) @@ -455,7 +455,7 @@ namespace MIPSAnalyst std::vector GetInputRegs(u32 op) { std::vector vec; - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); if ((info & IS_VFPU) == 0) { if (info & IN_RS) vec.push_back(MIPS_GET_RS(op)); @@ -466,7 +466,7 @@ namespace MIPSAnalyst std::vector GetOutputRegs(u32 op) { std::vector vec; - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); if ((info & IS_VFPU) == 0) { if (info & OUT_RD) vec.push_back(MIPS_GET_RD(op)); @@ -490,7 +490,7 @@ namespace MIPSAnalyst info.encodedOpcode = Memory::Read_Instruction(address); u32 op = info.encodedOpcode; - u32 opInfo = MIPSGetInfo(op); + MIPSInfo opInfo = MIPSGetInfo(op); info.isLikelyBranch = (opInfo & LIKELY) != 0; //j , jal, ... diff --git a/Core/MIPS/MIPSAnalyst.h b/Core/MIPS/MIPSAnalyst.h index 7167e8287a..510981d580 100644 --- a/Core/MIPS/MIPSAnalyst.h +++ b/Core/MIPS/MIPSAnalyst.h @@ -37,7 +37,6 @@ namespace MIPSAnalyst int readCount; int writeCount; int readAsAddrCount; - bool usesVFPU; int TotalReadCount() {return readCount + readAsAddrCount;} int FirstRead() {return firstReadAsAddr < firstRead ? firstReadAsAddr : firstRead;} diff --git a/Core/MIPS/MIPSCodeUtils.cpp b/Core/MIPS/MIPSCodeUtils.cpp index 43a112a166..b5f22005ad 100644 --- a/Core/MIPS/MIPSCodeUtils.cpp +++ b/Core/MIPS/MIPSCodeUtils.cpp @@ -34,7 +34,7 @@ namespace MIPSCodeUtils u32 op = Memory::Read_Instruction(addr); if (op) { - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); if ((info & IS_JUMP) && (info & IN_IMM26)) { u32 target = (addr & 0xF0000000) | ((op&0x03FFFFFF) << 2); @@ -52,7 +52,7 @@ namespace MIPSCodeUtils u32 op = Memory::Read_Instruction(addr); if (op) { - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); if (info & IS_CONDBRANCH) { return addr + 4 + ((signed short)(op&0xFFFF)<<2); @@ -69,7 +69,7 @@ namespace MIPSCodeUtils u32 op = Memory::Read_Instruction(addr); if (op) { - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); if ((info & IS_CONDBRANCH) && !(info & OUT_RA)) { return addr + 4 + ((signed short)(op&0xFFFF)<<2); @@ -86,7 +86,7 @@ namespace MIPSCodeUtils u32 op = Memory::Read_Instruction(addr); if (op) { - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); if (info & IS_CONDBRANCH) { bool sure; diff --git a/Core/MIPS/MIPSInt.cpp b/Core/MIPS/MIPSInt.cpp index 47d22a5130..119f614033 100644 --- a/Core/MIPS/MIPSInt.cpp +++ b/Core/MIPS/MIPSInt.cpp @@ -72,7 +72,7 @@ int MIPS_SingleStep() #endif /* // Choke on VFPU - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); if (info & IS_VFPU) { if (!Core_IsStepping() && !GetAsyncKeyState(VK_LSHIFT)) diff --git a/Core/MIPS/MIPSTables.cpp b/Core/MIPS/MIPSTables.cpp index 2c11791803..e8c46a8dfd 100644 --- a/Core/MIPS/MIPSTables.cpp +++ b/Core/MIPS/MIPSTables.cpp @@ -71,7 +71,7 @@ struct MIPSInstruction #endif MIPSInterpretFunc interpret; //MIPSInstructionInfo information; - u32 flags; + MIPSInfo flags; }; #define INVALID {-2} @@ -80,7 +80,7 @@ struct MIPSInstruction #ifndef FINAL #define ENCODING(a) {a} -#define INSTR(name, comp, dis, inter, flags) {-1, N(name), comp, dis, inter, flags} +#define INSTR(name, comp, dis, inter, flags) {-1, N(name), comp, dis, inter, MIPSInfo(flags)} #else #define ENCODING(a) {a} #define INSTR(name, comp, dis, inter, flags) {-1, comp, inter, flags} @@ -924,7 +924,7 @@ void MIPSCompileOp(u32 op) if (op==0) return; const MIPSInstruction *instr = MIPSGetInstruction(op); - const int info = MIPSGetInfo(op); + const MIPSInfo info = MIPSGetInfo(op); if (instr) { if (instr->compile) @@ -1018,7 +1018,7 @@ int MIPSInterpret_RunUntil(u64 globalTicks) //u32 op = Memory::Read_Opcode_JIT(mipsr4k.pc); /* // Choke on VFPU - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); if (info & IS_VFPU) { if (!Core_IsStepping() && !GetAsyncKeyState(VK_LSHIFT)) @@ -1089,14 +1089,14 @@ const char *MIPSGetName(u32 op) return instr->name; } -u32 MIPSGetInfo(u32 op) +MIPSInfo MIPSGetInfo(u32 op) { // int crunch = CRUNCH_MIPS_OP(op); const MIPSInstruction *instr = MIPSGetInstruction(op); if (instr) return instr->flags; else - return 0; + return MIPSInfo(BAD_INSTRUCTION); } MIPSInterpretFunc MIPSGetInterpretFunc(u32 op) @@ -1111,7 +1111,7 @@ MIPSInterpretFunc MIPSGetInterpretFunc(u32 op) // TODO: Do something that makes sense here. int MIPSGetInstructionCycleEstimate(u32 op) { - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); if (info & DELAYSLOT) return 2; else diff --git a/Core/MIPS/MIPSTables.h b/Core/MIPS/MIPSTables.h index 439e9c9fc2..2264aaa698 100644 --- a/Core/MIPS/MIPSTables.h +++ b/Core/MIPS/MIPSTables.h @@ -17,7 +17,22 @@ #pragma once -#include "../../Globals.h" +#include "Globals.h" + +struct MIPSInfo { + MIPSInfo() { + value = 0; + } + + explicit MIPSInfo(u32 v) : value(v) { + } + + u32 operator & (const u32 &arg) const { + return value & arg; + } + + u32 value; +}; #define CONDTYPE_MASK 0x00000007 #define CONDTYPE_EQ 0x00000001 @@ -40,32 +55,31 @@ #define IS_CONDMOVE 0x00000008 #define DELAYSLOT 0x00000010 #define BAD_INSTRUCTION 0x00000020 -#define UNCONDITIONAL 0x00000040 -#define LIKELY 0x00000080 -#define IS_CONDBRANCH 0x00000100 -#define IS_JUMP 0x00000200 +#define LIKELY 0x00000040 +#define IS_CONDBRANCH 0x00000080 +#define IS_JUMP 0x00000100 -#define IN_RS 0x00000400 -#define IN_RS_ADDR (0x00000800 | IN_RS) -#define IN_RS_SHIFT (0x00001000 | IN_RS) -#define IN_RT 0x00002000 -#define IN_SA 0x00004000 -#define IN_IMM16 0x00008000 -#define IN_IMM26 0x00010000 -#define IN_MEM 0x00020000 -#define IN_OTHER 0x00040000 -#define IN_FPUFLAG 0x00080000 +#define IN_RS 0x00000200 +#define IN_RS_ADDR (0x00000400 | IN_RS) +#define IN_RS_SHIFT (0x00000800 | IN_RS) +#define IN_RT 0x00001000 +#define IN_SA 0x00002000 +#define IN_IMM16 0x00004000 +#define IN_IMM26 0x00008000 +#define IN_MEM 0x00010000 +#define IN_OTHER 0x00020000 +#define IN_FPUFLAG 0x00040000 -#define OUT_RT 0x00100000 -#define OUT_RD 0x00200000 -#define OUT_RA 0x00400000 -#define OUT_MEM 0x00800000 -#define OUT_OTHER 0x01000000 -#define OUT_FPUFLAG 0x02000000 -#define OUT_EAT_PREFIX 0x04000000 +#define OUT_RT 0x00080000 +#define OUT_RD 0x00100000 +#define OUT_RA 0x00200000 +#define OUT_MEM 0x00400000 +#define OUT_OTHER 0x00800000 +#define OUT_FPUFLAG 0x01000000 +#define OUT_EAT_PREFIX 0x02000000 -#define VFPU_NO_PREFIX 0x08000000 -#define IS_VFPU 0x80000000 +#define VFPU_NO_PREFIX 0x04000000 +#define IS_VFPU 0x08000000 #ifndef CDECL #define CDECL @@ -77,7 +91,7 @@ typedef void (CDECL *MIPSInterpretFunc)(u32 opcode); void MIPSCompileOp(u32 op); void MIPSDisAsm(u32 op, u32 pc, char *out, bool tabsToSpaces = false); -u32 MIPSGetInfo(u32 op); +MIPSInfo MIPSGetInfo(u32 op); void MIPSInterpret(u32 op); //only for those rare ones int MIPSInterpret_RunUntil(u64 globalTicks); MIPSInterpretFunc MIPSGetInterpretFunc(u32 op); diff --git a/Core/MIPS/x86/CompBranch.cpp b/Core/MIPS/x86/CompBranch.cpp index f03a4920ee..44451de1e3 100644 --- a/Core/MIPS/x86/CompBranch.cpp +++ b/Core/MIPS/x86/CompBranch.cpp @@ -78,7 +78,7 @@ static void JitBranchLog(u32 op, u32 pc) currentMIPS->inDelaySlot = false; MIPSInterpretFunc func = MIPSGetInterpretFunc(op); - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); func(op); // Branch taken, use nextPC. diff --git a/Core/MIPS/x86/Jit.cpp b/Core/MIPS/x86/Jit.cpp index c73e6a5691..5e1eebd38e 100644 --- a/Core/MIPS/x86/Jit.cpp +++ b/Core/MIPS/x86/Jit.cpp @@ -229,7 +229,7 @@ void Jit::CompileAt(u32 addr) void Jit::EatInstruction(u32 op) { - u32 info = MIPSGetInfo(op); + MIPSInfo info = MIPSGetInfo(op); _dbg_assert_msg_(JIT, !(info & DELAYSLOT), "Never eat a branch op."); _dbg_assert_msg_(JIT, !js.inDelaySlot, "Never eat an instruction inside a delayslot."); @@ -361,7 +361,7 @@ void Jit::Comp_Generic(u32 op) else ERROR_LOG_REPORT(JIT, "Trying to compile instruction that can't be interpreted"); - const int info = MIPSGetInfo(op); + const MIPSInfo info = MIPSGetInfo(op); if ((info & IS_VFPU) != 0 && (info & VFPU_NO_PREFIX) == 0) { // If it does eat them, it'll happen in MIPSCompileOp(). From 4495559b7523ef3749c38b4218914ab0f2bd829e Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 13:41:03 -0700 Subject: [PATCH 015/237] Clean up register usage analysis a bit. --- Core/MIPS/MIPSAnalyst.cpp | 192 ++++++++++++++------------------------ Core/MIPS/MIPSAnalyst.h | 31 +++++- 2 files changed, 97 insertions(+), 126 deletions(-) diff --git a/Core/MIPS/MIPSAnalyst.cpp b/Core/MIPS/MIPSAnalyst.cpp index 84eeb729e9..5a56f2c956 100644 --- a/Core/MIPS/MIPSAnalyst.cpp +++ b/Core/MIPS/MIPSAnalyst.cpp @@ -16,182 +16,130 @@ // https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. #include -#include "../../Globals.h" +#include "Globals.h" -#include "MIPS.h" -#include "MIPSTables.h" -#include "MIPSAnalyst.h" -#include "MIPSCodeUtils.h" -#include "../Debugger/SymbolMap.h" -#include "../Debugger/DebugInterface.h" +#include "Core/MIPS/MIPS.h" +#include "Core/MIPS/MIPSTables.h" +#include "Core/MIPS/MIPSAnalyst.h" +#include "Core/MIPS/MIPSCodeUtils.h" +#include "Core/Debugger/SymbolMap.h" +#include "Core/Debugger/DebugInterface.h" using namespace MIPSCodeUtils; using namespace std; +#define NUM_MIPS_GPRS 32 + namespace MIPSAnalyst { - RegisterAnalysisResults regAnal[32]; - RegisterAnalysisResults total[32]; - int numAnalysisDone=0; + RegisterAnalysisResults gprAnal[NUM_MIPS_GPRS]; - int GetOutReg(u32 op) - { + // Only can ever output a single reg. + int GetOutGPReg(u32 op) { MIPSInfo opinfo = MIPSGetInfo(op); - if (opinfo & OUT_RT) - return MIPS_GET_RT(op); - if (opinfo & OUT_RD) - return MIPS_GET_RD(op); - if (opinfo & OUT_RA) - return MIPS_REG_RA; + if ((opinfo & IS_VFPU) == 0) { + if (opinfo & OUT_RT) { + return MIPS_GET_RT(op); + } + if (opinfo & OUT_RD) { + return MIPS_GET_RD(op); + } + if (opinfo & OUT_RA) { + return MIPS_REG_RA; + } + } return -1; } - bool ReadsFromReg(u32 op, u32 reg) - { - MIPSInfo opinfo = MIPSGetInfo(op); - if (opinfo & IN_RT) - { - if (MIPS_GET_RT(op) == reg) + bool ReadsFromGPReg(u32 op, u32 reg) { + MIPSInfo info = MIPSGetInfo(op); + if ((info & IS_VFPU) == 0) { + if ((info & IN_RS) != 0 && MIPS_GET_RS(op) == reg) { return true; - } - if (opinfo & IN_RS) - { - if (MIPS_GET_RS(op) == reg) - return true; - } - return false; //TODO: there are more cases! - } - - // TODO: Remove me? - bool IsDelaySlotNice(u32 branch, u32 delayslot) - { - int outReg = GetOutReg(delayslot); - if (outReg != -1) - { - if (ReadsFromReg(branch, outReg)) - { - return false; //evil :( } - else - { - return false; //aggh this should be true but doesn't work + if ((info & IN_RT) != 0 && MIPS_GET_RT(op) == reg) { + return true; } } - else - { - // Check for FPU flag - if ((MIPSGetInfo(delayslot) & OUT_FPUFLAG) && (MIPSGetInfo(branch) & IN_FPUFLAG)) - return false; - - return true; //nice :) - } + return false; } - bool IsDelaySlotNiceReg(u32 branchOp, u32 op, int reg1, int reg2) - { + bool IsDelaySlotNiceReg(u32 branchOp, u32 op, int reg1, int reg2) { // $0 is never an out reg, it's always 0. - if (reg1 != 0 && GetOutReg(op) == reg1) + if (reg1 != 0 && GetOutGPReg(op) == reg1) { return false; - if (reg2 != 0 && GetOutReg(op) == reg2) + } + if (reg2 != 0 && GetOutGPReg(op) == reg2) { return false; + } return true; } - bool IsDelaySlotNiceVFPU(u32 branchOp, u32 op) - { + bool IsDelaySlotNiceVFPU(u32 branchOp, u32 op) { // TODO: There may be IS_VFPU cases which are safe... return (MIPSGetInfo(op) & IS_VFPU) == 0; } - bool IsDelaySlotNiceFPU(u32 branchOp, u32 op) - { + bool IsDelaySlotNiceFPU(u32 branchOp, u32 op) { return (MIPSGetInfo(op) & OUT_FPUFLAG) == 0; } - bool IsSyscall(u32 op) - { + bool IsSyscall(u32 op) { // Syscalls look like this: 0000 00-- ---- ---- ---- --00 1100 return (op >> 26) == 0 && (op & 0x3f) == 12; } - void Analyze(u32 address) - { + void Analyze(u32 address) { + const int MAX_ANALYZE = 10000; + //set everything to -1 (FF) - memset(regAnal, 255, sizeof(AnalysisResults)*32); - for (int i=0; i<32; i++) - { - regAnal[i].used=false; - regAnal[i].readCount=0; - regAnal[i].writeCount=0; - regAnal[i].readAsAddrCount=0; + memset(gprAnal, 255, sizeof(AnalysisResults) * NUM_MIPS_GPRS); + for (int i = 0; i < NUM_MIPS_GPRS; i++) { + gprAnal[i].used = false; + gprAnal[i].readCount = 0; + gprAnal[i].writeCount = 0; + gprAnal[i].readAsAddrCount = 0; } - u32 addr = address; - bool exitFlag = false; - while (true) - { + for (u32 addr = address, endAddr = address + MAX_ANALYZE; addr <= endAddr; addr += 4) { u32 op = Memory::Read_Instruction(addr); MIPSInfo info = MIPSGetInfo(op); - for (int reg=0; reg < 32; reg++) - { - int rs = MIPS_GET_RS(op); - int rt = MIPS_GET_RT(op); - int rd = MIPS_GET_RD(op); + int rs = MIPS_GET_RS(op); + int rt = MIPS_GET_RT(op); - if ( - ((info & IN_RS) && (info & IN_RS_ADDR) == IN_RS && (rs == reg)) || - ((info & IN_RT) && (rt == reg))) - { - if (regAnal[reg].firstRead == -1) - regAnal[reg].firstRead = addr; - regAnal[reg].lastRead = addr; - regAnal[reg].readCount++; - regAnal[reg].used=true; - } - if ( - ((info & IN_RS_ADDR) && (rs == reg)) - ) - { - if (regAnal[reg].firstReadAsAddr == -1) - regAnal[reg].firstReadAsAddr = addr; - regAnal[reg].lastReadAsAddr = addr; - regAnal[reg].readAsAddrCount++; - regAnal[reg].used=true; - } - if ( - ((info & OUT_RT) && (rt == reg)) || - ((info & OUT_RD) && (rd == reg)) || - ((info & OUT_RA) && (reg == MIPS_REG_RA)) - ) - { - if (regAnal[reg].firstWrite == -1) - regAnal[reg].firstWrite = addr; - regAnal[reg].lastWrite = addr; - regAnal[reg].writeCount++; - regAnal[reg].used=true; + if (info & IN_RS) { + if ((info & IN_RS_ADDR) == IN_RS_ADDR) { + gprAnal[rs].MarkReadAsAddr(addr); + } else { + gprAnal[rs].MarkRead(addr); } } - if (exitFlag) //delay slot done, let's quit! - break; - - if ((info & IS_JUMP) || (info & IS_CONDBRANCH)) - { - exitFlag = true; // now do the delay slot + if (info & IN_RT) { + gprAnal[rt].MarkRead(addr); } - addr += 4; + int outReg = GetOutGPReg(op); + if (outReg != -1) { + gprAnal[outReg].MarkWrite(addr); + } + + if (info & DELAYSLOT) + { + // Let's just finish the delay slot before bailing. + endAddr = addr + 4; + } } int numUsedRegs=0; static int totalUsedRegs=0; static int numAnalyzings=0; - for (int i=0; i<32; i++) - { - if (regAnal[i].used) + for (int i = 0; i < NUM_MIPS_GPRS; i++) { + if (gprAnal[i].used) { numUsedRegs++; + } } totalUsedRegs+=numUsedRegs; numAnalyzings++; diff --git a/Core/MIPS/MIPSAnalyst.h b/Core/MIPS/MIPSAnalyst.h index 510981d580..7dcdbd4721 100644 --- a/Core/MIPS/MIPSAnalyst.h +++ b/Core/MIPS/MIPSAnalyst.h @@ -24,8 +24,7 @@ class DebugInterface; namespace MIPSAnalyst { void Analyze(u32 address); - struct RegisterAnalysisResults - { + struct RegisterAnalysisResults { bool used; int firstRead; int lastRead; @@ -41,6 +40,30 @@ namespace MIPSAnalyst int TotalReadCount() {return readCount + readAsAddrCount;} int FirstRead() {return firstReadAsAddr < firstRead ? firstReadAsAddr : firstRead;} int LastRead() {return lastReadAsAddr > lastRead ? lastReadAsAddr : lastRead;} + + void MarkRead(u32 addr) { + if (firstRead == -1) + firstRead = addr; + lastRead = addr; + readCount++; + used = true; + } + + void MarkReadAsAddr(u32 addr) { + if (firstReadAsAddr == -1) + firstReadAsAddr = addr; + lastReadAsAddr = addr; + readAsAddrCount++; + used = true; + } + + void MarkWrite(u32 addr) { + if (firstWrite == -1) + firstWrite = addr; + lastWrite = addr; + writeCount++; + used = true; + } }; struct AnalysisResults @@ -55,8 +78,8 @@ namespace MIPSAnalyst std::vector GetInputRegs(u32 op); std::vector GetOutputRegs(u32 op); - int GetOutReg(u32 op); - bool ReadsFromReg(u32 op, u32 reg); + int GetOutGPReg(u32 op); + bool ReadsFromGPReg(u32 op, u32 reg); bool IsDelaySlotNice(u32 branch, u32 delayslot); bool IsDelaySlotNiceReg(u32 branchOp, u32 op, int reg1, int reg2 = 0); bool IsDelaySlotNiceVFPU(u32 branchOp, u32 op); From ec46fdd06cf5eb464425af43071ae192138c56e0 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 14:35:28 -0700 Subject: [PATCH 016/237] Warning fixes in msgpipes. --- Core/HLE/sceKernelMsgPipe.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Core/HLE/sceKernelMsgPipe.cpp b/Core/HLE/sceKernelMsgPipe.cpp index b07e17f6f8..7915e94502 100644 --- a/Core/HLE/sceKernelMsgPipe.cpp +++ b/Core/HLE/sceKernelMsgPipe.cpp @@ -140,7 +140,7 @@ struct MsgPipe : public KernelObject void AddWaitingThread(std::vector &list, SceUID id, u32 addr, u32 size, int waitMode, u32 transferredBytesAddr) { - MsgPipeWaitingThread thread = { id, addr, size, size, waitMode, transferredBytesAddr }; + MsgPipeWaitingThread thread = { id, addr, size, size, waitMode, { transferredBytesAddr } }; // Start out with 0 transferred bytes while waiting. // TODO: for receive, it might be a different (partial) number. if (thread.transferredBytes.IsValid()) @@ -442,7 +442,7 @@ int __KernelSendMsgPipe(MsgPipe *m, u32 sendBufAddr, u32 sendSize, int waitMode, if (waitMode != SCE_KERNEL_MPW_ASAP && waitMode != SCE_KERNEL_MPW_FULL) { - ERROR_LOG(HLE, "__KernelSendMsgPipe(%d): invalid wait mode", uid, waitMode); + ERROR_LOG(HLE, "__KernelSendMsgPipe(%d): invalid wait mode %d", uid, waitMode); return SCE_KERNEL_ERROR_ILLEGAL_MODE; } @@ -605,7 +605,7 @@ int __KernelReceiveMsgPipe(MsgPipe *m, u32 receiveBufAddr, u32 receiveSize, int if (waitMode != SCE_KERNEL_MPW_ASAP && waitMode != SCE_KERNEL_MPW_FULL) { - ERROR_LOG(HLE, "__KernelReceiveMsgPipe(%d): invalid wait mode", uid, waitMode); + ERROR_LOG(HLE, "__KernelReceiveMsgPipe(%d): invalid wait mode %d", uid, waitMode); return SCE_KERNEL_ERROR_ILLEGAL_MODE; } From 109ad17ac6ccc6f49a4cdb59d5894c36e43b1f6d Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 14:43:49 -0700 Subject: [PATCH 017/237] Use a typesafe struct for opcodes. Also, correctly read delayslots using Read_Instruction on ARM. --- Core/Debugger/SymbolMap.cpp | 6 +- Core/ELF/ElfReader.cpp | 6 +- Core/HLE/HLE.cpp | 2 +- Core/HLE/HLE.h | 2 +- Core/HLE/sceKernelModule.cpp | 4 +- Core/MIPS/ARM/ArmCompALU.cpp | 20 ++-- Core/MIPS/ARM/ArmCompBranch.cpp | 36 +++---- Core/MIPS/ARM/ArmCompFPU.cpp | 12 +-- Core/MIPS/ARM/ArmCompLoadStore.cpp | 10 +- Core/MIPS/ARM/ArmCompVFPU.cpp | 62 +++++------ Core/MIPS/ARM/ArmJit.cpp | 16 +-- Core/MIPS/ARM/ArmJit.h | 132 +++++++++++------------ Core/MIPS/JitCommon/JitBlockCache.cpp | 18 ++-- Core/MIPS/JitCommon/JitBlockCache.h | 8 +- Core/MIPS/MIPS.h | 7 +- Core/MIPS/MIPSAnalyst.cpp | 26 ++--- Core/MIPS/MIPSAnalyst.h | 22 ++-- Core/MIPS/MIPSCodeUtils.cpp | 18 ++-- Core/MIPS/MIPSCodeUtils.h | 2 +- Core/MIPS/MIPSDis.cpp | 58 +++++----- Core/MIPS/MIPSDis.h | 65 +++++------ Core/MIPS/MIPSDisVFPU.cpp | 62 +++++------ Core/MIPS/MIPSDisVFPU.h | 60 +++++------ Core/MIPS/MIPSInt.cpp | 58 +++++----- Core/MIPS/MIPSInt.h | 56 +++++----- Core/MIPS/MIPSIntVFPU.cpp | 108 +++++++++---------- Core/MIPS/MIPSIntVFPU.h | 112 +++++++++---------- Core/MIPS/MIPSStackWalk.cpp | 10 +- Core/MIPS/MIPSTables.cpp | 26 ++--- Core/MIPS/MIPSTables.h | 19 ++-- Core/MIPS/MIPSVFPUUtils.cpp | 4 +- Core/MIPS/MIPSVFPUUtils.h | 4 +- Core/MIPS/x86/CompALU.cpp | 24 ++--- Core/MIPS/x86/CompBranch.cpp | 48 ++++----- Core/MIPS/x86/CompFPU.cpp | 12 +-- Core/MIPS/x86/CompLoadStore.cpp | 26 ++--- Core/MIPS/x86/CompVFPU.cpp | 66 ++++++------ Core/MIPS/x86/Jit.cpp | 20 ++-- Core/MIPS/x86/Jit.h | 150 +++++++++++++------------- Core/MemMap.cpp | 10 +- Core/MemMap.h | 33 +++++- 41 files changed, 736 insertions(+), 704 deletions(-) diff --git a/Core/Debugger/SymbolMap.cpp b/Core/Debugger/SymbolMap.cpp index b3fa7a9145..d1bd50f947 100644 --- a/Core/Debugger/SymbolMap.cpp +++ b/Core/Debugger/SymbolMap.cpp @@ -46,7 +46,7 @@ static u32 ComputeHash(u32 start, u32 size) { u32 hash=0; for (unsigned int i=start; i= 16 && entry.type == ST_FUNCTION) { - u32 inst = Memory::Read_Instruction(entry.vaddress); //try to make a bigger number of different vals sometime + u32 inst = Memory::Read_Instruction(entry.vaddress).encoding; //try to make a bigger number of different vals sometime if (inst != 0) { char temp[64]; @@ -633,7 +633,7 @@ void SymbolMap::UseFuncSignaturesFile(const char *filename, u32 maxAddress) sprintf(temp,"Scanning: %08x",addr); lastAddr=addr; } - u32 inst = Memory::Read_Instruction(addr); + u32 inst = Memory::Read_Instruction(addr).encoding; if (!inst) continue; diff --git a/Core/ELF/ElfReader.cpp b/Core/ELF/ElfReader.cpp index 54ceacdb4f..d7af78c335 100644 --- a/Core/ELF/ElfReader.cpp +++ b/Core/ELF/ElfReader.cpp @@ -68,7 +68,7 @@ void ElfReader::LoadRelocations(Elf32_Rel *rels, int numRelocs) addr += segmentVAddr[readwrite]; - u32 op = Memory::ReadUnchecked_U32(addr); + u32 op = Memory::Read_Instruction(addr).encoding; const bool log = false; //log=true; @@ -145,7 +145,7 @@ void ElfReader::LoadRelocations(Elf32_Rel *rels, int numRelocs) case R_MIPS_16: { char temp[256]; - MIPSDisAsm(op, 0, temp); + MIPSDisAsm(MIPSOpcode(op), 0, temp); ERROR_LOG_REPORT(LOADER, "WARNING: Unsupported R_MIPS_16 reloc @ %08x : %s", addr, temp); } break; @@ -157,7 +157,7 @@ void ElfReader::LoadRelocations(Elf32_Rel *rels, int numRelocs) default: { char temp[256]; - MIPSDisAsm(op, 0, temp); + MIPSDisAsm(MIPSOpcode(op), 0, temp); ERROR_LOG_REPORT(LOADER,"ARGH IT'S AN UNKNOWN RELOCATION!!!!!!!! %08x, type=%d : %s", addr, type, temp); } break; diff --git a/Core/HLE/HLE.cpp b/Core/HLE/HLE.cpp index 86bbcbdb17..772ff93c21 100644 --- a/Core/HLE/HLE.cpp +++ b/Core/HLE/HLE.cpp @@ -456,7 +456,7 @@ inline void updateSyscallStats(int modulenum, int funcnum, double total) } } -void CallSyscall(u32 op) +void CallSyscall(MIPSOpcode op) { double start = 0.0; // need to initialize to fix the race condition where g_Config.bShowDebugStats is enabled in the middle of this func. if (g_Config.bShowDebugStats) diff --git a/Core/HLE/HLE.h b/Core/HLE/HLE.h index 1d29280c5c..de34f7f9fc 100644 --- a/Core/HLE/HLE.h +++ b/Core/HLE/HLE.h @@ -114,6 +114,6 @@ void HLEShutdown(); u32 GetNibByName(const char *module, const char *function); u32 GetSyscallOp(const char *module, u32 nib); void WriteSyscall(const char *module, u32 nib, u32 address); -void CallSyscall(u32 op); +void CallSyscall(MIPSOpcode op); void ResolveSyscall(const char *moduleName, u32 nib, u32 address); diff --git a/Core/HLE/sceKernelModule.cpp b/Core/HLE/sceKernelModule.cpp index 1816d66ad5..985565b158 100644 --- a/Core/HLE/sceKernelModule.cpp +++ b/Core/HLE/sceKernelModule.cpp @@ -305,7 +305,7 @@ void WriteVarSymbol(u32 exportAddress, u32 relocAddress, u8 type) static std::vector lastHI16Relocs; static bool lastHI16Processed = true; - u32 relocData = Memory::Read_Instruction(relocAddress); + u32 relocData = Memory::Read_Instruction(relocAddress).encoding; switch (type) { @@ -341,7 +341,7 @@ void WriteVarSymbol(u32 exportAddress, u32 relocAddress, u8 type) // The R_MIPS_LO16 and R_MIPS_HI16 will often be *different* relocAddress values. HI16RelocInfo reloc; reloc.addr = relocAddress; - reloc.data = Memory::Read_Instruction(relocAddress); + reloc.data = Memory::Read_Instruction(relocAddress).encoding; lastHI16Relocs.push_back(reloc); lastHI16Processed = false; break; diff --git a/Core/MIPS/ARM/ArmCompALU.cpp b/Core/MIPS/ARM/ArmCompALU.cpp index 7d7bd78084..a0f066a726 100644 --- a/Core/MIPS/ARM/ArmCompALU.cpp +++ b/Core/MIPS/ARM/ArmCompALU.cpp @@ -61,7 +61,7 @@ namespace MIPSComp } } - void Jit::Comp_IType(u32 op) + void Jit::Comp_IType(MIPSOpcode op) { CONDITIONAL_DISABLE; s32 simm = (s32)(s16)(op & 0xFFFF); // sign extension @@ -127,7 +127,7 @@ namespace MIPSComp } } - void Jit::Comp_RType2(u32 op) + void Jit::Comp_RType2(MIPSOpcode op) { CONDITIONAL_DISABLE; int rs = _RS; @@ -180,7 +180,7 @@ namespace MIPSComp } } - void Jit::Comp_RType3(u32 op) + void Jit::Comp_RType3(MIPSOpcode op) { CONDITIONAL_DISABLE; int rt = _RT; @@ -325,7 +325,7 @@ namespace MIPSComp } } - void Jit::CompShiftImm(u32 op, ArmGen::ShiftType shiftType) + void Jit::CompShiftImm(MIPSOpcode op, ArmGen::ShiftType shiftType) { int rd = _RD; int rt = _RT; @@ -335,7 +335,7 @@ namespace MIPSComp MOV(gpr.R(rd), Operand2(gpr.R(rt), shiftType, sa)); } - void Jit::CompShiftVar(u32 op, ArmGen::ShiftType shiftType) + void Jit::CompShiftVar(MIPSOpcode op, ArmGen::ShiftType shiftType) { int rd = _RD; int rt = _RT; @@ -352,7 +352,7 @@ namespace MIPSComp MOV(gpr.R(rd), Operand2(gpr.R(rt), shiftType, R0)); } - void Jit::Comp_ShiftType(u32 op) + void Jit::Comp_ShiftType(MIPSOpcode op) { CONDITIONAL_DISABLE; int rs = _RS; @@ -379,7 +379,7 @@ namespace MIPSComp } } - void Jit::Comp_Special3(u32 op) + void Jit::Comp_Special3(MIPSOpcode op) { CONDITIONAL_DISABLE; @@ -447,7 +447,7 @@ namespace MIPSComp } } - void Jit::Comp_Allegrex(u32 op) + void Jit::Comp_Allegrex(MIPSOpcode op) { CONDITIONAL_DISABLE; int rt = _RT; @@ -505,7 +505,7 @@ namespace MIPSComp } } - void Jit::Comp_Allegrex2(u32 op) + void Jit::Comp_Allegrex2(MIPSOpcode op) { CONDITIONAL_DISABLE; int rt = _RT; @@ -538,7 +538,7 @@ namespace MIPSComp } } - void Jit::Comp_MulDivType(u32 op) + void Jit::Comp_MulDivType(MIPSOpcode op) { CONDITIONAL_DISABLE; int rt = _RT; diff --git a/Core/MIPS/ARM/ArmCompBranch.cpp b/Core/MIPS/ARM/ArmCompBranch.cpp index 69e6252283..d80ec2d4f1 100644 --- a/Core/MIPS/ARM/ArmCompBranch.cpp +++ b/Core/MIPS/ARM/ArmCompBranch.cpp @@ -53,7 +53,7 @@ using namespace MIPSAnalyst; namespace MIPSComp { -void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely) +void Jit::BranchRSRTComp(MIPSOpcode op, ArmGen::CCFlags cc, bool likely) { if (js.inDelaySlot) { ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); @@ -64,7 +64,7 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely) int rs = _RS; u32 targetAddr = js.compilerPC + offset + 4; - u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC+4); + MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC+4); bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs); CONDITIONAL_NICE_DELAYSLOT; if (!likely && delaySlotIsNice) @@ -113,7 +113,7 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely) } -void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely) +void Jit::BranchRSZeroComp(MIPSOpcode op, ArmGen::CCFlags cc, bool andLink, bool likely) { if (js.inDelaySlot) { ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); @@ -123,7 +123,7 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely int rs = _RS; u32 targetAddr = js.compilerPC + offset + 4; - u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4); + MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs); CONDITIONAL_NICE_DELAYSLOT; if (!likely && delaySlotIsNice) @@ -164,7 +164,7 @@ void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely } -void Jit::Comp_RelBranch(u32 op) +void Jit::Comp_RelBranch(MIPSOpcode op) { // The CC flags here should be opposite of the actual branch becuase they skip the branching action. switch (op>>26) @@ -187,7 +187,7 @@ void Jit::Comp_RelBranch(u32 op) } } -void Jit::Comp_RelBranchRI(u32 op) +void Jit::Comp_RelBranchRI(MIPSOpcode op) { switch ((op >> 16) & 0x1F) { @@ -206,7 +206,7 @@ void Jit::Comp_RelBranchRI(u32 op) } // If likely is set, discard the branch slot if NOT taken. -void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely) +void Jit::BranchFPFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely) { if (js.inDelaySlot) { ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); @@ -215,7 +215,7 @@ void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely) int offset = _IMM16 << 2; u32 targetAddr = js.compilerPC + offset + 4; - u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4); + MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); bool delaySlotIsNice = IsDelaySlotNiceFPU(op, delaySlotOp); CONDITIONAL_NICE_DELAYSLOT; if (!likely && delaySlotIsNice) @@ -249,7 +249,7 @@ void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely) js.compiling = false; } -void Jit::Comp_FPUBranch(u32 op) +void Jit::Comp_FPUBranch(MIPSOpcode op) { switch((op >> 16) & 0x1f) { @@ -264,7 +264,7 @@ void Jit::Comp_FPUBranch(u32 op) } // If likely is set, discard the branch slot if NOT taken. -void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely) +void Jit::BranchVFPUFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely) { if (js.inDelaySlot) { ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); @@ -273,7 +273,7 @@ void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely) int offset = _IMM16 << 2; u32 targetAddr = js.compilerPC + offset + 4; - u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4); + MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); // Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle) // The behavior is undefined - the CPU may take the second branch even if the first one passes. @@ -321,7 +321,7 @@ void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely) js.compiling = false; } -void Jit::Comp_VBranch(u32 op) +void Jit::Comp_VBranch(MIPSOpcode op) { switch ((op >> 16) & 3) { @@ -332,7 +332,7 @@ void Jit::Comp_VBranch(u32 op) } } -void Jit::Comp_Jump(u32 op) +void Jit::Comp_Jump(MIPSOpcode op) { if (js.inDelaySlot) { ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); @@ -364,7 +364,7 @@ void Jit::Comp_Jump(u32 op) js.compiling = false; } -void Jit::Comp_JumpReg(u32 op) +void Jit::Comp_JumpReg(MIPSOpcode op) { if (js.inDelaySlot) { ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); @@ -372,7 +372,7 @@ void Jit::Comp_JumpReg(u32 op) } int rs = _RS; - u32 delaySlotOp = Memory::ReadUnchecked_U32(js.compilerPC + 4); + MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs); CONDITIONAL_NICE_DELAYSLOT; @@ -413,7 +413,7 @@ void Jit::Comp_JumpReg(u32 op) } -void Jit::Comp_Syscall(u32 op) +void Jit::Comp_Syscall(MIPSOpcode op) { FlushAll(); @@ -428,7 +428,7 @@ void Jit::Comp_Syscall(u32 op) QuickCallFunction(R1, (void *)GetFunc("FakeSysCalls", NID_IDLE)->func); else { - MOVI2R(R0, op); + MOVI2R(R0, op.encoding); QuickCallFunction(R1, (void *)&CallSyscall); } RestoreDowncount(); @@ -437,7 +437,7 @@ void Jit::Comp_Syscall(u32 op) js.compiling = false; } -void Jit::Comp_Break(u32 op) +void Jit::Comp_Break(MIPSOpcode op) { Comp_Generic(op); WriteSyscallExit(); diff --git a/Core/MIPS/ARM/ArmCompFPU.cpp b/Core/MIPS/ARM/ArmCompFPU.cpp index 0fc048e2b9..590694334e 100644 --- a/Core/MIPS/ARM/ArmCompFPU.cpp +++ b/Core/MIPS/ARM/ArmCompFPU.cpp @@ -40,7 +40,7 @@ namespace MIPSComp { -void Jit::Comp_FPU3op(u32 op) +void Jit::Comp_FPU3op(MIPSOpcode op) { CONDITIONAL_DISABLE; @@ -54,7 +54,7 @@ void Jit::Comp_FPU3op(u32 op) case 0: VADD(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) + F(ft); //add case 1: VSUB(fpr.R(fd), fpr.R(fs), fpr.R(ft)); break; //F(fd) = F(fs) - F(ft); //sub case 2: { //F(fd) = F(fs) * F(ft); //mul - u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4); + MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4); // Optimization possible if destination is the same if (fd == (int)((nextOp>>6) & 0x1F)) { // VMUL + VNEG -> VNMUL @@ -78,7 +78,7 @@ void Jit::Comp_FPU3op(u32 op) extern int logBlocks; -void Jit::Comp_FPULS(u32 op) +void Jit::Comp_FPULS(MIPSOpcode op) { CONDITIONAL_DISABLE; @@ -167,7 +167,7 @@ void Jit::Comp_FPULS(u32 op) } } -void Jit::Comp_FPUComp(u32 op) { +void Jit::Comp_FPUComp(MIPSOpcode op) { CONDITIONAL_DISABLE; int opc = op & 0xF; if (opc >= 8) opc -= 8; // alias @@ -233,7 +233,7 @@ void Jit::Comp_FPUComp(u32 op) { STR(R0, CTXREG, offsetof(MIPSState, fpcond)); } -void Jit::Comp_FPU2op(u32 op) +void Jit::Comp_FPU2op(MIPSOpcode op) { CONDITIONAL_DISABLE; @@ -307,7 +307,7 @@ void Jit::Comp_FPU2op(u32 op) } } -void Jit::Comp_mxc1(u32 op) +void Jit::Comp_mxc1(MIPSOpcode op) { CONDITIONAL_DISABLE; diff --git a/Core/MIPS/ARM/ArmCompLoadStore.cpp b/Core/MIPS/ARM/ArmCompLoadStore.cpp index 7855d1408a..005eaa6a3d 100644 --- a/Core/MIPS/ARM/ArmCompLoadStore.cpp +++ b/Core/MIPS/ARM/ArmCompLoadStore.cpp @@ -121,7 +121,7 @@ namespace MIPSComp SetCC(CC_GT); } - void Jit::Comp_ITypeMem(u32 op) + void Jit::Comp_ITypeMem(MIPSOpcode op) { CONDITIONAL_DISABLE; int offset = (signed short)(op&0xFFFF); @@ -194,13 +194,13 @@ namespace MIPSComp if (!js.inDelaySlot) { // Optimisation: Combine to single unaligned load/store bool isLeft = (o == 34 || o == 42); - u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4); + MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4); // Find a matching shift in opposite direction with opposite offset. - if (nextOp == (isLeft ? (op + (4<<26) - 3) - : (op - (4<<26) + 3))) + if (nextOp == (isLeft ? (op.encoding + (4<<26) - 3) + : (op.encoding - (4<<26) + 3))) { EatInstruction(nextOp); - nextOp = ((load ? 35 : 43) << 26) | ((isLeft ? nextOp : op) & 0x03FFFFFF); //lw, sw + nextOp = MIPSOpcode(((load ? 35 : 43) << 26) | ((isLeft ? nextOp : op) & 0x03FFFFFF)); //lw, sw Comp_ITypeMem(nextOp); return; } diff --git a/Core/MIPS/ARM/ArmCompVFPU.cpp b/Core/MIPS/ARM/ArmCompVFPU.cpp index 27e7c419ae..6093c5d53f 100644 --- a/Core/MIPS/ARM/ArmCompVFPU.cpp +++ b/Core/MIPS/ARM/ArmCompVFPU.cpp @@ -73,7 +73,7 @@ namespace MIPSComp return IsOverlapSafeAllowS(dreg, di, sn, sregs, tn, tregs) && sregs[di] != dreg; } - void Jit::Comp_VPFX(u32 op) + void Jit::Comp_VPFX(MIPSOpcode op) { CONDITIONAL_DISABLE; int data = op & 0xFFFFF; @@ -231,7 +231,7 @@ namespace MIPSComp } } - void Jit::Comp_SV(u32 op) { + void Jit::Comp_SV(MIPSOpcode op) { CONDITIONAL_DISABLE; s32 imm = (signed short)(op&0xFFFC); @@ -321,7 +321,7 @@ namespace MIPSComp } } - void Jit::Comp_SVQ(u32 op) + void Jit::Comp_SVQ(MIPSOpcode op) { CONDITIONAL_DISABLE; @@ -433,7 +433,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_VVectorInit(u32 op) + void Jit::Comp_VVectorInit(MIPSOpcode op) { CONDITIONAL_DISABLE; @@ -470,7 +470,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_VIdt(u32 op) { + void Jit::Comp_VIdt(MIPSOpcode op) { CONDITIONAL_DISABLE if (js.HasUnknownPrefix() || disablePrefixes) { @@ -507,7 +507,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_VMatrixInit(u32 op) + void Jit::Comp_VMatrixInit(MIPSOpcode op) { CONDITIONAL_DISABLE; @@ -555,7 +555,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_VDot(u32 op) { + void Jit::Comp_VDot(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix() || disablePrefixes) { DISABLE; @@ -592,7 +592,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_Vhoriz(u32 op) { + void Jit::Comp_Vhoriz(MIPSOpcode op) { DISABLE; switch ((op >> 16) & 31) { @@ -603,12 +603,12 @@ namespace MIPSComp } } - void Jit::Comp_VHdp(u32 op) { + void Jit::Comp_VHdp(MIPSOpcode op) { // Similar to vdot DISABLE; } - void Jit::Comp_VecDo3(u32 op) { + void Jit::Comp_VecDo3(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix() || disablePrefixes) { @@ -723,7 +723,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_VV2Op(u32 op) { + void Jit::Comp_VV2Op(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix() || disablePrefixes) { @@ -849,7 +849,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_Vi2f(u32 op) { + void Jit::Comp_Vi2f(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix() || disablePrefixes) @@ -895,7 +895,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_Vf2i(u32 op) { + void Jit::Comp_Vf2i(MIPSOpcode op) { CONDITIONAL_DISABLE; DISABLE; @@ -963,7 +963,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_Mftv(u32 op) + void Jit::Comp_Mftv(MIPSOpcode op) { CONDITIONAL_DISABLE; @@ -1024,7 +1024,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_Vmtvc(u32 op) { + void Jit::Comp_Vmtvc(MIPSOpcode op) { CONDITIONAL_DISABLE; int vs = _VS; @@ -1045,7 +1045,7 @@ namespace MIPSComp } } - void Jit::Comp_Vmmov(u32 op) { + void Jit::Comp_Vmmov(MIPSOpcode op) { CONDITIONAL_DISABLE; // TODO: This probably ignores prefixes? @@ -1086,7 +1086,7 @@ namespace MIPSComp } } - void Jit::Comp_VScl(u32 op) { + void Jit::Comp_VScl(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix() || disablePrefixes) { @@ -1135,7 +1135,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_Vmmul(u32 op) { + void Jit::Comp_Vmmul(MIPSOpcode op) { CONDITIONAL_DISABLE; // TODO: This probably ignores prefixes? @@ -1177,11 +1177,11 @@ namespace MIPSComp } } - void Jit::Comp_Vmscl(u32 op) { + void Jit::Comp_Vmscl(MIPSOpcode op) { DISABLE; } - void Jit::Comp_Vtfm(u32 op) { + void Jit::Comp_Vtfm(MIPSOpcode op) { CONDITIONAL_DISABLE; // TODO: This probably ignores prefixes? Or maybe uses D? @@ -1241,23 +1241,23 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_VCrs(u32 op) { + void Jit::Comp_VCrs(MIPSOpcode op) { DISABLE; } - void Jit::Comp_VDet(u32 op) { + void Jit::Comp_VDet(MIPSOpcode op) { DISABLE; } - void Jit::Comp_Vi2x(u32 op) { + void Jit::Comp_Vi2x(MIPSOpcode op) { DISABLE; } - void Jit::Comp_Vx2i(u32 op) { + void Jit::Comp_Vx2i(MIPSOpcode op) { DISABLE; } - void Jit::Comp_VCrossQuat(u32 op) { + void Jit::Comp_VCrossQuat(MIPSOpcode op) { // This op does not support prefixes. if (js.HasUnknownPrefix() || disablePrefixes) DISABLE; @@ -1303,7 +1303,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_Vcmp(u32 op) { + void Jit::Comp_Vcmp(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix() || disablePrefixes) @@ -1441,7 +1441,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_Vcmov(u32 op) { + void Jit::Comp_Vcmov(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix() || disablePrefixes) @@ -1489,7 +1489,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_Viim(u32 op) { + void Jit::Comp_Viim(MIPSOpcode op) { CONDITIONAL_DISABLE; u8 dreg; @@ -1503,7 +1503,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_Vfim(u32 op) { + void Jit::Comp_Vfim(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix() || disablePrefixes) { @@ -1523,7 +1523,7 @@ namespace MIPSComp fpr.ReleaseSpillLocksAndDiscardTemps(); } - void Jit::Comp_Vcst(u32 op) { + void Jit::Comp_Vcst(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix() || disablePrefixes) { @@ -1572,7 +1572,7 @@ namespace MIPSComp } // Very heavily used by FF:CC - void Jit::Comp_VRot(u32 op) { + void Jit::Comp_VRot(MIPSOpcode op) { // Not sure about the ABI so I disable on non-Android. #if !defined(ARMV7) || !defined(ANDROID) DISABLE; diff --git a/Core/MIPS/ARM/ArmJit.cpp b/Core/MIPS/ARM/ArmJit.cpp index 48f34e3401..049b7105bc 100644 --- a/Core/MIPS/ARM/ArmJit.cpp +++ b/Core/MIPS/ARM/ArmJit.cpp @@ -126,11 +126,11 @@ void Jit::ClearCacheAt(u32 em_address) void Jit::CompileAt(u32 addr) { - u32 op = Memory::Read_Instruction(addr); + MIPSOpcode op = Memory::Read_Instruction(addr); MIPSCompileOp(op); } -void Jit::EatInstruction(u32 op) +void Jit::EatInstruction(MIPSOpcode op) { MIPSInfo info = MIPSGetInfo(op); _dbg_assert_msg_(JIT, !(info & DELAYSLOT), "Never eat a branch op."); @@ -149,7 +149,7 @@ void Jit::CompileDelaySlot(int flags) MRS(R8); // Save flags register. R8 is preserved through function calls and is not allocated. js.inDelaySlot = true; - u32 op = Memory::Read_Instruction(js.compilerPC + 4); + MIPSOpcode op = Memory::Read_Instruction(js.compilerPC + 4); MIPSCompileOp(op); js.inDelaySlot = false; @@ -224,7 +224,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b) { gpr.SetCompilerPC(js.compilerPC); // Let it know for log messages fpr.SetCompilerPC(js.compilerPC); - u32 inst = Memory::Read_Instruction(js.compilerPC); + MIPSOpcode inst = Memory::Read_Instruction(js.compilerPC); js.downcountAmount += MIPSGetInstructionCycleEstimate(inst); MIPSCompileOp(inst); @@ -266,13 +266,13 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b) return b->normalEntry; } -void Jit::Comp_RunBlock(u32 op) +void Jit::Comp_RunBlock(MIPSOpcode op) { // This shouldn't be necessary, the dispatcher should catch us before we get here. ERROR_LOG(DYNA_REC, "Comp_RunBlock should never be reached!"); } -void Jit::Comp_Generic(u32 op) +void Jit::Comp_Generic(MIPSOpcode op) { FlushAll(); MIPSInterpretFunc func = MIPSGetInterpretFunc(op); @@ -281,7 +281,7 @@ void Jit::Comp_Generic(u32 op) SaveDowncount(); MOVI2R(R0, js.compilerPC); MovToPC(R0); - MOVI2R(R0, op); + MOVI2R(R0, op.encoding); QuickCallFunction(R1, (void *)func); RestoreDowncount(); } @@ -383,7 +383,7 @@ void Jit::WriteSyscallExit() B((const void *)dispatcherCheckCoreState); } -void Jit::Comp_DoNothing(u32 op) { } +void Jit::Comp_DoNothing(MIPSOpcode op) { } #define _RS ((op>>21) & 0x1F) #define _RT ((op>>16) & 0x1F) diff --git a/Core/MIPS/ARM/ArmJit.h b/Core/MIPS/ARM/ArmJit.h index 73bca7f25a..689361e221 100644 --- a/Core/MIPS/ARM/ArmJit.h +++ b/Core/MIPS/ARM/ArmJit.h @@ -152,7 +152,7 @@ public: // Compiled ops should ignore delay slots // the compiler will take care of them by itself // OR NOT - void Comp_Generic(u32 op); + void Comp_Generic(MIPSOpcode op); void RunLoopUntil(u64 globalticks); @@ -161,71 +161,71 @@ public: void CompileDelaySlot(int flags); void CompileAt(u32 addr); - void EatInstruction(u32 op); - void Comp_RunBlock(u32 op); + void EatInstruction(MIPSOpcode op); + void Comp_RunBlock(MIPSOpcode op); // Ops - void Comp_ITypeMem(u32 op); + void Comp_ITypeMem(MIPSOpcode op); - void Comp_RelBranch(u32 op); - void Comp_RelBranchRI(u32 op); - void Comp_FPUBranch(u32 op); - void Comp_FPULS(u32 op); - void Comp_FPUComp(u32 op); - void Comp_Jump(u32 op); - void Comp_JumpReg(u32 op); - void Comp_Syscall(u32 op); - void Comp_Break(u32 op); + void Comp_RelBranch(MIPSOpcode op); + void Comp_RelBranchRI(MIPSOpcode op); + void Comp_FPUBranch(MIPSOpcode op); + void Comp_FPULS(MIPSOpcode op); + void Comp_FPUComp(MIPSOpcode op); + void Comp_Jump(MIPSOpcode op); + void Comp_JumpReg(MIPSOpcode op); + void Comp_Syscall(MIPSOpcode op); + void Comp_Break(MIPSOpcode op); - void Comp_IType(u32 op); - void Comp_RType2(u32 op); - void Comp_RType3(u32 op); - void Comp_ShiftType(u32 op); - void Comp_Allegrex(u32 op); - void Comp_Allegrex2(u32 op); - void Comp_VBranch(u32 op); - void Comp_MulDivType(u32 op); - void Comp_Special3(u32 op); + void Comp_IType(MIPSOpcode op); + void Comp_RType2(MIPSOpcode op); + void Comp_RType3(MIPSOpcode op); + void Comp_ShiftType(MIPSOpcode op); + void Comp_Allegrex(MIPSOpcode op); + void Comp_Allegrex2(MIPSOpcode op); + void Comp_VBranch(MIPSOpcode op); + void Comp_MulDivType(MIPSOpcode op); + void Comp_Special3(MIPSOpcode op); - void Comp_FPU3op(u32 op); - void Comp_FPU2op(u32 op); - void Comp_mxc1(u32 op); + void Comp_FPU3op(MIPSOpcode op); + void Comp_FPU2op(MIPSOpcode op); + void Comp_mxc1(MIPSOpcode op); - void Comp_DoNothing(u32 op); + void Comp_DoNothing(MIPSOpcode op); - void Comp_SV(u32 op); - void Comp_SVQ(u32 op); - void Comp_VPFX(u32 op); - void Comp_VVectorInit(u32 op); - void Comp_VMatrixInit(u32 op); - void Comp_VDot(u32 op); - void Comp_VecDo3(u32 op); - void Comp_VV2Op(u32 op); - void Comp_Mftv(u32 op); - void Comp_Vmtvc(u32 op); - void Comp_Vmmov(u32 op); - void Comp_VScl(u32 op); - void Comp_Vmmul(u32 op); - void Comp_Vmscl(u32 op); - void Comp_Vtfm(u32 op); - void Comp_VHdp(u32 op); - void Comp_VCrs(u32 op); - void Comp_VDet(u32 op); - void Comp_Vi2x(u32 op); - void Comp_Vx2i(u32 op); - void Comp_Vf2i(u32 op); - void Comp_Vi2f(u32 op); - void Comp_Vcst(u32 op); - void Comp_Vhoriz(u32 op); - void Comp_VRot(u32 op); - void Comp_VIdt(u32 op); - void Comp_Vcmp(u32 op); - void Comp_Vcmov(u32 op); - void Comp_Viim(u32 op); - void Comp_Vfim(u32 op); - void Comp_VCrossQuat(u32 op); - void Comp_Vsge(u32 op); - void Comp_Vslt(u32 op); + void Comp_SV(MIPSOpcode op); + void Comp_SVQ(MIPSOpcode op); + void Comp_VPFX(MIPSOpcode op); + void Comp_VVectorInit(MIPSOpcode op); + void Comp_VMatrixInit(MIPSOpcode op); + void Comp_VDot(MIPSOpcode op); + void Comp_VecDo3(MIPSOpcode op); + void Comp_VV2Op(MIPSOpcode op); + void Comp_Mftv(MIPSOpcode op); + void Comp_Vmtvc(MIPSOpcode op); + void Comp_Vmmov(MIPSOpcode op); + void Comp_VScl(MIPSOpcode op); + void Comp_Vmmul(MIPSOpcode op); + void Comp_Vmscl(MIPSOpcode op); + void Comp_Vtfm(MIPSOpcode op); + void Comp_VHdp(MIPSOpcode op); + void Comp_VCrs(MIPSOpcode op); + void Comp_VDet(MIPSOpcode op); + void Comp_Vi2x(MIPSOpcode op); + void Comp_Vx2i(MIPSOpcode op); + void Comp_Vf2i(MIPSOpcode op); + void Comp_Vi2f(MIPSOpcode op); + void Comp_Vcst(MIPSOpcode op); + void Comp_Vhoriz(MIPSOpcode op); + void Comp_VRot(MIPSOpcode op); + void Comp_VIdt(MIPSOpcode op); + void Comp_Vcmp(MIPSOpcode op); + void Comp_Vcmov(MIPSOpcode op); + void Comp_Viim(MIPSOpcode op); + void Comp_Vfim(MIPSOpcode op); + void Comp_VCrossQuat(MIPSOpcode op); + void Comp_Vsge(MIPSOpcode op); + void Comp_Vslt(MIPSOpcode op); JitBlockCache *GetBlockCache() { return &blocks; } @@ -251,17 +251,17 @@ private: void WriteSyscallExit(); // Utility compilation functions - void BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely); - void BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely); - void BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely); - void BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely); + void BranchFPFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely); + void BranchVFPUFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely); + void BranchRSZeroComp(MIPSOpcode op, ArmGen::CCFlags cc, bool andLink, bool likely); + void BranchRSRTComp(MIPSOpcode op, ArmGen::CCFlags cc, bool likely); // Utilities to reduce duplicated code void CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b)); void CompType3(int rd, int rs, int rt, void (ARMXEmitter::*arithOp2)(ARMReg dst, ARMReg rm, Operand2 rn), u32 (*eval)(u32 a, u32 b), bool isSub = false); - void CompShiftImm(u32 op, ArmGen::ShiftType shiftType); - void CompShiftVar(u32 op, ArmGen::ShiftType shiftType); + void CompShiftImm(MIPSOpcode op, ArmGen::ShiftType shiftType); + void CompShiftVar(MIPSOpcode op, ArmGen::ShiftType shiftType); void ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz); void ApplyPrefixD(const u8 *vregs, VectorSize sz); @@ -307,7 +307,7 @@ public: const u8 *breakpointBailout; }; -typedef void (Jit::*MIPSCompileFunc)(u32 opcode); +typedef void (Jit::*MIPSCompileFunc)(MIPSOpcode opcode); } // namespace MIPSComp diff --git a/Core/MIPS/JitCommon/JitBlockCache.cpp b/Core/MIPS/JitCommon/JitBlockCache.cpp index e51b93861c..ac23c7cafe 100644 --- a/Core/MIPS/JitCommon/JitBlockCache.cpp +++ b/Core/MIPS/JitCommon/JitBlockCache.cpp @@ -157,7 +157,7 @@ void JitBlockCache::FinalizeBlock(int block_num, bool block_link) JitBlock &b = blocks[block_num]; b.originalFirstOpcode = Memory::Read_Opcode_JIT(b.originalAddress); - u32 opcode = GetEmuHackOpForBlock(block_num); + MIPSOpcode opcode = GetEmuHackOpForBlock(block_num); Memory::Write_Opcode_JIT(b.originalAddress, opcode); // Convert the logical address to a physical address for the block map @@ -215,7 +215,7 @@ int binary_search(JitBlock blocks[], const u8 *baseoff, int imin, int imax) return -1; } -int JitBlockCache::GetBlockNumberFromEmuHackOp(u32 inst) const { +int JitBlockCache::GetBlockNumberFromEmuHackOp(MIPSOpcode inst) const { if (!num_blocks || !MIPS_IS_EMUHACK(inst)) // definitely not a JIT block return -1; int off = (inst & MIPS_EMUHACK_VALUE_MASK); @@ -224,16 +224,16 @@ int JitBlockCache::GetBlockNumberFromEmuHackOp(u32 inst) const { return binary_search(blocks, baseoff, 0, num_blocks-1); } -u32 JitBlockCache::GetEmuHackOpForBlock(int blockNum) const { +MIPSOpcode JitBlockCache::GetEmuHackOpForBlock(int blockNum) const { int off = (int)(blocks[blockNum].normalEntry - codeBlock_->GetBasePtr()); - return (MIPS_EMUHACK_OPCODE | off); + return MIPSOpcode(MIPS_EMUHACK_OPCODE | off); } int JitBlockCache::GetBlockNumberFromStartAddress(u32 addr) { if (!blocks) return -1; - u32 inst = Memory::Read_U32(addr); + MIPSOpcode inst = MIPSOpcode(Memory::Read_U32(addr)); int bl = GetBlockNumberFromEmuHackOp(inst); if (bl < 0) return -1; @@ -249,12 +249,12 @@ void JitBlockCache::GetBlockNumbersFromAddress(u32 em_address, std::vector block_numbers->push_back(i); } -u32 JitBlockCache::GetOriginalFirstOp(int block_num) +MIPSOpcode JitBlockCache::GetOriginalFirstOp(int block_num) { if (block_num >= num_blocks || block_num < 0) { //PanicAlert("JitBlockCache::GetOriginalFirstOp - block_num = %u is out of range", block_num); - return block_num; + return MIPSOpcode(block_num); } return blocks[block_num].originalFirstOpcode; } @@ -337,8 +337,8 @@ void JitBlockCache::DestroyBlock(int block_num, bool invalidate) return; } b.invalid = true; - if (Memory::ReadUnchecked_U32(b.originalAddress) == GetEmuHackOpForBlock(block_num)) - Memory::WriteUnchecked_U32(b.originalFirstOpcode, b.originalAddress); + if (Memory::ReadUnchecked_U32(b.originalAddress) == GetEmuHackOpForBlock(block_num).encoding) + Memory::Write_Opcode_JIT(b.originalAddress, b.originalFirstOpcode); b.normalEntry = 0; UnlinkBlock(block_num); diff --git a/Core/MIPS/JitCommon/JitBlockCache.h b/Core/MIPS/JitCommon/JitBlockCache.h index f37fd3bdd7..c7bd5288f0 100644 --- a/Core/MIPS/JitCommon/JitBlockCache.h +++ b/Core/MIPS/JitCommon/JitBlockCache.h @@ -65,7 +65,7 @@ struct JitBlock { u32 exitAddress[MAX_JIT_BLOCK_EXITS]; // 0xFFFFFFFF == unknown u32 originalAddress; - u32 originalFirstOpcode; //to be able to restore + MIPSOpcode originalFirstOpcode; //to be able to restore u16 codeSize; u16 originalSize; u16 blockNum; @@ -107,9 +107,9 @@ public: // Returns a list of block numbers - only one block can start at a particular address, but they CAN overlap. // This one is slow so should only be used for one-shots from the debugger UI, not for anything during runtime. void GetBlockNumbersFromAddress(u32 em_address, std::vector *block_numbers); - int GetBlockNumberFromEmuHackOp(u32 inst) const; + int GetBlockNumberFromEmuHackOp(MIPSOpcode inst) const; - u32 GetOriginalFirstOp(int block_num); + MIPSOpcode GetOriginalFirstOp(int block_num); // DOES NOT WORK CORRECTLY WITH JIT INLINING void InvalidateICache(u32 address, const u32 length); @@ -120,7 +120,7 @@ private: void LinkBlock(int i); void UnlinkBlock(int i); - u32 GetEmuHackOpForBlock(int block_num) const; + MIPSOpcode GetEmuHackOpForBlock(int block_num) const; MIPSState *mips; CodeBlock *codeBlock_; diff --git a/Core/MIPS/MIPS.h b/Core/MIPS/MIPS.h index 5ac5a7c99f..df947fae49 100644 --- a/Core/MIPS/MIPS.h +++ b/Core/MIPS/MIPS.h @@ -17,10 +17,13 @@ #pragma once -#include "../../Globals.h" -#include "../CPU.h" +#include "Globals.h" +#include "Core/MemMap.h" +#include "Core/CPU.h" #include "util/random/rng.h" +typedef Memory::Opcode MIPSOpcode; + enum { MIPS_REG_ZERO=0, diff --git a/Core/MIPS/MIPSAnalyst.cpp b/Core/MIPS/MIPSAnalyst.cpp index 5a56f2c956..b17479d50a 100644 --- a/Core/MIPS/MIPSAnalyst.cpp +++ b/Core/MIPS/MIPSAnalyst.cpp @@ -35,7 +35,7 @@ namespace MIPSAnalyst RegisterAnalysisResults gprAnal[NUM_MIPS_GPRS]; // Only can ever output a single reg. - int GetOutGPReg(u32 op) { + int GetOutGPReg(MIPSOpcode op) { MIPSInfo opinfo = MIPSGetInfo(op); if ((opinfo & IS_VFPU) == 0) { if (opinfo & OUT_RT) { @@ -51,7 +51,7 @@ namespace MIPSAnalyst return -1; } - bool ReadsFromGPReg(u32 op, u32 reg) { + bool ReadsFromGPReg(MIPSOpcode op, u32 reg) { MIPSInfo info = MIPSGetInfo(op); if ((info & IS_VFPU) == 0) { if ((info & IN_RS) != 0 && MIPS_GET_RS(op) == reg) { @@ -64,7 +64,7 @@ namespace MIPSAnalyst return false; } - bool IsDelaySlotNiceReg(u32 branchOp, u32 op, int reg1, int reg2) { + bool IsDelaySlotNiceReg(MIPSOpcode branchOp, MIPSOpcode op, int reg1, int reg2) { // $0 is never an out reg, it's always 0. if (reg1 != 0 && GetOutGPReg(op) == reg1) { return false; @@ -76,16 +76,16 @@ namespace MIPSAnalyst return true; } - bool IsDelaySlotNiceVFPU(u32 branchOp, u32 op) { + bool IsDelaySlotNiceVFPU(MIPSOpcode branchOp, MIPSOpcode op) { // TODO: There may be IS_VFPU cases which are safe... return (MIPSGetInfo(op) & IS_VFPU) == 0; } - bool IsDelaySlotNiceFPU(u32 branchOp, u32 op) { + bool IsDelaySlotNiceFPU(MIPSOpcode branchOp, MIPSOpcode op) { return (MIPSGetInfo(op) & OUT_FPUFLAG) == 0; } - bool IsSyscall(u32 op) { + bool IsSyscall(MIPSOpcode op) { // Syscalls look like this: 0000 00-- ---- ---- ---- --00 1100 return (op >> 26) == 0 && (op & 0x3f) == 12; } @@ -103,7 +103,7 @@ namespace MIPSAnalyst } for (u32 addr = address, endAddr = address + MAX_ANALYZE; addr <= endAddr; addr += 4) { - u32 op = Memory::Read_Instruction(addr); + MIPSOpcode op = Memory::Read_Instruction(addr); MIPSInfo info = MIPSGetInfo(op); int rs = MIPS_GET_RS(op); @@ -188,7 +188,7 @@ namespace MIPSAnalyst { while (true) { - u32 op = Memory::Read_Instruction(addr); + MIPSOpcode op = Memory::Read_Instruction(addr); MIPSInfo info = MIPSGetInfo(op); if ((info & IN_RS) && (MIPS_GET_RS(op) == reg)) @@ -219,7 +219,7 @@ namespace MIPSAnalyst for (u32 addr = f.start; addr <= f.end; addr += 4) { u32 validbits = 0xFFFFFFFF; - u32 instr = Memory::Read_Instruction(addr); + MIPSOpcode instr = Memory::Read_Instruction(addr); MIPSInfo flags = MIPSGetInfo(instr); if (flags & IN_IMM16) validbits&=~0xFFFF; @@ -251,7 +251,7 @@ namespace MIPSAnalyst continue; } - u32 op = Memory::Read_Instruction(addr); + MIPSOpcode op = Memory::Read_Instruction(addr); u32 target = GetBranchTargetNoRA(addr); if (target != INVALIDTARGET) { @@ -400,7 +400,7 @@ namespace MIPSAnalyst LOG(CPU,"Precompiled %i straight leaf functions",count);*/ } - std::vector GetInputRegs(u32 op) + std::vector GetInputRegs(MIPSOpcode op) { std::vector vec; MIPSInfo info = MIPSGetInfo(op); @@ -411,7 +411,7 @@ namespace MIPSAnalyst } return vec; } - std::vector GetOutputRegs(u32 op) + std::vector GetOutputRegs(MIPSOpcode op) { std::vector vec; MIPSInfo info = MIPSGetInfo(op); @@ -437,7 +437,7 @@ namespace MIPSAnalyst info.opcodeAddress = address; info.encodedOpcode = Memory::Read_Instruction(address); - u32 op = info.encodedOpcode; + MIPSOpcode op = info.encodedOpcode; MIPSInfo opInfo = MIPSGetInfo(op); info.isLikelyBranch = (opInfo & LIKELY) != 0; diff --git a/Core/MIPS/MIPSAnalyst.h b/Core/MIPS/MIPSAnalyst.h index 7dcdbd4721..2047212032 100644 --- a/Core/MIPS/MIPSAnalyst.h +++ b/Core/MIPS/MIPSAnalyst.h @@ -17,7 +17,8 @@ #pragma once -#include "../../Globals.h" +#include "Globals.h" +#include "Core/MIPS/MIPS.h" class DebugInterface; @@ -75,16 +76,15 @@ namespace MIPSAnalyst void ScanForFunctions(u32 startAddr, u32 endAddr); void CompileLeafs(); - std::vector GetInputRegs(u32 op); - std::vector GetOutputRegs(u32 op); + std::vector GetInputRegs(MIPSOpcode op); + std::vector GetOutputRegs(MIPSOpcode op); - int GetOutGPReg(u32 op); - bool ReadsFromGPReg(u32 op, u32 reg); - bool IsDelaySlotNice(u32 branch, u32 delayslot); - bool IsDelaySlotNiceReg(u32 branchOp, u32 op, int reg1, int reg2 = 0); - bool IsDelaySlotNiceVFPU(u32 branchOp, u32 op); - bool IsDelaySlotNiceFPU(u32 branchOp, u32 op); - bool IsSyscall(u32 op); + int GetOutGPReg(MIPSOpcode op); + bool ReadsFromGPReg(MIPSOpcode op, u32 reg); + bool IsDelaySlotNiceReg(MIPSOpcode branchOp, MIPSOpcode op, int reg1, int reg2 = 0); + bool IsDelaySlotNiceVFPU(MIPSOpcode branchOp, MIPSOpcode op); + bool IsDelaySlotNiceFPU(MIPSOpcode branchOp, MIPSOpcode op); + bool IsSyscall(MIPSOpcode op); void Shutdown(); @@ -92,7 +92,7 @@ namespace MIPSAnalyst { DebugInterface* cpu; u32 opcodeAddress; - u32 encodedOpcode; + MIPSOpcode encodedOpcode; // shared between branches and conditional moves bool isConditional; diff --git a/Core/MIPS/MIPSCodeUtils.cpp b/Core/MIPS/MIPSCodeUtils.cpp index b5f22005ad..49a42e4fa4 100644 --- a/Core/MIPS/MIPSCodeUtils.cpp +++ b/Core/MIPS/MIPSCodeUtils.cpp @@ -31,8 +31,8 @@ namespace MIPSCodeUtils u32 GetJumpTarget(u32 addr) { - u32 op = Memory::Read_Instruction(addr); - if (op) + MIPSOpcode op = Memory::Read_Instruction(addr); + if (op != 0) { MIPSInfo info = MIPSGetInfo(op); if ((info & IS_JUMP) && (info & IN_IMM26)) @@ -49,8 +49,8 @@ namespace MIPSCodeUtils u32 GetBranchTarget(u32 addr) { - u32 op = Memory::Read_Instruction(addr); - if (op) + MIPSOpcode op = Memory::Read_Instruction(addr); + if (op != 0) { MIPSInfo info = MIPSGetInfo(op); if (info & IS_CONDBRANCH) @@ -66,8 +66,8 @@ namespace MIPSCodeUtils u32 GetBranchTargetNoRA(u32 addr) { - u32 op = Memory::Read_Instruction(addr); - if (op) + MIPSOpcode op = Memory::Read_Instruction(addr); + if (op != 0) { MIPSInfo info = MIPSGetInfo(op); if ((info & IS_CONDBRANCH) && !(info & OUT_RA)) @@ -83,8 +83,8 @@ namespace MIPSCodeUtils u32 GetSureBranchTarget(u32 addr) { - u32 op = Memory::Read_Instruction(addr); - if (op) + MIPSOpcode op = Memory::Read_Instruction(addr); + if (op != 0) { MIPSInfo info = MIPSGetInfo(op); if (info & IS_CONDBRANCH) @@ -133,7 +133,7 @@ namespace MIPSCodeUtils return INVALIDTARGET; } - bool IsVFPUBranch(u32 op) { + bool IsVFPUBranch(MIPSOpcode op) { return (MIPSGetInfo(op) & (IS_VFPU | IS_CONDBRANCH)) == (IS_VFPU | IS_CONDBRANCH); } } diff --git a/Core/MIPS/MIPSCodeUtils.h b/Core/MIPS/MIPSCodeUtils.h index 018b9f0071..1ddf184f56 100644 --- a/Core/MIPS/MIPSCodeUtils.h +++ b/Core/MIPS/MIPSCodeUtils.h @@ -57,5 +57,5 @@ namespace MIPSCodeUtils u32 GetBranchTargetNoRA(u32 addr); u32 GetJumpTarget(u32 addr); u32 GetSureBranchTarget(u32 addr); - bool IsVFPUBranch(u32 op); + bool IsVFPUBranch(MIPSOpcode op); } diff --git a/Core/MIPS/MIPSDis.cpp b/Core/MIPS/MIPSDis.cpp index 7aa2953b7b..d06eaae6dc 100644 --- a/Core/MIPS/MIPSDis.cpp +++ b/Core/MIPS/MIPSDis.cpp @@ -56,12 +56,12 @@ namespace MIPSDis return temp; } - void Dis_Generic(u32 op, char *out) + void Dis_Generic(MIPSOpcode op, char *out) { sprintf(out, "%s\t --- unknown ---", MIPSGetName(op)); } - void Dis_mxc1(u32 op, char *out) + void Dis_mxc1(MIPSOpcode op, char *out) { int fs = _FS; int rt = _RT; @@ -69,7 +69,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %s",name,RN(rt),FN(fs)); } - void Dis_FPU3op(u32 op, char *out) + void Dis_FPU3op(MIPSOpcode op, char *out) { int ft = _FT; int fs = _FS; @@ -78,7 +78,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %s, %s",name,FN(fd),FN(fs),FN(ft)); } - void Dis_FPU2op(u32 op, char *out) + void Dis_FPU2op(MIPSOpcode op, char *out) { int fs = _FS; int fd = _FD;; @@ -86,7 +86,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %s",name,FN(fd),FN(fs)); } - void Dis_FPULS(u32 op, char *out) + void Dis_FPULS(MIPSOpcode op, char *out) { int offset = (signed short)(op&0xFFFF); int ft = _FT; @@ -94,7 +94,7 @@ namespace MIPSDis const char *name = MIPSGetName(op); sprintf(out, "%s\t%s, %s(%s)",name,FN(ft),SignedHex(offset),RN(rs)); } - void Dis_FPUComp(u32 op, char *out) + void Dis_FPUComp(MIPSOpcode op, char *out) { int fs = _FS; int ft = _FT; @@ -102,7 +102,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %s",name,FN(fs),FN(ft)); } - void Dis_FPUBranch(u32 op, char *out) + void Dis_FPUBranch(MIPSOpcode op, char *out) { u32 off = disPC; int imm = (signed short)(op&0xFFFF)<<2; @@ -111,7 +111,7 @@ namespace MIPSDis sprintf(out, "%s\t->$%08x",name,off); } - void Dis_RelBranch(u32 op, char *out) + void Dis_RelBranch(MIPSOpcode op, char *out) { u32 off = disPC; int imm = (signed short)(op&0xFFFF)<<2; @@ -122,7 +122,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, ->$%08x",name,RN(rs),off); } - void Dis_Syscall(u32 op, char *out) + void Dis_Syscall(MIPSOpcode op, char *out) { u32 callno = (op>>6) & 0xFFFFF; //20 bits int funcnum = callno & 0xFFF; @@ -130,20 +130,20 @@ namespace MIPSDis sprintf(out, "syscall\t %s",/*PSPHLE::GetModuleName(modulenum),*/GetFuncName(modulenum, funcnum)); } - void Dis_ToHiloTransfer(u32 op, char *out) + void Dis_ToHiloTransfer(MIPSOpcode op, char *out) { int rs = _RS; const char *name = MIPSGetName(op); sprintf(out, "%s\t%s",name,RN(rs)); } - void Dis_FromHiloTransfer(u32 op, char *out) + void Dis_FromHiloTransfer(MIPSOpcode op, char *out) { int rd = _RD; const char *name = MIPSGetName(op); sprintf(out, "%s\t%s",name,RN(rd)); } - void Dis_RelBranch2(u32 op, char *out) + void Dis_RelBranch2(MIPSOpcode op, char *out) { u32 off = disPC; int imm = (signed short)(op&0xFFFF)<<2; @@ -161,7 +161,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %s, ->$%08x",name,RN(rt),RN(rs),off); } - void Dis_IType(u32 op, char *out) + void Dis_IType(MIPSOpcode op, char *out) { s32 simm = (s32)(s16)(op & 0xFFFF); u32 uimm = (u32)(u16)(op & 0xFFFF); @@ -185,7 +185,7 @@ namespace MIPSDis break; } } - void Dis_ori(u32 op, char *out) + void Dis_ori(MIPSOpcode op, char *out) { s32 simm = (s32)(s16)(op & 0xFFFF); u32 uimm = (u32)(u16)(op & 0xFFFF); @@ -198,7 +198,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %s, 0x%X",name,RN(rt),RN(rs),uimm); } - void Dis_IType1(u32 op, char *out) + void Dis_IType1(MIPSOpcode op, char *out) { u32 uimm = (u32)(u16)(op & 0xFFFF); int rt = _RT; @@ -206,7 +206,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, 0x%X",name,RN(rt),uimm); } - void Dis_addi(u32 op, char *out) + void Dis_addi(MIPSOpcode op, char *out) { int imm = (signed short)(op&0xFFFF); int rt = _RT; @@ -217,7 +217,7 @@ namespace MIPSDis Dis_IType(op,out); } - void Dis_ITypeMem(u32 op, char *out) + void Dis_ITypeMem(MIPSOpcode op, char *out) { int imm = (signed short)(op&0xFFFF); int rt = _RT; @@ -226,7 +226,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %s(%s)",name,RN(rt),SignedHex(imm),RN(rs)); } - void Dis_RType2(u32 op, char *out) + void Dis_RType2(MIPSOpcode op, char *out) { int rs = _RS; int rd = _RD; @@ -234,7 +234,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %s",name,RN(rd),RN(rs)); } - void Dis_RType3(u32 op, char *out) + void Dis_RType3(MIPSOpcode op, char *out) { int rt = _RT; int rs = _RS; @@ -243,7 +243,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %s, %s",name,RN(rd),RN(rs),RN(rt)); } - void Dis_addu(u32 op, char *out) + void Dis_addu(MIPSOpcode op, char *out) { int rt = _RT; int rs = _RS; @@ -259,7 +259,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %s, %s",name,RN(rd),RN(rs),RN(rt)); } - void Dis_ShiftType(u32 op, char *out) + void Dis_ShiftType(MIPSOpcode op, char *out) { int rt = _RT; int rs = _RS; @@ -273,7 +273,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %s, 0x%X",name,RN(rd),RN(rt),sa); } - void Dis_VarShiftType(u32 op, char *out) + void Dis_VarShiftType(MIPSOpcode op, char *out) { int rt = _RT; int rs = _RS; @@ -283,7 +283,7 @@ namespace MIPSDis } - void Dis_MulDivType(u32 op, char *out) + void Dis_MulDivType(MIPSOpcode op, char *out) { int rt = _RT; int rs = _RS; @@ -292,7 +292,7 @@ namespace MIPSDis } - void Dis_Special3(u32 op, char *out) + void Dis_Special3(MIPSOpcode op, char *out) { int rs = _RS; int Rt = _RT; @@ -316,14 +316,14 @@ namespace MIPSDis } } - void Dis_JumpType(u32 op, char *out) + void Dis_JumpType(MIPSOpcode op, char *out) { u32 off = ((op & 0x03FFFFFF) << 2); u32 addr = (disPC & 0xF0000000) | off; const char *name = MIPSGetName(op); sprintf(out, "%s\t->$%08x",name,addr); } - void Dis_JumpRegType(u32 op, char *out) + void Dis_JumpRegType(MIPSOpcode op, char *out) { int rs = (op>>21)&0x1f; const char *name = MIPSGetName(op); @@ -331,7 +331,7 @@ namespace MIPSDis } - void Dis_Allegrex(u32 op, char *out) + void Dis_Allegrex(MIPSOpcode op, char *out) { int rt = _RT; int rd = _RD; @@ -339,7 +339,7 @@ namespace MIPSDis sprintf(out,"%s\t%s,%s",name,RN(rd),RN(rt)); } - void Dis_Allegrex2(u32 op, char *out) + void Dis_Allegrex2(MIPSOpcode op, char *out) { int rt = _RT; int rd = _RD; @@ -347,7 +347,7 @@ namespace MIPSDis sprintf(out,"%s\t%s,%s",name,RN(rd),RN(rt)); } - void Dis_Emuhack(u32 op, char *out) + void Dis_Emuhack(MIPSOpcode op, char *out) { //const char *name = MIPSGetName(op); //sprintf(out,"%s\t-",name); diff --git a/Core/MIPS/MIPSDis.h b/Core/MIPS/MIPSDis.h index e07351eec6..5a706f5919 100644 --- a/Core/MIPS/MIPSDis.h +++ b/Core/MIPS/MIPSDis.h @@ -17,45 +17,46 @@ #pragma once -#include "../../Globals.h" +#include "Globals.h" +#include "Core/MIPS/MIPS.h" extern u32 disPC; namespace MIPSDis { - void Dis_Unknown(u32 op, char *out); - void Dis_Unimpl(u32 op, char *out); - void Dis_Syscall(u32 op, char *out); + void Dis_Unknown(MIPSOpcode op, char *out); + void Dis_Unimpl(MIPSOpcode op, char *out); + void Dis_Syscall(MIPSOpcode op, char *out); - void Dis_mxc1(u32 op, char *out); - void Dis_addi(u32 op, char *out); - void Dis_addu(u32 op, char *out); - void Dis_RelBranch2(u32 op, char *out); - void Dis_RelBranch(u32 op, char *out); - void Dis_Generic(u32 op, char *out); - void Dis_IType(u32 op, char *out); - void Dis_IType1(u32 op, char *out); - void Dis_ITypeMem(u32 op, char *out); - void Dis_RType2(u32 op, char *out); - void Dis_RType3(u32 op, char *out); - void Dis_MulDivType(u32 op, char *out); - void Dis_ShiftType(u32 op, char *out); - void Dis_VarShiftType(u32 op, char *out); - void Dis_FPU3op(u32 op, char *out); - void Dis_FPU2op(u32 op, char *out); - void Dis_FPULS(u32 op, char *out); - void Dis_FPUComp(u32 op, char *out); - void Dis_FPUBranch(u32 op, char *out); - void Dis_ori(u32 op, char *out); - void Dis_Special3(u32 op, char *out); + void Dis_mxc1(MIPSOpcode op, char *out); + void Dis_addi(MIPSOpcode op, char *out); + void Dis_addu(MIPSOpcode op, char *out); + void Dis_RelBranch2(MIPSOpcode op, char *out); + void Dis_RelBranch(MIPSOpcode op, char *out); + void Dis_Generic(MIPSOpcode op, char *out); + void Dis_IType(MIPSOpcode op, char *out); + void Dis_IType1(MIPSOpcode op, char *out); + void Dis_ITypeMem(MIPSOpcode op, char *out); + void Dis_RType2(MIPSOpcode op, char *out); + void Dis_RType3(MIPSOpcode op, char *out); + void Dis_MulDivType(MIPSOpcode op, char *out); + void Dis_ShiftType(MIPSOpcode op, char *out); + void Dis_VarShiftType(MIPSOpcode op, char *out); + void Dis_FPU3op(MIPSOpcode op, char *out); + void Dis_FPU2op(MIPSOpcode op, char *out); + void Dis_FPULS(MIPSOpcode op, char *out); + void Dis_FPUComp(MIPSOpcode op, char *out); + void Dis_FPUBranch(MIPSOpcode op, char *out); + void Dis_ori(MIPSOpcode op, char *out); + void Dis_Special3(MIPSOpcode op, char *out); - void Dis_ToHiloTransfer(u32 op, char *out); - void Dis_FromHiloTransfer(u32 op, char *out); - void Dis_JumpType(u32 op, char *out); - void Dis_JumpRegType(u32 op, char *out); + void Dis_ToHiloTransfer(MIPSOpcode op, char *out); + void Dis_FromHiloTransfer(MIPSOpcode op, char *out); + void Dis_JumpType(MIPSOpcode op, char *out); + void Dis_JumpRegType(MIPSOpcode op, char *out); - void Dis_Allegrex(u32 op, char *out); - void Dis_Allegrex2(u32 op, char *out); + void Dis_Allegrex(MIPSOpcode op, char *out); + void Dis_Allegrex2(MIPSOpcode op, char *out); - void Dis_Emuhack(u32 op, char *out); + void Dis_Emuhack(MIPSOpcode op, char *out); } diff --git a/Core/MIPS/MIPSDisVFPU.cpp b/Core/MIPS/MIPSDisVFPU.cpp index 0d76e0d644..e76f7a49e6 100644 --- a/Core/MIPS/MIPSDisVFPU.cpp +++ b/Core/MIPS/MIPSDisVFPU.cpp @@ -82,7 +82,7 @@ inline const char *MN(int v, MatrixSize size) return GetMatrixNotation(v, size); } -inline const char *VSuff(u32 op) +inline const char *VSuff(MIPSOpcode op) { int a = (op>>7)&1; int b = (op>>15)&1; @@ -99,7 +99,7 @@ inline const char *VSuff(u32 op) namespace MIPSDis { - void Dis_SV(u32 op, char *out) + void Dis_SV(MIPSOpcode op, char *out) { int offset = (signed short)(op&0xFFFC); int vt = ((op>>16)&0x1f)|((op&3)<<5); @@ -108,7 +108,7 @@ namespace MIPSDis sprintf(out, "%s\t%s, %d(%s)",name,VN(vt, V_Single),offset,RN(rs)); } - void Dis_SVQ(u32 op, char *out) + void Dis_SVQ(MIPSOpcode op, char *out) { int offset = (signed short)(op&0xFFFC); int vt = (((op>>16)&0x1f))|((op&1)<<5); @@ -119,7 +119,7 @@ namespace MIPSDis strcat(out, ", wb"); } - void Dis_SVLRQ(u32 op, char *out) + void Dis_SVLRQ(MIPSOpcode op, char *out) { int offset = (signed short)(op&0xFFFC); int vt = (((op>>16)&0x1f))|((op&1)<<5); @@ -129,7 +129,7 @@ namespace MIPSDis sprintf(out, "%s%s.q\t%s, %d(%s)",name,lr?"r":"l",VN(vt,V_Quad),offset,RN(rs)); } - void Dis_Mftv(u32 op, char *out) + void Dis_Mftv(MIPSOpcode op, char *out) { int vr = op & 0xFF; int rt = _RT; @@ -137,7 +137,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s",name,vr>127?"c":"", RN(rt), VN(vr, V_Single)); } - void Dis_VPFXST(u32 op, char *out) + void Dis_VPFXST(MIPSOpcode op, char *out) { int data = op & 0xFFFFF; const char *name = MIPSGetName(op); @@ -170,7 +170,7 @@ namespace MIPSDis } } - void Dis_VPFXD(u32 op, char *out) + void Dis_VPFXD(MIPSOpcode op, char *out) { int data = op & 0xFFFFF; const char *name = MIPSGetName(op); @@ -189,7 +189,7 @@ namespace MIPSDis } - void Dis_Viim(u32 op, char *out) + void Dis_Viim(MIPSOpcode op, char *out) { int vt = _VT; int imm = op&0xFFFF; @@ -205,7 +205,7 @@ namespace MIPSDis sprintf(out, "ARGH"); } - void Dis_Vcst(u32 op, char *out) + void Dis_Vcst(MIPSOpcode op, char *out) { int conNum = (op>>16) & 0x1f; int vd = _VD; @@ -239,14 +239,14 @@ namespace MIPSDis } - void Dis_MatrixSet1(u32 op, char *out) + void Dis_MatrixSet1(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vd = _VD; MatrixSize sz = GetMtxSize(op); sprintf(out, "%s%s\t%s",name,VSuff(op),MN(vd, sz)); } - void Dis_MatrixSet2(u32 op, char *out) + void Dis_MatrixSet2(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vd = _VD; @@ -254,7 +254,7 @@ namespace MIPSDis MatrixSize sz = GetMtxSize(op); sprintf(out, "%s%s\t%s, %s",name,VSuff(op),MN(vd, sz),MN(vs,sz)); } - void Dis_MatrixSet3(u32 op, char *out) + void Dis_MatrixSet3(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vd = _VD; @@ -264,7 +264,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s, %s",name,VSuff(op),MN(vd, sz),MN(vs,sz),MN(vt,sz)); } - void Dis_MatrixMult(u32 op, char *out) + void Dis_MatrixMult(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vd = _VD; @@ -274,7 +274,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s, %s",name,VSuff(op),MN(vd, sz),MN(Xpose(vs),sz),MN(vt,sz)); } - void Dis_VectorDot(u32 op, char *out) + void Dis_VectorDot(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vd = _VD; @@ -284,7 +284,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s, %s", name, VSuff(op), VN(vd, V_Single), VN(vs,sz), VN(vt, sz)); } - void Dis_Vtfm(u32 op, char *out) + void Dis_Vtfm(MIPSOpcode op, char *out) { int vd = _VD; int vs = _VS; @@ -309,12 +309,12 @@ namespace MIPSDis } } - void Dis_Vflush(u32 op, char *out) + void Dis_Vflush(MIPSOpcode op, char *out) { sprintf(out,"vflush"); } - void Dis_Vcrs(u32 op, char *out) + void Dis_Vcrs(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vt = _VT; @@ -330,7 +330,7 @@ namespace MIPSDis } - void Dis_Vcmp(u32 op, char *out) + void Dis_Vcmp(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vt = _VT; @@ -341,7 +341,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s, %s", name, VSuff(op), condNames[cond], VN(vs, sz), VN(vt,sz)); } - void Dis_Vcmov(u32 op, char *out) + void Dis_Vcmov(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); VectorSize sz = GetVecSize(op); @@ -361,7 +361,7 @@ namespace MIPSDis } - void Dis_Vfad(u32 op, char *out) + void Dis_Vfad(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vd = _VD; @@ -370,7 +370,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s", name, VSuff(op), VN(vd, V_Single), VN(vs,sz)); } - void Dis_VScl(u32 op, char *out) + void Dis_VScl(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vd = _VD; @@ -380,14 +380,14 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s, %s", name, VSuff(op), VN(vd, sz), VN(vs,sz), VN(vt, V_Single)); } - void Dis_VectorSet1(u32 op, char *out) + void Dis_VectorSet1(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vd = _VD; VectorSize sz = GetVecSize(op); sprintf(out, "%s%s\t%s",name,VSuff(op),VN(vd, sz)); } - void Dis_VectorSet2(u32 op, char *out) + void Dis_VectorSet2(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vd = _VD; @@ -395,7 +395,7 @@ namespace MIPSDis VectorSize sz = GetVecSize(op); sprintf(out, "%s%s\t%s, %s",name,VSuff(op),VN(vd, sz),VN(vs, sz)); } - void Dis_VectorSet3(u32 op, char *out) + void Dis_VectorSet3(MIPSOpcode op, char *out) { const char *name = MIPSGetName(op); int vd = _VD; @@ -405,7 +405,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s, %s", name, VSuff(op), VN(vd, sz), VN(vs,sz), VN(vt, sz)); } - void Dis_VRot(u32 op, char *out) + void Dis_VRot(MIPSOpcode op, char *out) { int vd = _VD; int vs = _VS; @@ -439,7 +439,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s, %s",name,VSuff(op),VN(vd, sz),VN(vs, V_Single),temp); } - void Dis_CrossQuat(u32 op, char *out) + void Dis_CrossQuat(MIPSOpcode op, char *out) { VectorSize sz = GetVecSize(op); const char *name; @@ -464,7 +464,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s, %s", name, VSuff(op), VN(vd, sz), VN(vs,sz), VN(vt, sz)); } - void Dis_Vbfy(u32 op, char *out) + void Dis_Vbfy(MIPSOpcode op, char *out) { VectorSize sz = GetVecSize(op); int vd = _VD; @@ -473,7 +473,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s",name,VSuff(op),VN(vd, sz),VN(vs, sz)); } - void Dis_Vf2i(u32 op, char *out) + void Dis_Vf2i(MIPSOpcode op, char *out) { VectorSize sz = GetVecSize(op); int vd = _VD; @@ -483,7 +483,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s, %i",name,VSuff(op),VN(vd, sz),VN(vs, sz),imm); } - void Dis_Vs2i(u32 op, char *out) + void Dis_Vs2i(MIPSOpcode op, char *out) { VectorSize sz = GetVecSize(op); int vd = _VD; @@ -492,7 +492,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s",name,VSuff(op),VN(vd, sz),VN(vs, sz)); } - void Dis_Vi2x(u32 op, char *out) + void Dis_Vi2x(MIPSOpcode op, char *out) { VectorSize sz = GetVecSize(op); VectorSize dsz = GetHalfVectorSize(sz); @@ -505,7 +505,7 @@ namespace MIPSDis sprintf(out, "%s%s\t%s, %s",name,VSuff(op),VN(vd, dsz),VN(vs, sz)); } - void Dis_VBranch(u32 op, char *out) + void Dis_VBranch(MIPSOpcode op, char *out) { u32 off = disPC; int imm = (signed short)(op&0xFFFF)<<2; diff --git a/Core/MIPS/MIPSDisVFPU.h b/Core/MIPS/MIPSDisVFPU.h index ebc21aa07f..dbb1aef3f0 100644 --- a/Core/MIPS/MIPSDisVFPU.h +++ b/Core/MIPS/MIPSDisVFPU.h @@ -23,38 +23,38 @@ extern u32 disPC; namespace MIPSDis { - void Dis_Mftv(u32 op, char *out); + void Dis_Mftv(MIPSOpcode op, char *out); - void Dis_SV(u32 op, char *out); - void Dis_SVQ(u32 op, char *out); - void Dis_SVLRQ(u32 op, char *out); + void Dis_SV(MIPSOpcode op, char *out); + void Dis_SVQ(MIPSOpcode op, char *out); + void Dis_SVLRQ(MIPSOpcode op, char *out); - void Dis_MatrixSet1(u32 op, char *out); - void Dis_MatrixSet2(u32 op, char *out); - void Dis_MatrixSet3(u32 op, char *out); - void Dis_MatrixMult(u32 op, char *out); + void Dis_MatrixSet1(MIPSOpcode op, char *out); + void Dis_MatrixSet2(MIPSOpcode op, char *out); + void Dis_MatrixSet3(MIPSOpcode op, char *out); + void Dis_MatrixMult(MIPSOpcode op, char *out); - void Dis_VectorDot(u32 op, char *out); - void Dis_Vfad(u32 op, char *out); - void Dis_VectorSet1(u32 op, char *out); - void Dis_VectorSet2(u32 op, char *out); - void Dis_VectorSet3(u32 op, char *out); - void Dis_VRot(u32 op, char *out); - void Dis_VScl(u32 op, char *out); + void Dis_VectorDot(MIPSOpcode op, char *out); + void Dis_Vfad(MIPSOpcode op, char *out); + void Dis_VectorSet1(MIPSOpcode op, char *out); + void Dis_VectorSet2(MIPSOpcode op, char *out); + void Dis_VectorSet3(MIPSOpcode op, char *out); + void Dis_VRot(MIPSOpcode op, char *out); + void Dis_VScl(MIPSOpcode op, char *out); - void Dis_VPFXST(u32 op, char *out); - void Dis_VPFXD(u32 op, char *out); - void Dis_Vcrs(u32 op, char *out); - void Dis_Viim(u32 op, char *out); - void Dis_Vcst(u32 op, char *out); - void Dis_CrossQuat(u32 op, char *out); - void Dis_Vtfm(u32 op, char *out); - void Dis_Vcmp(u32 op, char *out); - void Dis_Vcmov(u32 op, char *out); - void Dis_Vflush(u32 op, char *out); - void Dis_Vbfy(u32 op, char *out); - void Dis_Vf2i(u32 op, char *out); - void Dis_Vi2x(u32 op, char *out); - void Dis_Vs2i(u32 op, char *out); - void Dis_VBranch(u32 op, char *out); + void Dis_VPFXST(MIPSOpcode op, char *out); + void Dis_VPFXD(MIPSOpcode op, char *out); + void Dis_Vcrs(MIPSOpcode op, char *out); + void Dis_Viim(MIPSOpcode op, char *out); + void Dis_Vcst(MIPSOpcode op, char *out); + void Dis_CrossQuat(MIPSOpcode op, char *out); + void Dis_Vtfm(MIPSOpcode op, char *out); + void Dis_Vcmp(MIPSOpcode op, char *out); + void Dis_Vcmov(MIPSOpcode op, char *out); + void Dis_Vflush(MIPSOpcode op, char *out); + void Dis_Vbfy(MIPSOpcode op, char *out); + void Dis_Vf2i(MIPSOpcode op, char *out); + void Dis_Vi2x(MIPSOpcode op, char *out); + void Dis_Vs2i(MIPSOpcode op, char *out); + void Dis_VBranch(MIPSOpcode op, char *out); } diff --git a/Core/MIPS/MIPSInt.cpp b/Core/MIPS/MIPSInt.cpp index 119f614033..1ac735f444 100644 --- a/Core/MIPS/MIPSInt.cpp +++ b/Core/MIPS/MIPSInt.cpp @@ -66,9 +66,9 @@ static inline void SkipLikely() int MIPS_SingleStep() { #if defined(ARM) - u32 op = Memory::ReadUnchecked_U32(mipsr4k.pc); + MIPSOpcode op = MIPSOpcode(Memory::ReadUnchecked_U32(mipsr4k.pc)); #else - u32 op = Memory::Read_Opcode_JIT(mipsr4k.pc); + MIPSOpcode op = Memory::Read_Opcode_JIT(mipsr4k.pc); #endif /* // Choke on VFPU @@ -117,7 +117,7 @@ void MIPS_ClearDelaySlot() namespace MIPSInt { - void Int_Cache(u32 op) + void Int_Cache(MIPSOpcode op) { int imm = (s16)(op & 0xFFFF); int rs = _RS; @@ -145,7 +145,7 @@ namespace MIPSInt PC += 4; } - void Int_Syscall(u32 op) + void Int_Syscall(MIPSOpcode op) { // Need to pre-move PC, as CallSyscall may result in a rescheduling! // To do this neater, we'll need a little generated kernel loop that syscall can jump to and then RFI from @@ -162,13 +162,13 @@ namespace MIPSInt CallSyscall(op); } - void Int_Sync(u32 op) + void Int_Sync(MIPSOpcode op) { //DEBUG_LOG(CPU, "sync"); PC += 4; } - void Int_Break(u32 op) + void Int_Break(MIPSOpcode op) { Reporting::ReportMessage("BREAK instruction hit"); ERROR_LOG(CPU, "BREAK!"); @@ -177,7 +177,7 @@ namespace MIPSInt PC += 4; } - void Int_RelBranch(u32 op) + void Int_RelBranch(MIPSOpcode op) { int imm = (signed short)(op&0xFFFF)<<2; int rs = _RS; @@ -202,7 +202,7 @@ namespace MIPSInt } } - void Int_RelBranchRI(u32 op) + void Int_RelBranchRI(MIPSOpcode op) { int imm = (signed short)(op&0xFFFF)<<2; int rs = _RS; @@ -225,7 +225,7 @@ namespace MIPSInt } - void Int_VBranch(u32 op) + void Int_VBranch(MIPSOpcode op) { int imm = (signed short)(op&0xFFFF)<<2; u32 addr = PC + imm + 4; @@ -243,7 +243,7 @@ namespace MIPSInt } } - void Int_FPUBranch(u32 op) + void Int_FPUBranch(MIPSOpcode op) { int imm = (signed short)(op&0xFFFF)<<2; u32 addr = PC + imm + 4; @@ -259,7 +259,7 @@ namespace MIPSInt } } - void Int_JumpType(u32 op) + void Int_JumpType(MIPSOpcode op) { if (mipsr4k.inDelaySlot) _dbg_assert_msg_(CPU,0,"Jump in delay slot :("); @@ -280,7 +280,7 @@ namespace MIPSInt } } - void Int_JumpRegType(u32 op) + void Int_JumpRegType(MIPSOpcode op) { if (mipsr4k.inDelaySlot) { @@ -306,7 +306,7 @@ namespace MIPSInt } } - void Int_IType(u32 op) + void Int_IType(MIPSOpcode op) { s32 simm = (s32)(s16)(op & 0xFFFF); u32 uimm = (u32)(u16)(op & 0xFFFF); @@ -338,7 +338,7 @@ namespace MIPSInt PC += 4; } - void Int_StoreSync(u32 op) + void Int_StoreSync(MIPSOpcode op) { int imm = (signed short)(op&0xFFFF); int rt = _RT; @@ -371,7 +371,7 @@ namespace MIPSInt } - void Int_RType3(u32 op) + void Int_RType3(MIPSOpcode op) { int rt = _RT; int rs = _RS; @@ -419,7 +419,7 @@ namespace MIPSInt } - void Int_ITypeMem(u32 op) + void Int_ITypeMem(MIPSOpcode op) { int imm = (signed short)(op&0xFFFF); int rt = _RT; @@ -489,7 +489,7 @@ namespace MIPSInt PC += 4; } - void Int_FPULS(u32 op) + void Int_FPULS(MIPSOpcode op) { s32 offset = (s16)(op&0xFFFF); int ft = _FT; @@ -507,7 +507,7 @@ namespace MIPSInt PC += 4; } - void Int_mxc1(u32 op) + void Int_mxc1(MIPSOpcode op) { int fs = _FS; int rt = _RT; @@ -526,7 +526,7 @@ namespace MIPSInt PC += 4; } - void Int_RType2(u32 op) + void Int_RType2(MIPSOpcode op) { int rs = _RS; int rd = _RD; @@ -571,7 +571,7 @@ namespace MIPSInt PC += 4; } - void Int_MulDivType(u32 op) + void Int_MulDivType(MIPSOpcode op) { int rt = _RT; int rs = _RS; @@ -674,7 +674,7 @@ namespace MIPSInt } - void Int_ShiftType(u32 op) + void Int_ShiftType(MIPSOpcode op) { int rt = _RT; int rs = _RS; @@ -728,7 +728,7 @@ namespace MIPSInt PC += 4; } - void Int_Allegrex(u32 op) + void Int_Allegrex(MIPSOpcode op) { int rt = _RT; int rd = _RD; @@ -771,7 +771,7 @@ namespace MIPSInt PC += 4; } - void Int_Allegrex2(u32 op) + void Int_Allegrex2(MIPSOpcode op) { int rt = _RT; int rd = _RD; @@ -798,7 +798,7 @@ namespace MIPSInt PC += 4; } - void Int_Special3(u32 op) + void Int_Special3(MIPSOpcode op) { int rs = _RS; int rt = _RT; @@ -832,7 +832,7 @@ namespace MIPSInt PC += 4; } - void Int_FPU2op(u32 op) + void Int_FPU2op(MIPSOpcode op) { int fs = _FS; int fd = _FD; @@ -865,7 +865,7 @@ namespace MIPSInt PC += 4; } - void Int_FPUComp(u32 op) + void Int_FPUComp(MIPSOpcode op) { int fs = _FS; int ft = _FT; @@ -921,7 +921,7 @@ namespace MIPSInt PC += 4; } - void Int_FPU3op(u32 op) + void Int_FPU3op(MIPSOpcode op) { int ft = _FT; int fs = _FS; @@ -940,7 +940,7 @@ namespace MIPSInt PC += 4; } - void Int_Interrupt(u32 op) + void Int_Interrupt(MIPSOpcode op) { static int reported = 0; switch (op & 1) @@ -957,7 +957,7 @@ namespace MIPSInt } - void Int_Emuhack(u32 op) + void Int_Emuhack(MIPSOpcode op) { _dbg_assert_msg_(CPU,0,"Trying to interpret emuhack instruction that can't be interpreted"); } diff --git a/Core/MIPS/MIPSInt.h b/Core/MIPS/MIPSInt.h index 7f7ad7d1c1..3601365f40 100644 --- a/Core/MIPS/MIPSInt.h +++ b/Core/MIPS/MIPSInt.h @@ -25,33 +25,33 @@ int MIPS_SingleStep(); namespace MIPSInt { - void Int_Unknown(u32 op); - void Int_Unimpl(u32 op); - void Int_Syscall(u32 op); + void Int_Unknown(MIPSOpcode op); + void Int_Unimpl(MIPSOpcode op); + void Int_Syscall(MIPSOpcode op); - void Int_mxc1(u32 op); - void Int_RelBranch(u32 op); - void Int_RelBranchRI(u32 op); - void Int_IType(u32 op); - void Int_ITypeMem(u32 op); - void Int_RType2(u32 op); - void Int_RType3(u32 op); - void Int_ShiftType(u32 op); - void Int_MulDivType(u32 op); - void Int_JumpType(u32 op); - void Int_JumpRegType(u32 op); - void Int_Allegrex2(u32 op); - void Int_FPULS(u32 op); - void Int_FPU3op(u32 op); - void Int_FPU2op(u32 op); - void Int_Allegrex(u32 op); - void Int_FPUComp(u32 op); - void Int_FPUBranch(u32 op); - void Int_Emuhack(u32 op); - void Int_Special3(u32 op); - void Int_Interrupt(u32 op); - void Int_Cache(u32 op); - void Int_Sync(u32 op); - void Int_Break(u32 op); - void Int_StoreSync(u32 op); + void Int_mxc1(MIPSOpcode op); + void Int_RelBranch(MIPSOpcode op); + void Int_RelBranchRI(MIPSOpcode op); + void Int_IType(MIPSOpcode op); + void Int_ITypeMem(MIPSOpcode op); + void Int_RType2(MIPSOpcode op); + void Int_RType3(MIPSOpcode op); + void Int_ShiftType(MIPSOpcode op); + void Int_MulDivType(MIPSOpcode op); + void Int_JumpType(MIPSOpcode op); + void Int_JumpRegType(MIPSOpcode op); + void Int_Allegrex2(MIPSOpcode op); + void Int_FPULS(MIPSOpcode op); + void Int_FPU3op(MIPSOpcode op); + void Int_FPU2op(MIPSOpcode op); + void Int_Allegrex(MIPSOpcode op); + void Int_FPUComp(MIPSOpcode op); + void Int_FPUBranch(MIPSOpcode op); + void Int_Emuhack(MIPSOpcode op); + void Int_Special3(MIPSOpcode op); + void Int_Interrupt(MIPSOpcode op); + void Int_Cache(MIPSOpcode op); + void Int_Sync(MIPSOpcode op); + void Int_Break(MIPSOpcode op); + void Int_StoreSync(MIPSOpcode op); } diff --git a/Core/MIPS/MIPSIntVFPU.cpp b/Core/MIPS/MIPSIntVFPU.cpp index 0dccfd70b8..b91a5d582a 100644 --- a/Core/MIPS/MIPSIntVFPU.cpp +++ b/Core/MIPS/MIPSIntVFPU.cpp @@ -196,7 +196,7 @@ void EatPrefixes() namespace MIPSInt { - void Int_VPFX(u32 op) + void Int_VPFX(MIPSOpcode op) { int data = op & 0xFFFFF; int regnum = (op >> 24) & 3; @@ -204,7 +204,7 @@ namespace MIPSInt PC += 4; } - void Int_SVQ(u32 op) + void Int_SVQ(MIPSOpcode op) { int imm = (signed short)(op&0xFFFC); int rs = _RS; @@ -315,7 +315,7 @@ namespace MIPSInt PC += 4; } - void Int_VMatrixInit(u32 op) + void Int_VMatrixInit(MIPSOpcode op) { static const float idt[16] = { @@ -359,7 +359,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_VVectorInit(u32 op) + void Int_VVectorInit(MIPSOpcode op) { int vd = _VD; VectorSize sz = GetVecSize(op); @@ -387,7 +387,7 @@ namespace MIPSInt PC += 4; } - void Int_Viim(u32 op) + void Int_Viim(MIPSOpcode op) { int vt = _VT; s32 imm = (s16)(op&0xFFFF); @@ -408,7 +408,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vidt(u32 op) + void Int_Vidt(MIPSOpcode op) { int vd = _VD; VectorSize sz = GetVecSize(op); @@ -435,7 +435,7 @@ namespace MIPSInt EatPrefixes(); } // The test really needs some work. - void Int_Vmmul(u32 op) + void Int_Vmmul(MIPSOpcode op) { float s[16]; float t[16]; @@ -468,7 +468,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vmscl(u32 op) + void Int_Vmscl(MIPSOpcode op) { float d[16]; float s[16]; @@ -496,7 +496,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vmmov(u32 op) + void Int_Vmmov(MIPSOpcode op) { float s[16]; int vd = _VD; @@ -509,13 +509,13 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vflush(u32 op) + void Int_Vflush(MIPSOpcode op) { // DEBUG_LOG(CPU,"vflush"); PC += 4; } - void Int_VV2Op(u32 op) + void Int_VV2Op(MIPSOpcode op) { float s[4], d[4]; int vd = _VD; @@ -555,7 +555,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vocp(u32 op) + void Int_Vocp(MIPSOpcode op) { float s[4], d[4]; int vd = _VD; @@ -573,7 +573,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vsocp(u32 op) + void Int_Vsocp(MIPSOpcode op) { float s[4], d[4]; int vd = _VD; @@ -596,7 +596,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vsgn(u32 op) + void Int_Vsgn(MIPSOpcode op) { float s[4], d[4]; int vd = _VD; @@ -627,7 +627,7 @@ namespace MIPSInt return (int)round_ieee_754(param); } - void Int_Vf2i(u32 op) { + void Int_Vf2i(MIPSOpcode op) { float s[4]; int d[4]; int vd = _VD; @@ -665,7 +665,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vi2f(u32 op) + void Int_Vi2f(MIPSOpcode op) { int s[4]; float d[4]; @@ -686,7 +686,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vh2f(u32 op) + void Int_Vh2f(MIPSOpcode op) { u32 s[4]; float d[4]; @@ -721,7 +721,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vf2h(u32 op) + void Int_Vf2h(MIPSOpcode op) { float s[4]; u32 d[4]; @@ -753,7 +753,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vx2i(u32 op) + void Int_Vx2i(MIPSOpcode op) { u32 s[4]; u32 d[4] = {0}; @@ -845,7 +845,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vi2x(u32 op) + void Int_Vi2x(MIPSOpcode op) { int s[4]; u32 d[2] = {0}; @@ -920,7 +920,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_ColorConv(u32 op) + void Int_ColorConv(MIPSOpcode op) { int vd = _VD; int vs = _VS; @@ -969,7 +969,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_VDot(u32 op) + void Int_VDot(MIPSOpcode op) { float s[4], t[4]; float d; @@ -994,7 +994,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_VHdp(u32 op) + void Int_VHdp(MIPSOpcode op) { float s[4], t[4]; float d; @@ -1019,7 +1019,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vbfy(u32 op) + void Int_Vbfy(MIPSOpcode op) { float s[4]; float d[4]; @@ -1051,7 +1051,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vsrt1(u32 op) + void Int_Vsrt1(MIPSOpcode op) { float s[4]; float d[4]; @@ -1074,7 +1074,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vsrt2(u32 op) + void Int_Vsrt2(MIPSOpcode op) { float s[4]; float d[4]; @@ -1097,7 +1097,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vsrt3(u32 op) + void Int_Vsrt3(MIPSOpcode op) { float s[4]; float d[4]; @@ -1120,7 +1120,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vsrt4(u32 op) + void Int_Vsrt4(MIPSOpcode op) { float s[4]; float d[4]; @@ -1143,7 +1143,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vcrs(u32 op) + void Int_Vcrs(MIPSOpcode op) { //half a cross product float s[4], t[4]; @@ -1167,7 +1167,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vdet(u32 op) + void Int_Vdet(MIPSOpcode op) { float s[4], t[4]; float d[4]; @@ -1187,7 +1187,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vfad(u32 op) + void Int_Vfad(MIPSOpcode op) { float s[4]; float d; @@ -1209,7 +1209,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vavg(u32 op) + void Int_Vavg(MIPSOpcode op) { float s[4]; float d; @@ -1231,7 +1231,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_VScl(u32 op) + void Int_VScl(MIPSOpcode op) { float s[4]; float d[4]; @@ -1258,7 +1258,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vrnds(u32 op) + void Int_Vrnds(MIPSOpcode op) { int vd = _VD; int seed = VI(vd); @@ -1267,7 +1267,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_VrndX(u32 op) + void Int_VrndX(MIPSOpcode op) { float d[4]; int vd = _VD; @@ -1290,7 +1290,7 @@ namespace MIPSInt } // Generates one line of a rotation matrix around one of the three axes - void Int_Vrot(u32 op) + void Int_Vrot(MIPSOpcode op) { int vd = _VD; int vs = _VS; @@ -1315,7 +1315,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vtfm(u32 op) + void Int_Vtfm(MIPSOpcode op) { int vd = _VD; int vs = _VS; @@ -1372,7 +1372,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_SV(u32 op) + void Int_SV(MIPSOpcode op) { s32 imm = (signed short)(op&0xFFFC); int vt = ((op >> 16) & 0x1f) | ((op & 3) << 5); @@ -1395,7 +1395,7 @@ namespace MIPSInt } - void Int_Mftv(u32 op) + void Int_Mftv(MIPSOpcode op) { int imm = op & 0xFF; int rt = _RT; @@ -1433,7 +1433,7 @@ namespace MIPSInt PC += 4; } - void Int_Vmfvc(u32 op) { + void Int_Vmfvc(MIPSOpcode op) { int vs = _VS; int imm = op & 0xFF; if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) { @@ -1442,7 +1442,7 @@ namespace MIPSInt PC += 4; } - void Int_Vmtvc(u32 op) { + void Int_Vmtvc(MIPSOpcode op) { int vs = _VS; int imm = op & 0xFF; if (imm >= 128 && imm < 128 + VFPU_CTRL_MAX) { @@ -1451,7 +1451,7 @@ namespace MIPSInt PC += 4; } - void Int_Vcst(u32 op) + void Int_Vcst(MIPSOpcode op) { int conNum = (op >> 16) & 0x1f; int vd = _VD; @@ -1465,7 +1465,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vcmp(u32 op) + void Int_Vcmp(MIPSOpcode op) { int vs = _VS; int vt = _VT; @@ -1527,7 +1527,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vminmax(u32 op) { + void Int_Vminmax(MIPSOpcode op) { int vt = _VT; int vs = _VS; int vd = _VD; @@ -1565,7 +1565,7 @@ namespace MIPSInt } // This doesn't quite pass all the tests :/ - void Int_Vscmp(u32 op) { + void Int_Vscmp(MIPSOpcode op) { int vt = _VT; int vs = _VS; int vd = _VD; @@ -1588,7 +1588,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vsge(u32 op) { + void Int_Vsge(MIPSOpcode op) { int vt = _VT; int vs = _VS; int vd = _VD; @@ -1614,7 +1614,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vslt(u32 op) { + void Int_Vslt(MIPSOpcode op) { int vt = _VT; int vs = _VS; int vd = _VD; @@ -1641,7 +1641,7 @@ namespace MIPSInt } - void Int_Vcmov(u32 op) + void Int_Vcmov(MIPSOpcode op) { int vs = _VS; int vd = _VD; @@ -1683,7 +1683,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_VecDo3(u32 op) + void Int_VecDo3(MIPSOpcode op) { int vd = _VD; int vs = _VS; @@ -1729,7 +1729,7 @@ bad: } - void Int_CrossQuat(u32 op) + void Int_CrossQuat(MIPSOpcode op) { int vd = _VD; int vs = _VS; @@ -1764,7 +1764,7 @@ bad: EatPrefixes(); } - void Int_Vlgb(u32 op) + void Int_Vlgb(MIPSOpcode op) { // S & D valid Reporting::ReportMessage("vlgb not implemented"); @@ -1775,7 +1775,7 @@ bad: // There has to be a concise way of expressing this in terms of // bit manipulation on the raw floats. - void Int_Vwbn(u32 op) { + void Int_Vwbn(MIPSOpcode op) { Reporting::ReportMessage("vwbn not implemented"); _dbg_assert_msg_(CPU,0,"vwbn not implemented"); PC += 4; @@ -1807,7 +1807,7 @@ bad: EatPrefixes();*/ } - void Int_Vsbn(u32 op) + void Int_Vsbn(MIPSOpcode op) { Reporting::ReportMessage("vsbn not implemented"); _dbg_assert_msg_(CPU,0,"vsbn not implemented"); @@ -1815,7 +1815,7 @@ bad: EatPrefixes(); } - void Int_Vsbz(u32 op) + void Int_Vsbz(MIPSOpcode op) { Reporting::ReportMessage("vsbz not implemented"); _dbg_assert_msg_(CPU,0,"vsbz not implemented"); diff --git a/Core/MIPS/MIPSIntVFPU.h b/Core/MIPS/MIPSIntVFPU.h index 8e45efc55b..c2899955ab 100644 --- a/Core/MIPS/MIPSIntVFPU.h +++ b/Core/MIPS/MIPSIntVFPU.h @@ -25,60 +25,60 @@ int MIPS_SingleStep(); namespace MIPSInt { - void Int_SV(u32 op); - void Int_SVQ(u32 op); - void Int_Mftv(u32 op); - void Int_MatrixSet(u32 op); - void Int_VecDo3(u32 op); - void Int_Vcst(u32 op); - void Int_VMatrixInit(u32 op); - void Int_VVectorInit(u32 op); - void Int_Vmmul(u32 op); - void Int_Vmscl(u32 op); - void Int_Vmmov(u32 op); - void Int_VV2Op(u32 op); - void Int_Vrot(u32 op); - void Int_VDot(u32 op); - void Int_VHdp(u32 op); - void Int_Vavg(u32 op); - void Int_Vfad(u32 op); - void Int_Vocp(u32 op); - void Int_Vsocp(u32 op); - void Int_Vsgn(u32 op); - void Int_Vtfm(u32 op); - void Int_Viim(u32 op); - void Int_VScl(u32 op); - void Int_Vidt(u32 op); - void Int_Vcmp(u32 op); - void Int_Vminmax(u32 op); - void Int_Vscmp(u32 op); - void Int_Vcrs(u32 op); - void Int_Vdet(u32 op); - void Int_Vcmov(u32 op); - void Int_CrossQuat(u32 op); - void Int_VPFX(u32 op); - void Int_Vflush(u32 op); - void Int_Vbfy(u32 op); - void Int_Vsrt1(u32 op); - void Int_Vsrt2(u32 op); - void Int_Vsrt3(u32 op); - void Int_Vsrt4(u32 op); - void Int_Vf2i(u32 op); - void Int_Vi2f(u32 op); - void Int_Vi2x(u32 op); - void Int_Vx2i(u32 op); - void Int_VBranch(u32 op); - void Int_Vrnds(u32 op); - void Int_VrndX(u32 op); - void Int_ColorConv(u32 op); - void Int_Vh2f(u32 op); - void Int_Vf2h(u32 op); - void Int_Vsge(u32 op); - void Int_Vslt(u32 op); - void Int_Vmfvc(u32 op); - void Int_Vmtvc(u32 op); - void Int_Vlgb(u32 op); - void Int_Vwbn(u32 op); - void Int_Vsbn(u32 op); - void Int_Vsbz(u32 op); + void Int_SV(MIPSOpcode op); + void Int_SVQ(MIPSOpcode op); + void Int_Mftv(MIPSOpcode op); + void Int_MatrixSet(MIPSOpcode op); + void Int_VecDo3(MIPSOpcode op); + void Int_Vcst(MIPSOpcode op); + void Int_VMatrixInit(MIPSOpcode op); + void Int_VVectorInit(MIPSOpcode op); + void Int_Vmmul(MIPSOpcode op); + void Int_Vmscl(MIPSOpcode op); + void Int_Vmmov(MIPSOpcode op); + void Int_VV2Op(MIPSOpcode op); + void Int_Vrot(MIPSOpcode op); + void Int_VDot(MIPSOpcode op); + void Int_VHdp(MIPSOpcode op); + void Int_Vavg(MIPSOpcode op); + void Int_Vfad(MIPSOpcode op); + void Int_Vocp(MIPSOpcode op); + void Int_Vsocp(MIPSOpcode op); + void Int_Vsgn(MIPSOpcode op); + void Int_Vtfm(MIPSOpcode op); + void Int_Viim(MIPSOpcode op); + void Int_VScl(MIPSOpcode op); + void Int_Vidt(MIPSOpcode op); + void Int_Vcmp(MIPSOpcode op); + void Int_Vminmax(MIPSOpcode op); + void Int_Vscmp(MIPSOpcode op); + void Int_Vcrs(MIPSOpcode op); + void Int_Vdet(MIPSOpcode op); + void Int_Vcmov(MIPSOpcode op); + void Int_CrossQuat(MIPSOpcode op); + void Int_VPFX(MIPSOpcode op); + void Int_Vflush(MIPSOpcode op); + void Int_Vbfy(MIPSOpcode op); + void Int_Vsrt1(MIPSOpcode op); + void Int_Vsrt2(MIPSOpcode op); + void Int_Vsrt3(MIPSOpcode op); + void Int_Vsrt4(MIPSOpcode op); + void Int_Vf2i(MIPSOpcode op); + void Int_Vi2f(MIPSOpcode op); + void Int_Vi2x(MIPSOpcode op); + void Int_Vx2i(MIPSOpcode op); + void Int_VBranch(MIPSOpcode op); + void Int_Vrnds(MIPSOpcode op); + void Int_VrndX(MIPSOpcode op); + void Int_ColorConv(MIPSOpcode op); + void Int_Vh2f(MIPSOpcode op); + void Int_Vf2h(MIPSOpcode op); + void Int_Vsge(MIPSOpcode op); + void Int_Vslt(MIPSOpcode op); + void Int_Vmfvc(MIPSOpcode op); + void Int_Vmtvc(MIPSOpcode op); + void Int_Vlgb(MIPSOpcode op); + void Int_Vwbn(MIPSOpcode op); + void Int_Vsbn(MIPSOpcode op); + void Int_Vsbz(MIPSOpcode op); } \ No newline at end of file diff --git a/Core/MIPS/MIPSStackWalk.cpp b/Core/MIPS/MIPSStackWalk.cpp index d4a9ffcb4c..f520461e37 100644 --- a/Core/MIPS/MIPSStackWalk.cpp +++ b/Core/MIPS/MIPSStackWalk.cpp @@ -44,15 +44,15 @@ namespace MIPSStackWalk { return INVALIDTARGET; } - bool IsSWInstr(u32 op) { + bool IsSWInstr(MIPSOpcode op) { return (op & MIPSTABLE_IMM_MASK) == 0xAC000000; } - bool IsAddImmInstr(u32 op) { + bool IsAddImmInstr(MIPSOpcode op) { return (op & MIPSTABLE_IMM_MASK) == 0x20000000 || (op & MIPSTABLE_IMM_MASK) == 0x24000000; } - bool IsMovRegsInstr(u32 op) { + bool IsMovRegsInstr(MIPSOpcode op) { // TODO: There are more options here. Let's assume addu for now. if ((op & MIPSTABLE_SPECIAL_MASK) == 0x00000021) { return _RS == 0 || _RT == 0; @@ -67,7 +67,7 @@ namespace MIPSStackWalk { // It ought to be pretty close. u32 stop = pc - 32 * 4; for (; Memory::IsValidAddress(pc) && pc >= stop; pc -= 4) { - u32 op = Memory::Read_Instruction(pc); + MIPSOpcode op = Memory::Read_Instruction(pc); // We're looking for a "mov fp, sp" close by a "addiu sp, sp, -N". if (IsMovRegsInstr(op) && _RD == MIPS_REG_FP && (_RS == MIPS_REG_SP || _RT == MIPS_REG_SP)) { @@ -83,7 +83,7 @@ namespace MIPSStackWalk { int ra_offset = -1; u32 stop = entry == INVALIDTARGET ? 0 : entry; for (u32 pc = frame.pc; Memory::IsValidAddress(pc) && pc >= stop; pc -= 4) { - u32 op = Memory::Read_Instruction(pc); + MIPSOpcode op = Memory::Read_Instruction(pc); // Here's where they store the ra address. if (IsSWInstr(op) && _RT == MIPS_REG_RA && _RS == MIPS_REG_SP) { diff --git a/Core/MIPS/MIPSTables.cpp b/Core/MIPS/MIPSTables.cpp index e8c46a8dfd..56124909e4 100644 --- a/Core/MIPS/MIPSTables.cpp +++ b/Core/MIPS/MIPSTables.cpp @@ -891,7 +891,7 @@ const MIPSInstruction *mipsTables[NumEncodings] = //Todo : generate dispatcher functions from above tables //instead of this horribly slow abomination -const MIPSInstruction *MIPSGetInstruction(u32 op) +const MIPSInstruction *MIPSGetInstruction(MIPSOpcode op) { MipsEncoding encoding = Imme; const MIPSInstruction *instr = &tableImmediate[op>>26]; @@ -919,7 +919,7 @@ const MIPSInstruction *MIPSGetInstruction(u32 op) -void MIPSCompileOp(u32 op) +void MIPSCompileOp(MIPSOpcode op) { if (op==0) return; @@ -931,7 +931,7 @@ void MIPSCompileOp(u32 op) (MIPSComp::jit->*(instr->compile))(op); // woohoo, member functions pointers! else { - ERROR_LOG_REPORT(CPU,"MIPSCompileOp %08x failed",op); + ERROR_LOG_REPORT(CPU,"MIPSCompileOp %08x failed",op.encoding); //MessageBox(0,"ARGH2",0,0);//compile an interpreter call } @@ -940,12 +940,12 @@ void MIPSCompileOp(u32 op) } else { - ERROR_LOG_REPORT(CPU, "MIPSCompileOp: Invalid instruction %08x", op); + ERROR_LOG_REPORT(CPU, "MIPSCompileOp: Invalid instruction %08x", op.encoding); } } -void MIPSDisAsm(u32 op, u32 pc, char *out, bool tabsToSpaces) +void MIPSDisAsm(MIPSOpcode op, u32 pc, char *out, bool tabsToSpaces) { if (op == 0) { @@ -973,7 +973,7 @@ void MIPSDisAsm(u32 op, u32 pc, char *out, bool tabsToSpaces) } -void MIPSInterpret(u32 op) //only for those rare ones +void MIPSInterpret(MIPSOpcode op) //only for those rare ones { //if ((op&0xFFFFF000) == 0xd0110000) // Crash(); @@ -986,7 +986,7 @@ void MIPSInterpret(u32 op) //only for those rare ones instr->interpret(op); else { - ERROR_LOG_REPORT(CPU, "Unknown instruction %08x at %08x", op, currentMIPS->pc); + ERROR_LOG_REPORT(CPU, "Unknown instruction %08x at %08x", op.encoding, currentMIPS->pc); // Try to disassemble it char disasm[256]; MIPSDisAsm(op, currentMIPS->pc, disasm); @@ -1014,8 +1014,8 @@ int MIPSInterpret_RunUntil(u64 globalTicks) // int cycles = 0; { again: - u32 op = Memory::Read_U32(curMips->pc); - //u32 op = Memory::Read_Opcode_JIT(mipsr4k.pc); + MIPSOpcode op = MIPSOpcode(Memory::Read_U32(curMips->pc)); + //MIPSOpcode op = Memory::Read_Opcode_JIT(mipsr4k.pc); /* // Choke on VFPU MIPSInfo info = MIPSGetInfo(op); @@ -1079,7 +1079,7 @@ static inline void DelayBranchTo(MIPSState *curMips, u32 where) curMips->inDelaySlot = true; } -const char *MIPSGetName(u32 op) +const char *MIPSGetName(MIPSOpcode op) { static const char *noname = "unk"; const MIPSInstruction *instr = MIPSGetInstruction(op); @@ -1089,7 +1089,7 @@ const char *MIPSGetName(u32 op) return instr->name; } -MIPSInfo MIPSGetInfo(u32 op) +MIPSInfo MIPSGetInfo(MIPSOpcode op) { // int crunch = CRUNCH_MIPS_OP(op); const MIPSInstruction *instr = MIPSGetInstruction(op); @@ -1099,7 +1099,7 @@ MIPSInfo MIPSGetInfo(u32 op) return MIPSInfo(BAD_INSTRUCTION); } -MIPSInterpretFunc MIPSGetInterpretFunc(u32 op) +MIPSInterpretFunc MIPSGetInterpretFunc(MIPSOpcode op) { const MIPSInstruction *instr = MIPSGetInstruction(op); if (instr->interpret) @@ -1109,7 +1109,7 @@ MIPSInterpretFunc MIPSGetInterpretFunc(u32 op) } // TODO: Do something that makes sense here. -int MIPSGetInstructionCycleEstimate(u32 op) +int MIPSGetInstructionCycleEstimate(MIPSOpcode op) { MIPSInfo info = MIPSGetInfo(op); if (info & DELAYSLOT) diff --git a/Core/MIPS/MIPSTables.h b/Core/MIPS/MIPSTables.h index 2264aaa698..ed0fb24404 100644 --- a/Core/MIPS/MIPSTables.h +++ b/Core/MIPS/MIPSTables.h @@ -18,6 +18,7 @@ #pragma once #include "Globals.h" +#include "Core/MIPS/MIPS.h" struct MIPSInfo { MIPSInfo() { @@ -85,19 +86,19 @@ struct MIPSInfo { #define CDECL #endif -typedef void (CDECL *MIPSDisFunc)(u32 opcode, char *out); -typedef void (CDECL *MIPSInterpretFunc)(u32 opcode); +typedef void (CDECL *MIPSDisFunc)(MIPSOpcode opcode, char *out); +typedef void (CDECL *MIPSInterpretFunc)(MIPSOpcode opcode); -void MIPSCompileOp(u32 op); -void MIPSDisAsm(u32 op, u32 pc, char *out, bool tabsToSpaces = false); -MIPSInfo MIPSGetInfo(u32 op); -void MIPSInterpret(u32 op); //only for those rare ones +void MIPSCompileOp(MIPSOpcode op); +void MIPSDisAsm(MIPSOpcode op, u32 pc, char *out, bool tabsToSpaces = false); +MIPSInfo MIPSGetInfo(MIPSOpcode op); +void MIPSInterpret(MIPSOpcode op); //only for those rare ones int MIPSInterpret_RunUntil(u64 globalTicks); -MIPSInterpretFunc MIPSGetInterpretFunc(u32 op); +MIPSInterpretFunc MIPSGetInterpretFunc(MIPSOpcode op); -int MIPSGetInstructionCycleEstimate(u32 op); -const char *MIPSGetName(u32 op); +int MIPSGetInstructionCycleEstimate(MIPSOpcode op); +const char *MIPSGetName(MIPSOpcode op); void FillMIPSTables(); diff --git a/Core/MIPS/MIPSVFPUUtils.cpp b/Core/MIPS/MIPSVFPUUtils.cpp index a192af8c95..b89e988e6d 100644 --- a/Core/MIPS/MIPSVFPUUtils.cpp +++ b/Core/MIPS/MIPSVFPUUtils.cpp @@ -226,7 +226,7 @@ VectorSize GetHalfVectorSize(VectorSize sz) } } -VectorSize GetVecSize(u32 op) +VectorSize GetVecSize(MIPSOpcode op) { int a = (op>>7)&1; int b = (op>>15)&1; @@ -241,7 +241,7 @@ VectorSize GetVecSize(u32 op) } } -MatrixSize GetMtxSize(u32 op) +MatrixSize GetMtxSize(MIPSOpcode op) { int a = (op>>7)&1; int b = (op>>15)&1; diff --git a/Core/MIPS/MIPSVFPUUtils.h b/Core/MIPS/MIPSVFPUUtils.h index d44d2fdf20..68e4a75153 100644 --- a/Core/MIPS/MIPSVFPUUtils.h +++ b/Core/MIPS/MIPSVFPUUtils.h @@ -65,8 +65,8 @@ inline int GetMtx(int matrixReg) { return (matrixReg >> 2) & 7; } -VectorSize GetVecSize(u32 op); -MatrixSize GetMtxSize(u32 op); +VectorSize GetVecSize(MIPSOpcode op); +MatrixSize GetMtxSize(MIPSOpcode op); VectorSize GetHalfVectorSize(VectorSize sz); int GetNumVectorElements(VectorSize sz); int GetMatrixSide(MatrixSize sz); diff --git a/Core/MIPS/x86/CompALU.cpp b/Core/MIPS/x86/CompALU.cpp index 6553b3c8b3..2619d98fa6 100644 --- a/Core/MIPS/x86/CompALU.cpp +++ b/Core/MIPS/x86/CompALU.cpp @@ -39,7 +39,7 @@ using namespace MIPSAnalyst; namespace MIPSComp { - void Jit::CompImmLogic(u32 op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &)) + void Jit::CompImmLogic(MIPSOpcode op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &)) { u32 uimm = (u16)(op & 0xFFFF); int rt = _RT; @@ -52,7 +52,7 @@ namespace MIPSComp gpr.UnlockAll(); } - void Jit::Comp_IType(u32 op) + void Jit::Comp_IType(MIPSOpcode op) { CONDITIONAL_DISABLE; s32 simm = (s32)(s16)(op & 0xFFFF); // sign extension @@ -159,7 +159,7 @@ namespace MIPSComp } } - void Jit::Comp_RType2(u32 op) + void Jit::Comp_RType2(MIPSOpcode op) { CONDITIONAL_DISABLE; int rs = _RS; @@ -266,7 +266,7 @@ namespace MIPSComp } //rd = rs X rt - void Jit::CompTriArith(u32 op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &), u32 (*doImm)(const u32, const u32)) + void Jit::CompTriArith(MIPSOpcode op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &), u32 (*doImm)(const u32, const u32)) { int rt = _RT; int rs = _RS; @@ -323,7 +323,7 @@ namespace MIPSComp gpr.UnlockAll(); } - void Jit::Comp_RType3(u32 op) + void Jit::Comp_RType3(MIPSOpcode op) { CONDITIONAL_DISABLE @@ -507,7 +507,7 @@ namespace MIPSComp return (a >> sa) | (a << (32 - sa)); } - void Jit::CompShiftImm(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32)) + void Jit::CompShiftImm(MIPSOpcode op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32)) { int rd = _RD; int rt = _RT; @@ -528,7 +528,7 @@ namespace MIPSComp } // "over-shifts" work the same as on x86 - only bottom 5 bits are used to get the shift value - void Jit::CompShiftVar(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32)) + void Jit::CompShiftVar(MIPSOpcode op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32)) { int rd = _RD; int rt = _RT; @@ -563,7 +563,7 @@ namespace MIPSComp gpr.UnlockAll(); } - void Jit::Comp_ShiftType(u32 op) + void Jit::Comp_ShiftType(MIPSOpcode op) { CONDITIONAL_DISABLE; int rs = _RS; @@ -591,7 +591,7 @@ namespace MIPSComp } } - void Jit::Comp_Special3(u32 op) + void Jit::Comp_Special3(MIPSOpcode op) { CONDITIONAL_DISABLE; int rs = _RS; @@ -659,7 +659,7 @@ namespace MIPSComp } - void Jit::Comp_Allegrex(u32 op) + void Jit::Comp_Allegrex(MIPSOpcode op) { CONDITIONAL_DISABLE int rt = _RT; @@ -769,7 +769,7 @@ namespace MIPSComp } } - void Jit::Comp_Allegrex2(u32 op) + void Jit::Comp_Allegrex2(MIPSOpcode op) { CONDITIONAL_DISABLE int rt = _RT; @@ -799,7 +799,7 @@ namespace MIPSComp } } - void Jit::Comp_MulDivType(u32 op) + void Jit::Comp_MulDivType(MIPSOpcode op) { CONDITIONAL_DISABLE; int rt = _RT; diff --git a/Core/MIPS/x86/CompBranch.cpp b/Core/MIPS/x86/CompBranch.cpp index 44451de1e3..655dd04d67 100644 --- a/Core/MIPS/x86/CompBranch.cpp +++ b/Core/MIPS/x86/CompBranch.cpp @@ -72,7 +72,7 @@ namespace MIPSComp static u32 intBranchExit; static u32 jitBranchExit; -static void JitBranchLog(u32 op, u32 pc) +static void JitBranchLog(MIPSOpcode op, u32 pc) { currentMIPS->pc = pc; currentMIPS->inDelaySlot = false; @@ -98,7 +98,7 @@ static void JitBranchLog(u32 op, u32 pc) currentMIPS->inDelaySlot = false; } -static void JitBranchLogMismatch(u32 op, u32 pc) +static void JitBranchLogMismatch(MIPSOpcode op, u32 pc) { char temp[256]; MIPSDisAsm(op, pc, temp, true); @@ -106,13 +106,13 @@ static void JitBranchLogMismatch(u32 op, u32 pc) host->SetDebugMode(true); } -void Jit::BranchLog(u32 op) +void Jit::BranchLog(MIPSOpcode op) { FlushAll(); - ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLog, 2), op, js.compilerPC); + ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLog, 2), op.encoding, js.compilerPC); } -void Jit::BranchLogExit(u32 op, u32 dest, bool useEAX) +void Jit::BranchLogExit(MIPSOpcode op, u32 dest, bool useEAX) { OpArg destArg = useEAX ? R(EAX) : Imm32(dest); @@ -120,7 +120,7 @@ void Jit::BranchLogExit(u32 op, u32 dest, bool useEAX) FixupBranch skip = J_CC(CC_E); MOV(32, M((void *) &jitBranchExit), destArg); - ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLogMismatch, 2), op, js.compilerPC); + ABI_CallFunctionCC(thunks.ProtectFunction((void *) &JitBranchLogMismatch, 2), op.encoding, js.compilerPC); // Restore EAX, we probably ruined it. if (useEAX) MOV(32, R(EAX), M((void *) &jitBranchExit)); @@ -128,7 +128,7 @@ void Jit::BranchLogExit(u32 op, u32 dest, bool useEAX) SetJumpTarget(skip); } -void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely) +void Jit::BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely) { CONDITIONAL_LOG; if (js.inDelaySlot) { @@ -140,7 +140,7 @@ void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely) int rs = _RS; u32 targetAddr = js.compilerPC + offset + 4; - u32 delaySlotOp = Memory::Read_Instruction(js.compilerPC+4); + MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC+4); bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs); CONDITIONAL_NICE_DELAYSLOT; @@ -224,7 +224,7 @@ void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely) } } -void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool andLink, bool likely) +void Jit::BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool likely) { CONDITIONAL_LOG; if (js.inDelaySlot) { @@ -235,7 +235,7 @@ void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool andLink, bool likely) int rs = _RS; u32 targetAddr = js.compilerPC + offset + 4; - u32 delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); + MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs); CONDITIONAL_NICE_DELAYSLOT; @@ -321,7 +321,7 @@ void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool andLink, bool likely) } -void Jit::Comp_RelBranch(u32 op) +void Jit::Comp_RelBranch(MIPSOpcode op) { switch (op>>26) { @@ -343,7 +343,7 @@ void Jit::Comp_RelBranch(u32 op) } } -void Jit::Comp_RelBranchRI(u32 op) +void Jit::Comp_RelBranchRI(MIPSOpcode op) { switch ((op >> 16) & 0x1F) { @@ -363,7 +363,7 @@ void Jit::Comp_RelBranchRI(u32 op) // If likely is set, discard the branch slot if NOT taken. -void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely) +void Jit::BranchFPFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely) { CONDITIONAL_LOG; if (js.inDelaySlot) { @@ -373,7 +373,7 @@ void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely) int offset = _IMM16 << 2; u32 targetAddr = js.compilerPC + offset + 4; - u32 delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); + MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); bool delaySlotIsNice = IsDelaySlotNiceFPU(op, delaySlotOp); CONDITIONAL_NICE_DELAYSLOT; if (!likely && delaySlotIsNice) @@ -419,7 +419,7 @@ void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely) } -void Jit::Comp_FPUBranch(u32 op) +void Jit::Comp_FPUBranch(MIPSOpcode op) { switch((op >> 16) & 0x1f) { @@ -434,7 +434,7 @@ void Jit::Comp_FPUBranch(u32 op) } // If likely is set, discard the branch slot if NOT taken. -void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely) +void Jit::BranchVFPUFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely) { CONDITIONAL_LOG; if (js.inDelaySlot) { @@ -444,7 +444,7 @@ void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely) int offset = _IMM16 << 2; u32 targetAddr = js.compilerPC + offset + 4; - u32 delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); + MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); // Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle) // The behavior is undefined - the CPU may take the second branch even if the first one passes. @@ -503,7 +503,7 @@ void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely) } -void Jit::Comp_VBranch(u32 op) +void Jit::Comp_VBranch(MIPSOpcode op) { switch ((op >> 16) & 3) { @@ -517,7 +517,7 @@ void Jit::Comp_VBranch(u32 op) } } -void Jit::Comp_Jump(u32 op) +void Jit::Comp_Jump(MIPSOpcode op) { CONDITIONAL_LOG; if (js.inDelaySlot) { @@ -554,7 +554,7 @@ void Jit::Comp_Jump(u32 op) static u32 savedPC; -void Jit::Comp_JumpReg(u32 op) +void Jit::Comp_JumpReg(MIPSOpcode op) { CONDITIONAL_LOG; if (js.inDelaySlot) { @@ -563,7 +563,7 @@ void Jit::Comp_JumpReg(u32 op) } int rs = _RS; - u32 delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); + MIPSOpcode delaySlotOp = Memory::Read_Instruction(js.compilerPC + 4); bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs); CONDITIONAL_NICE_DELAYSLOT; @@ -611,7 +611,7 @@ void Jit::Comp_JumpReg(u32 op) js.compiling = false; } -void Jit::Comp_Syscall(u32 op) +void Jit::Comp_Syscall(MIPSOpcode op) { FlushAll(); @@ -624,13 +624,13 @@ void Jit::Comp_Syscall(u32 op) if (op == GetSyscallOp("FakeSysCalls", NID_IDLE)) ABI_CallFunction((void *)GetFunc("FakeSysCalls", NID_IDLE)->func); else - ABI_CallFunctionC((void *)&CallSyscall, op); + ABI_CallFunctionC((void *)&CallSyscall, op.encoding); WriteSyscallExit(); js.compiling = false; } -void Jit::Comp_Break(u32 op) +void Jit::Comp_Break(MIPSOpcode op) { Comp_Generic(op); WriteSyscallExit(); diff --git a/Core/MIPS/x86/CompFPU.cpp b/Core/MIPS/x86/CompFPU.cpp index 336c864565..2caa8344e4 100644 --- a/Core/MIPS/x86/CompFPU.cpp +++ b/Core/MIPS/x86/CompFPU.cpp @@ -41,7 +41,7 @@ namespace MIPSComp { -void Jit::CompFPTriArith(u32 op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters) +void Jit::CompFPTriArith(MIPSOpcode op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters) { int ft = _FT; int fs = _FS; @@ -72,7 +72,7 @@ void Jit::CompFPTriArith(u32 op, void (XEmitter::*arith)(X64Reg reg, OpArg), boo fpr.ReleaseSpillLocks(); } -void Jit::Comp_FPU3op(u32 op) +void Jit::Comp_FPU3op(MIPSOpcode op) { CONDITIONAL_DISABLE; switch (op & 0x3f) @@ -89,7 +89,7 @@ void Jit::Comp_FPU3op(u32 op) static u32 MEMORY_ALIGNED16(ssLoadStoreTemp); -void Jit::Comp_FPULS(u32 op) +void Jit::Comp_FPULS(MIPSOpcode op) { CONDITIONAL_DISABLE; s32 offset = (s16)(op&0xFFFF); @@ -171,7 +171,7 @@ void Jit::CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN) } } -void Jit::Comp_FPUComp(u32 op) +void Jit::Comp_FPUComp(MIPSOpcode op) { CONDITIONAL_DISABLE; @@ -225,7 +225,7 @@ void Jit::Comp_FPUComp(u32 op) } } -void Jit::Comp_FPU2op(u32 op) { +void Jit::Comp_FPU2op(MIPSOpcode op) { CONDITIONAL_DISABLE; int fs = _FS; @@ -290,7 +290,7 @@ void Jit::Comp_FPU2op(u32 op) { } } -void Jit::Comp_mxc1(u32 op) +void Jit::Comp_mxc1(MIPSOpcode op) { CONDITIONAL_DISABLE; diff --git a/Core/MIPS/x86/CompLoadStore.cpp b/Core/MIPS/x86/CompLoadStore.cpp index 6469aebea4..6e81899cb9 100644 --- a/Core/MIPS/x86/CompLoadStore.cpp +++ b/Core/MIPS/x86/CompLoadStore.cpp @@ -41,7 +41,7 @@ namespace MIPSComp { - void Jit::CompITypeMemRead(u32 op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), void *safeFunc) + void Jit::CompITypeMemRead(MIPSOpcode op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), void *safeFunc) { CONDITIONAL_DISABLE; int offset = (signed short)(op&0xFFFF); @@ -62,7 +62,7 @@ namespace MIPSComp gpr.UnlockAll(); } - void Jit::CompITypeMemWrite(u32 op, u32 bits, void *safeFunc) + void Jit::CompITypeMemWrite(MIPSOpcode op, u32 bits, void *safeFunc) { CONDITIONAL_DISABLE; int offset = (signed short)(op&0xFFFF); @@ -102,7 +102,7 @@ namespace MIPSComp gpr.UnlockAll(); } - void Jit::CompITypeMemUnpairedLR(u32 op, bool isStore) + void Jit::CompITypeMemUnpairedLR(MIPSOpcode op, bool isStore) { CONDITIONAL_DISABLE; int o = op>>26; @@ -159,7 +159,7 @@ namespace MIPSComp gpr.UnlockAllX(); } - void Jit::CompITypeMemUnpairedLRInner(u32 op, X64Reg shiftReg) + void Jit::CompITypeMemUnpairedLRInner(MIPSOpcode op, X64Reg shiftReg) { CONDITIONAL_DISABLE; int o = op>>26; @@ -251,7 +251,7 @@ namespace MIPSComp } } - void Jit::Comp_ITypeMem(u32 op) + void Jit::Comp_ITypeMem(MIPSOpcode op) { CONDITIONAL_DISABLE; int offset = (signed short)(op&0xFFFF); @@ -299,9 +299,9 @@ namespace MIPSComp case 34: //lwl { - u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4); + MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4); // Looking for lwr rd, offset-3(rs) which makes a pair. - u32 desiredOp = ((op + (4 << 26)) & 0xFFFF0000) + (offset - 3); + u32 desiredOp = ((op & 0xFFFF0000) + (4 << 26)) + (offset - 3); if (!js.inDelaySlot && nextOp == desiredOp) { EatInstruction(nextOp); @@ -315,9 +315,9 @@ namespace MIPSComp case 38: //lwr { - u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4); + MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4); // Looking for lwl rd, offset+3(rs) which makes a pair. - u32 desiredOp = ((op - (4 << 26)) & 0xFFFF0000) + (offset + 3); + u32 desiredOp = ((op & 0xFFFF0000) - (4 << 26)) + (offset + 3); if (!js.inDelaySlot && nextOp == desiredOp) { EatInstruction(nextOp); @@ -331,9 +331,9 @@ namespace MIPSComp case 42: //swl { - u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4); + MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4); // Looking for swr rd, offset-3(rs) which makes a pair. - u32 desiredOp = ((op + (4 << 26)) & 0xFFFF0000) + (offset - 3); + u32 desiredOp = ((op & 0xFFFF0000) + (4 << 26)) + (offset - 3); if (!js.inDelaySlot && nextOp == desiredOp) { EatInstruction(nextOp); @@ -347,9 +347,9 @@ namespace MIPSComp case 46: //swr { - u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4); + MIPSOpcode nextOp = Memory::Read_Instruction(js.compilerPC + 4); // Looking for swl rd, offset+3(rs) which makes a pair. - u32 desiredOp = ((op - (4 << 26)) & 0xFFFF0000) + (offset + 3); + u32 desiredOp = ((op & 0xFFFF0000) - (4 << 26)) + (offset + 3); if (!js.inDelaySlot && nextOp == desiredOp) { EatInstruction(nextOp); diff --git a/Core/MIPS/x86/CompVFPU.cpp b/Core/MIPS/x86/CompVFPU.cpp index dc598ddec4..bf2b7c3d73 100644 --- a/Core/MIPS/x86/CompVFPU.cpp +++ b/Core/MIPS/x86/CompVFPU.cpp @@ -61,7 +61,7 @@ const u32 MEMORY_ALIGNED16( noSignMask[4] ) = {0x7FFFFFFF, 0x7FFFFFFF, 0x7FFFFFF const u32 MEMORY_ALIGNED16( signBitLower[4] ) = {0x80000000, 0, 0, 0}; const float MEMORY_ALIGNED16( oneOneOneOne[4] ) = {1.0f, 1.0f, 1.0f, 1.0f}; -void Jit::Comp_VPFX(u32 op) +void Jit::Comp_VPFX(MIPSOpcode op) { CONDITIONAL_DISABLE; int data = op & 0xFFFFF; @@ -198,7 +198,7 @@ bool IsOverlapSafe(int dreg, int di, int sn, u8 sregs[], int tn = 0, u8 tregs[] static u32 MEMORY_ALIGNED16(ssLoadStoreTemp); -void Jit::Comp_SV(u32 op) { +void Jit::Comp_SV(MIPSOpcode op) { CONDITIONAL_DISABLE; s32 imm = (signed short)(op&0xFFFC); @@ -262,7 +262,7 @@ void Jit::Comp_SV(u32 op) { } } -void Jit::Comp_SVQ(u32 op) +void Jit::Comp_SVQ(MIPSOpcode op) { CONDITIONAL_DISABLE; @@ -412,7 +412,7 @@ void Jit::Comp_SVQ(u32 op) } } -void Jit::Comp_VVectorInit(u32 op) { +void Jit::Comp_VVectorInit(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -445,7 +445,7 @@ void Jit::Comp_VVectorInit(u32 op) { -void Jit::Comp_VIdt(u32 op) { +void Jit::Comp_VIdt(MIPSOpcode op) { CONDITIONAL_DISABLE; int vd = _VD; @@ -477,7 +477,7 @@ void Jit::Comp_VIdt(u32 op) { } -void Jit::Comp_VDot(u32 op) { +void Jit::Comp_VDot(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -521,7 +521,7 @@ void Jit::Comp_VDot(u32 op) { } -void Jit::Comp_VHdp(u32 op) { +void Jit::Comp_VHdp(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -568,7 +568,7 @@ void Jit::Comp_VHdp(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_VCrossQuat(u32 op) { +void Jit::Comp_VCrossQuat(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -676,7 +676,7 @@ void Jit::Comp_VCrossQuat(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_Vcmov(u32 op) { +void Jit::Comp_Vcmov(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -722,7 +722,7 @@ void Jit::Comp_Vcmov(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_VecDo3(u32 op) { +void Jit::Comp_VecDo3(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -861,7 +861,7 @@ void Jit::Comp_VecDo3(u32 op) { static float ssCompareTemp; -void Jit::Comp_Vcmp(u32 op) { +void Jit::Comp_Vcmp(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -1009,11 +1009,11 @@ void Jit::Comp_Vcmp(u32 op) { gpr.UnlockAllX(); } -void Jit::Comp_Vsge(u32 op) { +void Jit::Comp_Vsge(MIPSOpcode op) { DISABLE; } -void Jit::Comp_Vslt(u32 op) { +void Jit::Comp_Vslt(MIPSOpcode op) { DISABLE; } @@ -1030,7 +1030,7 @@ extern const float mulTableVi2f[32] = { 1.0f/(1UL<<28),1.0f/(1UL<<29),1.0f/(1UL<<30),1.0f/(1UL<<31), }; -void Jit::Comp_Vi2f(u32 op) { +void Jit::Comp_Vi2f(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -1096,7 +1096,7 @@ static const float half = 0.5f; static double maxIntAsDouble = (double)0x7fffffff; // that's not equal to 0x80000000 static double minIntAsDouble = (double)(int)0x80000000; -void Jit::Comp_Vf2i(u32 op) { +void Jit::Comp_Vf2i(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) DISABLE; @@ -1165,7 +1165,7 @@ void Jit::Comp_Vf2i(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_Vcst(u32 op) { +void Jit::Comp_Vcst(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -1189,7 +1189,7 @@ void Jit::Comp_Vcst(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_VV2Op(u32 op) { +void Jit::Comp_VV2Op(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -1313,7 +1313,7 @@ void Jit::Comp_VV2Op(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_Mftv(u32 op) { +void Jit::Comp_Mftv(MIPSOpcode op) { CONDITIONAL_DISABLE; int imm = op & 0xFF; @@ -1368,7 +1368,7 @@ void Jit::Comp_Mftv(u32 op) { } } -void Jit::Comp_Vmtvc(u32 op) { +void Jit::Comp_Vmtvc(MIPSOpcode op) { CONDITIONAL_DISABLE; int vs = _VS; int imm = op & 0xFF; @@ -1387,7 +1387,7 @@ void Jit::Comp_Vmtvc(u32 op) { } } -void Jit::Comp_VMatrixInit(u32 op) { +void Jit::Comp_VMatrixInit(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -1430,7 +1430,7 @@ void Jit::Comp_VMatrixInit(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_Vmmov(u32 op) { +void Jit::Comp_Vmmov(MIPSOpcode op) { CONDITIONAL_DISABLE; // TODO: This probably ignores prefixes? @@ -1472,7 +1472,7 @@ void Jit::Comp_Vmmov(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_VScl(u32 op) { +void Jit::Comp_VScl(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -1523,7 +1523,7 @@ void Jit::Comp_VScl(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_Vmmul(u32 op) { +void Jit::Comp_Vmmul(MIPSOpcode op) { CONDITIONAL_DISABLE; // TODO: This probably ignores prefixes? @@ -1587,7 +1587,7 @@ void Jit::Comp_Vmmul(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_Vmscl(u32 op) { +void Jit::Comp_Vmscl(MIPSOpcode op) { CONDITIONAL_DISABLE; // TODO: This probably ignores prefixes? @@ -1632,7 +1632,7 @@ void Jit::Comp_Vmscl(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_Vtfm(u32 op) { +void Jit::Comp_Vtfm(MIPSOpcode op) { CONDITIONAL_DISABLE; // TODO: This probably ignores prefixes? Or maybe uses D? @@ -1689,27 +1689,27 @@ void Jit::Comp_Vtfm(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_VCrs(u32 op) { +void Jit::Comp_VCrs(MIPSOpcode op) { DISABLE; } -void Jit::Comp_VDet(u32 op) { +void Jit::Comp_VDet(MIPSOpcode op) { DISABLE; } -void Jit::Comp_Vi2x(u32 op) { +void Jit::Comp_Vi2x(MIPSOpcode op) { DISABLE; } -void Jit::Comp_Vx2i(u32 op) { +void Jit::Comp_Vx2i(MIPSOpcode op) { DISABLE; } -void Jit::Comp_Vhoriz(u32 op) { +void Jit::Comp_Vhoriz(MIPSOpcode op) { DISABLE; } -void Jit::Comp_Viim(u32 op) { +void Jit::Comp_Viim(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -1729,7 +1729,7 @@ void Jit::Comp_Viim(u32 op) { fpr.ReleaseSpillLocks(); } -void Jit::Comp_Vfim(u32 op) { +void Jit::Comp_Vfim(MIPSOpcode op) { CONDITIONAL_DISABLE; if (js.HasUnknownPrefix()) @@ -1769,7 +1769,7 @@ void SinCosNegSin(float angle) { sincostemp[1] = cosf(angle); } // Very heavily used by FF:CC -void Jit::Comp_VRot(u32 op) { +void Jit::Comp_VRot(MIPSOpcode op) { // DISABLE; CONDITIONAL_DISABLE; diff --git a/Core/MIPS/x86/Jit.cpp b/Core/MIPS/x86/Jit.cpp index 5e1eebd38e..cd820d718e 100644 --- a/Core/MIPS/x86/Jit.cpp +++ b/Core/MIPS/x86/Jit.cpp @@ -97,7 +97,7 @@ u32 JitBreakpoint() return 1; } -static void JitLogMiss(u32 op) +static void JitLogMiss(MIPSOpcode op) { if (USE_JIT_MISSMAP) notJitOps[MIPSGetName(op)]++; @@ -205,7 +205,7 @@ void Jit::CompileDelaySlot(int flags, RegCacheState *state) SAVE_FLAGS; // preserve flag around the delay slot! js.inDelaySlot = true; - u32 op = Memory::Read_Instruction(addr); + MIPSOpcode op = Memory::Read_Instruction(addr); MIPSCompileOp(op); js.inDelaySlot = false; @@ -223,11 +223,11 @@ void Jit::CompileDelaySlot(int flags, RegCacheState *state) void Jit::CompileAt(u32 addr) { CheckJitBreakpoint(addr, 0); - u32 op = Memory::Read_Instruction(addr); + MIPSOpcode op = Memory::Read_Instruction(addr); MIPSCompileOp(op); } -void Jit::EatInstruction(u32 op) +void Jit::EatInstruction(MIPSOpcode op) { MIPSInfo info = MIPSGetInfo(op); _dbg_assert_msg_(JIT, !(info & DELAYSLOT), "Never eat a branch op."); @@ -303,7 +303,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b) // Jit breakpoints are quite fast, so let's do them in release too. CheckJitBreakpoint(js.compilerPC, 0); - u32 inst = Memory::Read_Instruction(js.compilerPC); + MIPSOpcode inst = Memory::Read_Instruction(js.compilerPC); js.downcountAmount += MIPSGetInstructionCycleEstimate(inst); MIPSCompileOp(inst); @@ -338,13 +338,13 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b) return b->normalEntry; } -void Jit::Comp_RunBlock(u32 op) +void Jit::Comp_RunBlock(MIPSOpcode op) { // This shouldn't be necessary, the dispatcher should catch us before we get here. ERROR_LOG(DYNA_REC, "Comp_RunBlock"); } -void Jit::Comp_Generic(u32 op) +void Jit::Comp_Generic(MIPSOpcode op) { FlushAll(); MIPSInterpretFunc func = MIPSGetInterpretFunc(op); @@ -354,9 +354,9 @@ void Jit::Comp_Generic(u32 op) { MOV(32, M(&mips_->pc), Imm32(js.compilerPC)); if (USE_JIT_MISSMAP) - ABI_CallFunctionC((void *)&JitLogMiss, op); + ABI_CallFunctionC((void *)&JitLogMiss, op.encoding); else - ABI_CallFunctionC((void *)func, op); + ABI_CallFunctionC((void *)func, op.encoding); } else ERROR_LOG_REPORT(JIT, "Trying to compile instruction that can't be interpreted"); @@ -868,6 +868,6 @@ void Jit::CallProtectedFunction(void *func, const OpArg &arg1, const u32 arg2, c ABI_CallFunction((void *)thunks.GetLoadRegsFunction()); } -void Jit::Comp_DoNothing(u32 op) { } +void Jit::Comp_DoNothing(MIPSOpcode op) { } } // namespace diff --git a/Core/MIPS/x86/Jit.h b/Core/MIPS/x86/Jit.h index 64546ecc68..be080b6a8c 100644 --- a/Core/MIPS/x86/Jit.h +++ b/Core/MIPS/x86/Jit.h @@ -176,7 +176,7 @@ public: // Compiled ops should ignore delay slots // the compiler will take care of them by itself // OR NOT - void Comp_Generic(u32 op); + void Comp_Generic(MIPSOpcode op); void RunLoopUntil(u64 globalticks); @@ -184,70 +184,70 @@ public: const u8 *DoJit(u32 em_address, JitBlock *b); void CompileAt(u32 addr); - void Comp_RunBlock(u32 op); + void Comp_RunBlock(MIPSOpcode op); // Ops - void Comp_ITypeMem(u32 op); + void Comp_ITypeMem(MIPSOpcode op); - void Comp_RelBranch(u32 op); - void Comp_RelBranchRI(u32 op); - void Comp_FPUBranch(u32 op); - void Comp_FPULS(u32 op); - void Comp_FPUComp(u32 op); - void Comp_Jump(u32 op); - void Comp_JumpReg(u32 op); - void Comp_Syscall(u32 op); - void Comp_Break(u32 op); + void Comp_RelBranch(MIPSOpcode op); + void Comp_RelBranchRI(MIPSOpcode op); + void Comp_FPUBranch(MIPSOpcode op); + void Comp_FPULS(MIPSOpcode op); + void Comp_FPUComp(MIPSOpcode op); + void Comp_Jump(MIPSOpcode op); + void Comp_JumpReg(MIPSOpcode op); + void Comp_Syscall(MIPSOpcode op); + void Comp_Break(MIPSOpcode op); - void Comp_IType(u32 op); - void Comp_RType2(u32 op); - void Comp_RType3(u32 op); - void Comp_ShiftType(u32 op); - void Comp_Allegrex(u32 op); - void Comp_Allegrex2(u32 op); - void Comp_VBranch(u32 op); - void Comp_MulDivType(u32 op); - void Comp_Special3(u32 op); + void Comp_IType(MIPSOpcode op); + void Comp_RType2(MIPSOpcode op); + void Comp_RType3(MIPSOpcode op); + void Comp_ShiftType(MIPSOpcode op); + void Comp_Allegrex(MIPSOpcode op); + void Comp_Allegrex2(MIPSOpcode op); + void Comp_VBranch(MIPSOpcode op); + void Comp_MulDivType(MIPSOpcode op); + void Comp_Special3(MIPSOpcode op); - void Comp_FPU3op(u32 op); - void Comp_FPU2op(u32 op); - void Comp_mxc1(u32 op); + void Comp_FPU3op(MIPSOpcode op); + void Comp_FPU2op(MIPSOpcode op); + void Comp_mxc1(MIPSOpcode op); - void Comp_SV(u32 op); - void Comp_SVQ(u32 op); - void Comp_VPFX(u32 op); - void Comp_VVectorInit(u32 op); - void Comp_VMatrixInit(u32 op); - void Comp_VDot(u32 op); - void Comp_VecDo3(u32 op); - void Comp_VV2Op(u32 op); - void Comp_Mftv(u32 op); - void Comp_Vmtvc(u32 op); - void Comp_Vmmov(u32 op); - void Comp_VScl(u32 op); - void Comp_Vmmul(u32 op); - void Comp_Vmscl(u32 op); - void Comp_Vtfm(u32 op); - void Comp_VHdp(u32 op); - void Comp_VCrs(u32 op); - void Comp_VDet(u32 op); - void Comp_Vi2x(u32 op); - void Comp_Vx2i(u32 op); - void Comp_Vf2i(u32 op); - void Comp_Vi2f(u32 op); - void Comp_Vcst(u32 op); - void Comp_Vhoriz(u32 op); - void Comp_VRot(u32 op); - void Comp_VIdt(u32 op); - void Comp_Vcmp(u32 op); - void Comp_Vcmov(u32 op); - void Comp_Viim(u32 op); - void Comp_Vfim(u32 op); - void Comp_VCrossQuat(u32 op); - void Comp_Vsge(u32 op); - void Comp_Vslt(u32 op); + void Comp_SV(MIPSOpcode op); + void Comp_SVQ(MIPSOpcode op); + void Comp_VPFX(MIPSOpcode op); + void Comp_VVectorInit(MIPSOpcode op); + void Comp_VMatrixInit(MIPSOpcode op); + void Comp_VDot(MIPSOpcode op); + void Comp_VecDo3(MIPSOpcode op); + void Comp_VV2Op(MIPSOpcode op); + void Comp_Mftv(MIPSOpcode op); + void Comp_Vmtvc(MIPSOpcode op); + void Comp_Vmmov(MIPSOpcode op); + void Comp_VScl(MIPSOpcode op); + void Comp_Vmmul(MIPSOpcode op); + void Comp_Vmscl(MIPSOpcode op); + void Comp_Vtfm(MIPSOpcode op); + void Comp_VHdp(MIPSOpcode op); + void Comp_VCrs(MIPSOpcode op); + void Comp_VDet(MIPSOpcode op); + void Comp_Vi2x(MIPSOpcode op); + void Comp_Vx2i(MIPSOpcode op); + void Comp_Vf2i(MIPSOpcode op); + void Comp_Vi2f(MIPSOpcode op); + void Comp_Vcst(MIPSOpcode op); + void Comp_Vhoriz(MIPSOpcode op); + void Comp_VRot(MIPSOpcode op); + void Comp_VIdt(MIPSOpcode op); + void Comp_Vcmp(MIPSOpcode op); + void Comp_Vcmov(MIPSOpcode op); + void Comp_Viim(MIPSOpcode op); + void Comp_Vfim(MIPSOpcode op); + void Comp_VCrossQuat(MIPSOpcode op); + void Comp_Vsge(MIPSOpcode op); + void Comp_Vslt(MIPSOpcode op); - void Comp_DoNothing(u32 op); + void Comp_DoNothing(MIPSOpcode op); void ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz); void ApplyPrefixD(const u8 *vregs, VectorSize sz); @@ -281,7 +281,7 @@ private: void CompileDelaySlot(int flags, RegCacheState &state) { CompileDelaySlot(flags, &state); } - void EatInstruction(u32 op); + void EatInstruction(MIPSOpcode op); void WriteExit(u32 destination, int exit_num); void WriteExitDestInEAX(); @@ -290,24 +290,24 @@ private: bool CheckJitBreakpoint(u32 addr, int downcountOffset); // Utility compilation functions - void BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely); - void BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely); - void BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool andLink, bool likely); - void BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely); - void BranchLog(u32 op); - void BranchLogExit(u32 op, u32 dest, bool useEAX); + void BranchFPFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely); + void BranchVFPUFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely); + void BranchRSZeroComp(MIPSOpcode op, Gen::CCFlags cc, bool andLink, bool likely); + void BranchRSRTComp(MIPSOpcode op, Gen::CCFlags cc, bool likely); + void BranchLog(MIPSOpcode op); + void BranchLogExit(MIPSOpcode op, u32 dest, bool useEAX); // Utilities to reduce duplicated code - void CompImmLogic(u32 op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &)); - void CompTriArith(u32 op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &), u32 (*doImm)(const u32, const u32)); - void CompShiftImm(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32)); - void CompShiftVar(u32 op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32)); - void CompITypeMemRead(u32 op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), void *safeFunc); - void CompITypeMemWrite(u32 op, u32 bits, void *safeFunc); - void CompITypeMemUnpairedLR(u32 op, bool isStore); - void CompITypeMemUnpairedLRInner(u32 op, X64Reg shiftReg); + void CompImmLogic(MIPSOpcode op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &)); + void CompTriArith(MIPSOpcode op, void (XEmitter::*arith)(int, const OpArg &, const OpArg &), u32 (*doImm)(const u32, const u32)); + void CompShiftImm(MIPSOpcode op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32)); + void CompShiftVar(MIPSOpcode op, void (XEmitter::*shift)(int, OpArg, OpArg), u32 (*doImm)(const u32, const u32)); + void CompITypeMemRead(MIPSOpcode op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), void *safeFunc); + void CompITypeMemWrite(MIPSOpcode op, u32 bits, void *safeFunc); + void CompITypeMemUnpairedLR(MIPSOpcode op, bool isStore); + void CompITypeMemUnpairedLRInner(MIPSOpcode op, X64Reg shiftReg); - void CompFPTriArith(u32 op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters); + void CompFPTriArith(MIPSOpcode op, void (XEmitter::*arith)(X64Reg reg, OpArg), bool orderMatters); void CompFPComp(int lhs, int rhs, u8 compare, bool allowNaN = false); void CallProtectedFunction(void *func, const OpArg &arg1); @@ -395,7 +395,7 @@ private: friend class JitSafeMem; }; -typedef void (Jit::*MIPSCompileFunc)(u32 opcode); +typedef void (Jit::*MIPSCompileFunc)(MIPSOpcode opcode); } // namespace MIPSComp diff --git a/Core/MemMap.cpp b/Core/MemMap.cpp index 02aa55fef6..3fd60a8d35 100644 --- a/Core/MemMap.cpp +++ b/Core/MemMap.cpp @@ -122,9 +122,9 @@ void Clear() memset(m_pVRAM, 0, VRAM_SIZE); } -u32 Read_Instruction(u32 address) +Opcode Read_Instruction(u32 address) { - u32 inst = Read_U32(address); + Opcode inst = Opcode(Read_U32(address)); if (MIPS_IS_EMUHACK(inst) && MIPSComp::jit) { JitBlockCache *bc = MIPSComp::jit->GetBlockCache(); @@ -139,16 +139,16 @@ u32 Read_Instruction(u32 address) } } -u32 Read_Opcode_JIT(u32 address) +Opcode Read_Opcode_JIT(u32 address) { return Read_Instruction(address); } // WARNING! No checks! // We assume that _Address is cached -void Write_Opcode_JIT(const u32 _Address, const u32 _Value) +void Write_Opcode_JIT(const u32 _Address, const Opcode _Value) { - Memory::WriteUnchecked_U32(_Value, _Address); + Memory::WriteUnchecked_U32(_Value.encoding, _Address); } void Memset(const u32 _Address, const u8 _iValue, const u32 _iLength) diff --git a/Core/MemMap.h b/Core/MemMap.h index ad2e76a483..417f0e12f5 100644 --- a/Core/MemMap.h +++ b/Core/MemMap.h @@ -97,13 +97,40 @@ void Shutdown(); void DoState(PointerWrap &p); void Clear(); +struct Opcode { + Opcode() { + encoding = 0; + } + + explicit Opcode(u32 v) : encoding (v) { + } + + u32 operator & (const u32 &arg) const { + return encoding & arg; + } + + u32 operator >> (const u32 &arg) const { + return encoding >> arg; + } + + bool operator == (const u32 &arg) const { + return encoding == arg; + } + + bool operator != (const u32 &arg) const { + return encoding != arg; + } + + u32 encoding; +}; + // used by JIT to read instructions -u32 Read_Opcode_JIT(const u32 _Address); +Opcode Read_Opcode_JIT(const u32 _Address); // used by JIT. uses iCacheJIT. Reads in the "Locked cache" mode -void Write_Opcode_JIT(const u32 _Address, const u32 _Value); +void Write_Opcode_JIT(const u32 _Address, const Opcode _Value); // this is used by Debugger a lot. // For now, just reads from memory! -u32 Read_Instruction(const u32 _Address); +Opcode Read_Instruction(const u32 _Address); // For use by emulator From 52d6080fb45920a44a552f5e15b2fe21dc2c67d5 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 24 Aug 2013 15:35:31 -0700 Subject: [PATCH 018/237] Pass in some analysis results, don't use yet. --- Core/MIPS/MIPSAnalyst.cpp | 34 +++++++++++++++++----------------- Core/MIPS/MIPSAnalyst.h | 17 ++++++++++------- Core/MIPS/x86/Jit.cpp | 3 +-- Core/MIPS/x86/RegCache.h | 4 ++-- 4 files changed, 30 insertions(+), 28 deletions(-) diff --git a/Core/MIPS/MIPSAnalyst.cpp b/Core/MIPS/MIPSAnalyst.cpp index b17479d50a..d9a843bb5f 100644 --- a/Core/MIPS/MIPSAnalyst.cpp +++ b/Core/MIPS/MIPSAnalyst.cpp @@ -28,12 +28,8 @@ using namespace MIPSCodeUtils; using namespace std; -#define NUM_MIPS_GPRS 32 - namespace MIPSAnalyst { - RegisterAnalysisResults gprAnal[NUM_MIPS_GPRS]; - // Only can ever output a single reg. int GetOutGPReg(MIPSOpcode op) { MIPSInfo opinfo = MIPSGetInfo(op); @@ -90,16 +86,18 @@ namespace MIPSAnalyst return (op >> 26) == 0 && (op & 0x3f) == 12; } - void Analyze(u32 address) { + AnalysisResults Analyze(u32 address) { const int MAX_ANALYZE = 10000; + AnalysisResults results; + //set everything to -1 (FF) - memset(gprAnal, 255, sizeof(AnalysisResults) * NUM_MIPS_GPRS); - for (int i = 0; i < NUM_MIPS_GPRS; i++) { - gprAnal[i].used = false; - gprAnal[i].readCount = 0; - gprAnal[i].writeCount = 0; - gprAnal[i].readAsAddrCount = 0; + memset(&results, 255, sizeof(AnalysisResults)); + for (int i = 0; i < MIPS_NUM_GPRS; i++) { + results.r[i].used = false; + results.r[i].readCount = 0; + results.r[i].writeCount = 0; + results.r[i].readAsAddrCount = 0; } for (u32 addr = address, endAddr = address + MAX_ANALYZE; addr <= endAddr; addr += 4) { @@ -111,19 +109,19 @@ namespace MIPSAnalyst if (info & IN_RS) { if ((info & IN_RS_ADDR) == IN_RS_ADDR) { - gprAnal[rs].MarkReadAsAddr(addr); + results.r[rs].MarkReadAsAddr(addr); } else { - gprAnal[rs].MarkRead(addr); + results.r[rs].MarkRead(addr); } } if (info & IN_RT) { - gprAnal[rt].MarkRead(addr); + results.r[rt].MarkRead(addr); } int outReg = GetOutGPReg(op); if (outReg != -1) { - gprAnal[outReg].MarkWrite(addr); + results.r[outReg].MarkWrite(addr); } if (info & DELAYSLOT) @@ -136,14 +134,16 @@ namespace MIPSAnalyst int numUsedRegs=0; static int totalUsedRegs=0; static int numAnalyzings=0; - for (int i = 0; i < NUM_MIPS_GPRS; i++) { - if (gprAnal[i].used) { + for (int i = 0; i < MIPS_NUM_GPRS; i++) { + if (results.r[i].used) { numUsedRegs++; } } totalUsedRegs+=numUsedRegs; numAnalyzings++; DEBUG_LOG(CPU,"[ %08x ] Used regs: %i Average: %f",address,numUsedRegs,(float)totalUsedRegs/(float)numAnalyzings); + + return results; } diff --git a/Core/MIPS/MIPSAnalyst.h b/Core/MIPS/MIPSAnalyst.h index 2047212032..d37581aec5 100644 --- a/Core/MIPS/MIPSAnalyst.h +++ b/Core/MIPS/MIPSAnalyst.h @@ -24,7 +24,8 @@ class DebugInterface; namespace MIPSAnalyst { - void Analyze(u32 address); + const int MIPS_NUM_GPRS = 32; + struct RegisterAnalysisResults { bool used; int firstRead; @@ -38,9 +39,9 @@ namespace MIPSAnalyst int writeCount; int readAsAddrCount; - int TotalReadCount() {return readCount + readAsAddrCount;} - int FirstRead() {return firstReadAsAddr < firstRead ? firstReadAsAddr : firstRead;} - int LastRead() {return lastReadAsAddr > lastRead ? lastReadAsAddr : lastRead;} + int TotalReadCount() const { return readCount + readAsAddrCount; } + int FirstRead() const { return firstReadAsAddr < firstRead ? firstReadAsAddr : firstRead; } + int LastRead() const { return lastReadAsAddr > lastRead ? lastReadAsAddr : lastRead; } void MarkRead(u32 addr) { if (firstRead == -1) @@ -67,11 +68,13 @@ namespace MIPSAnalyst } }; - struct AnalysisResults - { - int x; + struct AnalysisResults { + RegisterAnalysisResults r[MIPS_NUM_GPRS]; }; + AnalysisResults Analyze(u32 address); + + bool IsRegisterUsed(u32 reg, u32 addr); void ScanForFunctions(u32 startAddr, u32 endAddr); void CompileLeafs(); diff --git a/Core/MIPS/x86/Jit.cpp b/Core/MIPS/x86/Jit.cpp index cd820d718e..e82dc811c8 100644 --- a/Core/MIPS/x86/Jit.cpp +++ b/Core/MIPS/x86/Jit.cpp @@ -292,8 +292,7 @@ const u8 *Jit::DoJit(u32 em_address, JitBlock *b) b->normalEntry = GetCodePtr(); - // TODO: this needs work - MIPSAnalyst::AnalysisResults analysis; // = MIPSAnalyst::Analyze(em_address); + MIPSAnalyst::AnalysisResults analysis = MIPSAnalyst::Analyze(em_address); gpr.Start(mips_, analysis); fpr.Start(mips_, analysis); diff --git a/Core/MIPS/x86/RegCache.h b/Core/MIPS/x86/RegCache.h index 5bea7d12d3..2af478e0f6 100644 --- a/Core/MIPS/x86/RegCache.h +++ b/Core/MIPS/x86/RegCache.h @@ -17,8 +17,8 @@ #pragma once -#include "x64Emitter.h" -#include "../MIPSAnalyst.h" +#include "Common/x64Emitter.h" +#include "Core/MIPS/MIPSAnalyst.h" using namespace Gen; From 0436b751a70c4a6b374f3dca777f13e0d42f8855 Mon Sep 17 00:00:00 2001 From: Henrik Rydgard Date: Sun, 25 Aug 2013 01:07:51 +0200 Subject: [PATCH 019/237] Let's try W-MS' latest converted JPN font. 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