From cbdc38f68f0eeb79326d6470b2dc66752a6e2ac3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= Date: Wed, 28 Oct 2026 00:02:06 +0100 Subject: [PATCH] Fix volatile ++/-- and anonymous enum arithmetic Avoids the C++20 deprecation warnings (-Wdeprecated-volatile and -Wdeprecated-anon-enum-enum-conversion). No behaviour change. Co-Authored-By: Claude Sonnet 5.5 --- Core/Instance.cpp | 7 ++++--- Core/MIPS/ARM64/Arm64IRCompFPU.cpp | 2 +- Core/MIPS/ARM64/Arm64IRRegCache.cpp | 2 +- Core/MIPS/LoongArch64/LoongArch64CompFPU.cpp | 2 +- Core/MIPS/RiscV/RiscVCompFPU.cpp | 2 +- 5 files changed, 8 insertions(+), 7 deletions(-) diff --git a/Core/Instance.cpp b/Core/Instance.cpp index 09cba0c3f5..20fd1f86db 100644 --- a/Core/Instance.cpp +++ b/Core/Instance.cpp @@ -168,11 +168,12 @@ void InitInstanceCounter() { // so next keeps climbing across runs and eventually wraps this uint8_t. ID 0 is not a // valid instance - it fails the IsFirstInstance() check, which quietly disables config // saving - so skip past it. - if (++buf->next == 0) { + buf->next = (uint8_t)(buf->next + 1); + if (buf->next == 0) { buf->next = 1; } PPSSPP_ID = buf->next; - buf->total++; + buf->total = (uint8_t)(buf->total + 1); }); if (!success) { PPSSPP_ID = 1; @@ -181,7 +182,7 @@ void InitInstanceCounter() { void ShutdownInstanceCounter() { UpdateInstanceCounter([](volatile InstanceInfo *buf) { - buf->total--; + buf->total = (uint8_t)(buf->total - 1); }); #if PPSSPP_PLATFORM(WINDOWS) diff --git a/Core/MIPS/ARM64/Arm64IRCompFPU.cpp b/Core/MIPS/ARM64/Arm64IRCompFPU.cpp index 08dd479256..937d15da85 100644 --- a/Core/MIPS/ARM64/Arm64IRCompFPU.cpp +++ b/Core/MIPS/ARM64/Arm64IRCompFPU.cpp @@ -128,7 +128,7 @@ void Arm64JitBackend::CompIR_FAssign(IRInst inst) { void Arm64JitBackend::CompIR_FCompare(IRInst inst) { CONDITIONAL_DISABLE; - constexpr IRReg IRREG_VFPU_CC = IRREG_VFPU_CTRL_BASE + VFPU_CTRL_CC; + constexpr IRReg IRREG_VFPU_CC = IRREG_VFPU_CTRL_BASE + (int)VFPU_CTRL_CC; switch (inst.op) { case IROp::FCmp: diff --git a/Core/MIPS/ARM64/Arm64IRRegCache.cpp b/Core/MIPS/ARM64/Arm64IRRegCache.cpp index c09f7f0ce2..6c39702d69 100644 --- a/Core/MIPS/ARM64/Arm64IRRegCache.cpp +++ b/Core/MIPS/ARM64/Arm64IRRegCache.cpp @@ -69,7 +69,7 @@ const int *Arm64IRRegCache::GetAllocationOrder(MIPSLoc type, MIPSMap flags, int count = ARRAY_SIZE(allocationOrder); return allocationOrder; } else if (type == MIPSLoc::FREG) { - base = S0 - NUM_X_REGS; + base = S0 - (int)NUM_X_REGS; // We don't really need four temps, probably. // We start with S8 for call flushes. diff --git a/Core/MIPS/LoongArch64/LoongArch64CompFPU.cpp b/Core/MIPS/LoongArch64/LoongArch64CompFPU.cpp index e1335944c9..598bfbe9f2 100644 --- a/Core/MIPS/LoongArch64/LoongArch64CompFPU.cpp +++ b/Core/MIPS/LoongArch64/LoongArch64CompFPU.cpp @@ -290,7 +290,7 @@ void LoongArch64JitBackend::CompIR_FSat(IRInst inst) { void LoongArch64JitBackend::CompIR_FCompare(IRInst inst) { CONDITIONAL_DISABLE; - constexpr IRReg IRREG_VFPU_CC = IRREG_VFPU_CTRL_BASE + VFPU_CTRL_CC; + constexpr IRReg IRREG_VFPU_CC = IRREG_VFPU_CTRL_BASE + (int)VFPU_CTRL_CC; switch (inst.op) { case IROp::FCmp: diff --git a/Core/MIPS/RiscV/RiscVCompFPU.cpp b/Core/MIPS/RiscV/RiscVCompFPU.cpp index e19152dbd8..ef7ef3c8a4 100644 --- a/Core/MIPS/RiscV/RiscVCompFPU.cpp +++ b/Core/MIPS/RiscV/RiscVCompFPU.cpp @@ -305,7 +305,7 @@ void RiscVJitBackend::CompIR_FSat(IRInst inst) { void RiscVJitBackend::CompIR_FCompare(IRInst inst) { CONDITIONAL_DISABLE; - constexpr IRReg IRREG_VFPU_CC = IRREG_VFPU_CTRL_BASE + VFPU_CTRL_CC; + constexpr IRReg IRREG_VFPU_CC = IRREG_VFPU_CTRL_BASE + (int)VFPU_CTRL_CC; switch (inst.op) { case IROp::FCmp: