From c397e2e4da690288e775e82bc77fe5b0b94c8486 Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Tue, 22 Aug 2023 18:32:47 -0700
Subject: [PATCH] x86jit: Flush reg if dirty on map as ptr.

---
 Core/MIPS/IR/IRRegCache.cpp | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Core/MIPS/IR/IRRegCache.cpp b/Core/MIPS/IR/IRRegCache.cpp
index dd4f49cdec..2c2b3a4818 100644
--- a/Core/MIPS/IR/IRRegCache.cpp
+++ b/Core/MIPS/IR/IRRegCache.cpp
@@ -1030,6 +1030,11 @@ IRNativeReg IRNativeRegCacheBase::MapNativeRegAsPointer(IRReg gpr) {
 		return mr[gpr].nReg;
 	}
 
+	// Cannot use if somehow multilane.
+	if (mr[gpr].nReg != -1 && mr[gpr].lane != -1) {
+		FlushNativeReg(mr[gpr].nReg);
+	}
+
 	IRNativeReg nreg = mr[gpr].nReg;
 	if (mr[gpr].loc != MIPSLoc::REG && mr[gpr].loc != MIPSLoc::REG_IMM) {
 		nreg = MapNativeReg(MIPSLoc::REG, gpr, 1, MIPSMap::INIT);
@@ -1040,6 +1045,13 @@ IRNativeReg IRNativeRegCacheBase::MapNativeRegAsPointer(IRReg gpr) {
 		mr[gpr].loc = MIPSLoc::REG;
 		mr[gpr].imm = 0;
 
+#ifdef MASKED_PSP_MEMORY
+		if (nr[mr[gpr].nReg].isDirty) {
+			StoreNativeReg(mr[gpr].nReg, gpr, 1);
+			nr[mr[gpr].nReg].isDirty = false;
+		}
+#endif
+
 		if (!jo_->enablePointerify) {
 			AdjustNativeRegAsPtr(nreg, true);
 			mr[gpr].loc = MIPSLoc::REG_AS_PTR;