From bea74ba162994ed26500415392cdcb334e8cbe07 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Mon, 21 Aug 2023 08:25:25 -0700 Subject: [PATCH] x86jit: Avoid negative offset warning. --- Core/MIPS/x86/X64IRAsm.cpp | 28 ++++++++++++++-------------- Core/MIPS/x86/X64IRCompSystem.cpp | 2 +- Core/MIPS/x86/X64IRJit.cpp | 12 ++++++------ Core/MIPS/x86/X64IRRegCache.h | 5 +++++ 4 files changed, 26 insertions(+), 21 deletions(-) diff --git a/Core/MIPS/x86/X64IRAsm.cpp b/Core/MIPS/x86/X64IRAsm.cpp index 6c66a38eb1..7282bc68d4 100644 --- a/Core/MIPS/x86/X64IRAsm.cpp +++ b/Core/MIPS/x86/X64IRAsm.cpp @@ -54,13 +54,13 @@ void X64JitBackend::GenerateFixedCode(MIPSState *mipsState) { if (jo.useStaticAlloc && false) { saveStaticRegisters_ = AlignCode16(); - //MOV(32, MDisp(CTXREG, -128 + offsetof(MIPSState, downcount)), R(DOWNCOUNTREG)); + //MOV(32, MDisp(CTXREG, downcountOffset), R(DOWNCOUNTREG)); //regs_.EmitSaveStaticRegisters(); RET(); loadStaticRegisters_ = AlignCode16(); //regs_.EmitLoadStaticRegisters(); - //MOV(32, R(DOWNCOUNTREG), MDisp(CTXREG, -128 + offsetof(MIPSState, downcount))); + //MOV(32, R(DOWNCOUNTREG), MDisp(CTXREG, downcountOffset)); RET(); start = saveStaticRegisters_; @@ -71,22 +71,22 @@ void X64JitBackend::GenerateFixedCode(MIPSState *mipsState) { restoreRoundingMode_ = AlignCode16(); { - STMXCSR(MDisp(CTXREG, -128 + offsetof(MIPSState, temp))); + STMXCSR(MDisp(CTXREG, tempOffset)); // Clear the rounding mode and flush-to-zero bits back to 0. - AND(32, MDisp(CTXREG, -128 + offsetof(MIPSState, temp)), Imm32(~(7 << 13))); - LDMXCSR(MDisp(CTXREG, -128 + offsetof(MIPSState, temp))); + AND(32, MDisp(CTXREG, tempOffset), Imm32(~(7 << 13))); + LDMXCSR(MDisp(CTXREG, tempOffset)); RET(); } applyRoundingMode_ = AlignCode16(); { - MOV(32, R(SCRATCH1), MDisp(CTXREG, -128 + offsetof(MIPSState, fcr31))); + MOV(32, R(SCRATCH1), MDisp(CTXREG, fcr31Offset)); AND(32, R(SCRATCH1), Imm32(0x01000003)); // If it's 0 (nearest + no flush0), we don't actually bother setting - we cleared the rounding // mode out in restoreRoundingMode anyway. This is the most common. FixupBranch skip = J_CC(CC_Z); - STMXCSR(MDisp(CTXREG, -128 + offsetof(MIPSState, temp))); + STMXCSR(MDisp(CTXREG, tempOffset)); // The MIPS bits don't correspond exactly, so we have to adjust. // 0 -> 0 (skip2), 1 -> 3, 2 -> 2 (skip2), 3 -> 1 @@ -99,15 +99,15 @@ void X64JitBackend::GenerateFixedCode(MIPSState *mipsState) { SHL(32, R(SCRATCH1), Imm8(13)); // Before setting new bits, we must clear the old ones. // Clearing bits 13-14 (rounding mode) and 15 (flush to zero.) - AND(32, MDisp(CTXREG, -128 + offsetof(MIPSState, temp)), Imm32(~(7 << 13))); - OR(32, MDisp(CTXREG, -128 + offsetof(MIPSState, temp)), R(SCRATCH1)); + AND(32, MDisp(CTXREG, tempOffset), Imm32(~(7 << 13))); + OR(32, MDisp(CTXREG, tempOffset), R(SCRATCH1)); - TEST(32, MDisp(CTXREG, -128 + offsetof(MIPSState, fcr31)), Imm32(1 << 24)); + TEST(32, MDisp(CTXREG, fcr31Offset), Imm32(1 << 24)); FixupBranch skip3 = J_CC(CC_Z); - OR(32, MDisp(CTXREG, -128 + offsetof(MIPSState, temp)), Imm32(1 << 15)); + OR(32, MDisp(CTXREG, tempOffset), Imm32(1 << 15)); SetJumpTarget(skip3); - LDMXCSR(MDisp(CTXREG, -128 + offsetof(MIPSState, temp))); + LDMXCSR(MDisp(CTXREG, tempOffset)); SetJumpTarget(skip); RET(); } @@ -151,7 +151,7 @@ void X64JitBackend::GenerateFixedCode(MIPSState *mipsState) { FixupBranch badCoreState = J_CC(CC_NZ, true); //CMP(32, R(DOWNCOUNTREG), Imm32(0)); - CMP(32, MDisp(CTXREG, -128 + offsetof(MIPSState, downcount)), Imm32(0)); + CMP(32, MDisp(CTXREG, downcountOffset), Imm32(0)); J_CC(CC_S, outerLoop_); FixupBranch skipToRealDispatch = J(); @@ -162,7 +162,7 @@ void X64JitBackend::GenerateFixedCode(MIPSState *mipsState) { // TODO: See if we can get the slice decrement to line up with IR. //CMP(32, R(DOWNCOUNTREG), Imm32(0)); - CMP(32, MDisp(CTXREG, -128 + offsetof(MIPSState, downcount)), Imm32(0)); + CMP(32, MDisp(CTXREG, downcountOffset), Imm32(0)); FixupBranch bail = J_CC(CC_S, true); SetJumpTarget(skipToRealDispatch); diff --git a/Core/MIPS/x86/X64IRCompSystem.cpp b/Core/MIPS/x86/X64IRCompSystem.cpp index 5ff96d0c86..7e1061f494 100644 --- a/Core/MIPS/x86/X64IRCompSystem.cpp +++ b/Core/MIPS/x86/X64IRCompSystem.cpp @@ -47,7 +47,7 @@ void X64JitBackend::CompIR_Basic(IRInst inst) { switch (inst.op) { case IROp::Downcount: //ADD(32, R(DOWNCOUNTREG), R(DOWNCOUNTREG), Imm32(-(s32)inst.constant)); - SUB(32, MDisp(CTXREG, -128 + offsetof(MIPSState, downcount)), Imm32((s32)inst.constant)); + SUB(32, MDisp(CTXREG, downcountOffset), Imm32((s32)inst.constant)); break; case IROp::SetConst: diff --git a/Core/MIPS/x86/X64IRJit.cpp b/Core/MIPS/x86/X64IRJit.cpp index 3cb57d5b2c..6f3d7e24d1 100644 --- a/Core/MIPS/x86/X64IRJit.cpp +++ b/Core/MIPS/x86/X64IRJit.cpp @@ -64,7 +64,7 @@ bool X64JitBackend::CompileBlock(IRBlock *block, int block_num, bool preload) { // TODO: See if we can get flags to always have the downcount compare. //CMP(32, R(DOWNCOUNTREG), Imm32(0)); - CMP(32, MDisp(CTXREG, -128 + offsetof(MIPSState, downcount)), Imm32(0)); + CMP(32, MDisp(CTXREG, downcountOffset), Imm32(0)); FixupBranch normalEntry = J_CC(CC_NS); MOV(32, R(SCRATCH1), Imm32(startPC)); JMP(outerLoopPCInSCRATCH1_, true); @@ -117,7 +117,7 @@ bool X64JitBackend::CompileBlock(IRBlock *block, int block_num, bool preload) { if (jo.enableBlocklink && jo.useBackJump) { //CMP(32, R(DOWNCOUNTREG), Imm32(0)); - CMP(32, MDisp(CTXREG, -128 + offsetof(MIPSState, downcount)), Imm32(0)); + CMP(32, MDisp(CTXREG, downcountOffset), Imm32(0)); J_CC(CC_NS, blockStart, true); MOV(32, R(SCRATCH1), Imm32(startPC)); @@ -302,11 +302,11 @@ void X64JitBackend::ApplyRoundingMode(bool force) { } void X64JitBackend::MovFromPC(X64Reg r) { - MOV(32, R(r), MDisp(CTXREG, -128 + offsetof(MIPSState, pc))); + MOV(32, R(r), MDisp(CTXREG, pcOffset)); } void X64JitBackend::MovToPC(X64Reg r) { - MOV(32, MDisp(CTXREG, -128 + offsetof(MIPSState, pc)), R(r)); + MOV(32, MDisp(CTXREG, pcOffset), R(r)); } void X64JitBackend::SaveStaticRegisters() { @@ -314,7 +314,7 @@ void X64JitBackend::SaveStaticRegisters() { //CALL(saveStaticRegisters_); } else { // Inline the single operation - //MOV(32, MDisp(CTXREG, -128 + offsetof(MIPSState, downcount)), R(DOWNCOUNTREG)); + //MOV(32, MDisp(CTXREG, downcountOffset), R(DOWNCOUNTREG)); } } @@ -322,7 +322,7 @@ void X64JitBackend::LoadStaticRegisters() { if (jo.useStaticAlloc) { //CALL(loadStaticRegisters_); } else { - //MOV(32, R(DOWNCOUNTREG), MDisp(CTXREG, -128 + offsetof(MIPSState, downcount))); + //MOV(32, R(DOWNCOUNTREG), MDisp(CTXREG, downcountOffset)); } } diff --git a/Core/MIPS/x86/X64IRRegCache.h b/Core/MIPS/x86/X64IRRegCache.h index 036fc4fbe5..a56dffb3a7 100644 --- a/Core/MIPS/x86/X64IRRegCache.h +++ b/Core/MIPS/x86/X64IRRegCache.h @@ -36,6 +36,11 @@ const Gen::X64Reg CTXREG = Gen::EBP; #endif const Gen::X64Reg SCRATCH1 = Gen::EAX; +static constexpr auto downcountOffset = offsetof(MIPSState, downcount) - 128; +static constexpr auto tempOffset = offsetof(MIPSState, temp) - 128; +static constexpr auto fcr31Offset = offsetof(MIPSState, fcr31) - 128; +static constexpr auto pcOffset = offsetof(MIPSState, pc) - 128; + } // namespace X64IRJitConstants class X64IRRegCache : public IRNativeRegCacheBase {