From b5ee47a80c38e51399e4635206365e933850e79e Mon Sep 17 00:00:00 2001
From: Henrik Rydgard <hrydgard@gmail.com>
Date: Tue, 25 Nov 2014 23:28:29 +0100
Subject: [PATCH] x86 jit: SIMD-ify lv.q and sv.q

---
 Core/MIPS/x86/CompVFPU.cpp | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/Core/MIPS/x86/CompVFPU.cpp b/Core/MIPS/x86/CompVFPU.cpp
index e1abbe90ad..8e53d9be9d 100644
--- a/Core/MIPS/x86/CompVFPU.cpp
+++ b/Core/MIPS/x86/CompVFPU.cpp
@@ -376,6 +376,22 @@ void Jit::Comp_SVQ(MIPSOpcode op)
 	
 			u8 vregs[4];
 			GetVectorRegs(vregs, V_Quad, vt);
+
+			if (g_Config.bFastMemory && fpr.TryMapRegsVS(vregs, V_Quad, MAP_NOINIT | MAP_DIRTY)) {
+				JitSafeMem safe(this, rs, imm);
+				safe.SetFar();
+				OpArg src;
+				if (safe.PrepareRead(src, 16)) {
+					MOVAPS(fpr.VSX(vregs[0]), safe.NextFastAddress(0));
+				} else {
+					// Hmm... probably never happens.
+				}
+				safe.Finish();
+				gpr.UnlockAll();
+				fpr.ReleaseSpillLocks();
+				return;
+			}
+
 			fpr.MapRegsV(vregs, V_Quad, MAP_DIRTY | MAP_NOINIT);
 
 			JitSafeMem safe(this, rs, imm);
@@ -409,6 +425,22 @@ void Jit::Comp_SVQ(MIPSOpcode op)
 
 			u8 vregs[4];
 			GetVectorRegs(vregs, V_Quad, vt);
+
+			if (g_Config.bFastMemory && fpr.TryMapRegsVS(vregs, V_Quad, 0)) {
+				JitSafeMem safe(this, rs, imm);
+				safe.SetFar();
+				OpArg dest;
+				if (safe.PrepareWrite(dest, 16)) {
+					MOVAPS(safe.NextFastAddress(0), fpr.VSX(vregs[0]));
+				} else {
+					// Hmm... probably never happens.
+				}
+				safe.Finish();
+				gpr.UnlockAll();
+				fpr.ReleaseSpillLocks();
+				return;
+			}
+
 			// Even if we don't use real SIMD there's still 8 or 16 scalar float registers.
 			fpr.MapRegsV(vregs, V_Quad, 0);