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Armjit: Optimise swl+swr and lwl+lwr cases that can be combined to a single sw or lw. Add shift flags to STR/LDR. Add EatInstruction to ArmJit.
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-46
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@@ -98,6 +98,32 @@ namespace MIPSComp
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// Don't load anything into $zr
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return;
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}
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// Optimisation: Combine to single unaligned load/store
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switch(o)
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{
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case 34: //lwl
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case 38: //lwr
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load = true;
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case 42: //swl
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case 46: //swr
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{
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int left = (o == 34 || o == 42) ? 1 : -1;
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u32 nextOp = Memory::Read_Instruction(js.compilerPC + 4);
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// Find a matching shift in opposite direction with opposite offset.
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u32 desiredOp = ((op + left* (4 << 26)) & 0xFFFF0000) + (offset - left*3);
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if (!js.inDelaySlot && nextOp == desiredOp)
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{
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EatInstruction(nextOp);
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nextOp = ((load ? 35 : 43) << 26) | (nextOp & 0x3FFFFFF); //lw, sw
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Comp_ITypeMem(nextOp);
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return;
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}
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}
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default:
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break;
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}
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switch (o)
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{
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case 32: //lb
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@@ -138,45 +164,6 @@ namespace MIPSComp
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return;
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}
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break;
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/*
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case 34: //lwl
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{
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Crash();
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//u32 shift = (addr & 3) << 3;
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//u32 mem = ReadMem32(addr & 0xfffffffc);
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//R(rt) = ( u32(R(rt)) & (0x00ffffff >> shift) ) | ( mem << (24 - shift) );
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}
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break;
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case 38: //lwr
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{
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Crash();
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//u32 shift = (addr & 3) << 3;
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//u32 mem = ReadMem32(addr & 0xfffffffc);
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//R(rt) = ( u32(rt) & (0xffffff00 << (24 - shift)) ) | ( mem >> shift );
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}
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break;
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case 42: //swl
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{
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Crash();
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//u32 shift = (addr & 3) << 3;
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//u32 mem = ReadMem32(addr & 0xfffffffc);
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//WriteMem32((addr & 0xfffffffc), ( ( u32(R(rt)) >> (24 - shift) ) ) |
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// ( mem & (0xffffff00 << shift) ));
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}
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break;
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case 46: //swr
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{
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Crash();
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// u32 shift = (addr & 3) << 3;
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// u32 mem = ReadMem32(addr & 0xfffffffc);
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//
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// WriteMem32((addr & 0xfffffffc), ( ( u32(R(rt)) << shift ) |
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// (mem & (0x00ffffff >> (24 - shift)) ) ) );
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}
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break;*/
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default:
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Comp_Generic(op);
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return ;
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