From 8ca487910eae52dcdfe74ee097365d526d4b2423 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= Date: Thu, 15 Oct 2026 02:13:23 +0200 Subject: [PATCH] IR: vc2i and vuc2i read their source at the size encoded They read one lane, the first of the source vector at the size in the instruction, as the interpreter does, which for the pair and quad encodings is another register than the single the IR took. Co-Authored-By: Claude Opus 5.5 (1M context) --- Core/MIPS/IR/IRCompVFPU.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Core/MIPS/IR/IRCompVFPU.cpp b/Core/MIPS/IR/IRCompVFPU.cpp index 24fce93ab9..5aa94ebf58 100644 --- a/Core/MIPS/IR/IRCompVFPU.cpp +++ b/Core/MIPS/IR/IRCompVFPU.cpp @@ -2193,9 +2193,15 @@ namespace MIPSComp { VectorSize sz = GetVecSize(op); VectorSize outsize; + // vc2i and vuc2i read one lane, the first of the source at the size encoded, which decides + // which register that is. + int sourceReg = -1; if (bits == 8) { outsize = V_Quad; - sz = V_Single; // For some reason, sz is set to Quad in this case though the outsize is Single. + u8 full[4]; + GetVectorRegs(full, sz, _VS); + sourceReg = full[0]; + sz = V_Single; } else { switch (sz) { case V_Single: @@ -2211,6 +2217,8 @@ namespace MIPSComp { u8 sregs[2], dregs[4], tempregs[4], srcregs[2]; GetVectorRegsPrefixS(sregs, sz, _VS); + if (sourceReg >= 0) + sregs[0] = sourceReg; GetVectorRegsPrefixD(dregs, outsize, _VD); memcpy(tempregs, dregs, sizeof(dregs)); memcpy(srcregs, sregs, sizeof(sregs));