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ARM32: Start an IR-based JIT

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The backend follows the ARM64 one: a dispatcher, a register cache on top of the IR one, and
native exits, syscalls, breakpoints and transfers. Everything else goes to the IR interpreter
for now. Floats are mapped one lane per S register (no SIMD mapping yet), and addresses are
masked, as on every 32-bit build.

The JIT core now uses it on ARM32 in place of the old ArmJit.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
This commit is contained in:
Henrik RydgårdandClaude Opus 5.5 committed 2026-10-14 17:32:53 +02:00
1 parent 2e3b844cff
commit 6d105ae35d
19 files changed
+2222 -2
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android/jni/Android.mk
+9
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@@ -520,6 +520,15 @@ ARCH_FILES := \
$(SRC)/Core/MIPS/ARM/ArmJit.cpp \
$(SRC)/Core/MIPS/ARM/ArmRegCache.cpp \
$(SRC)/Core/MIPS/ARM/ArmRegCacheFPU.cpp \
$(SRC)/Core/MIPS/ARM/ArmIRAsm.cpp \
$(SRC)/Core/MIPS/ARM/ArmIRCompALU.cpp \
$(SRC)/Core/MIPS/ARM/ArmIRCompBranch.cpp \
$(SRC)/Core/MIPS/ARM/ArmIRCompFPU.cpp \
$(SRC)/Core/MIPS/ARM/ArmIRCompLoadStore.cpp \
$(SRC)/Core/MIPS/ARM/ArmIRCompSystem.cpp \
$(SRC)/Core/MIPS/ARM/ArmIRCompVec.cpp \
$(SRC)/Core/MIPS/ARM/ArmIRJit.cpp \
$(SRC)/Core/MIPS/ARM/ArmIRRegCache.cpp \
$(SRC)/GPU/Common/VertexDecoderArm.cpp \
ArmEmitterTest.cpp
else ifeq ($(findstring arm64-v8a,$(TARGET_ARCH_ABI)),arm64-v8a)