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ARM32: Start an IR-based JIT
The backend follows the ARM64 one: a dispatcher, a register cache on top of the IR one, and native exits, syscalls, breakpoints and transfers. Everything else goes to the IR interpreter for now. Floats are mapped one lane per S register (no SIMD mapping yet), and addresses are masked, as on every 32-bit build. The JIT core now uses it on ARM32 in place of the old ArmJit. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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Henrik RydgårdandClaude Opus 5.5 committed
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// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM)
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#ifndef offsetof
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#include <cstddef>
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#endif
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#include "Common/LogReporting.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/IR/IRInst.h"
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#include "Core/MIPS/IR/IRAnalysis.h"
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#include "Core/MIPS/ARM/ArmIRRegCache.h"
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#include "Core/MIPS/JitCommon/JitState.h"
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using namespace ArmGen;
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using namespace ArmIRJitConstants;
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ArmIRRegCache::ArmIRRegCache(MIPSComp::JitOptions *jo)
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: IRNativeRegCacheBase(jo) {
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config_.totalNativeRegs = NUM_GPRS + NUM_FPRS;
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config_.mapFPUSIMD = false;
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config_.mapUseVRegs = false;
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}
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void ArmIRRegCache::Init(ARMXEmitter *emitter) {
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emit_ = emitter;
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}
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const int *ArmIRRegCache::GetAllocationOrder(MIPSLoc type, MIPSMap flags, int &count, int &base) const {
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// ARMReg values are used directly as native reg numbers.
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base = 0;
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if (type == MIPSLoc::REG) {
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// R0/R1 are scratch, R9-R11 are fixed (see ArmIRJitConstants), R13/R15 are SP/PC.
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// The callee-saved ones come first, since they survive calls.
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static const int allocationOrder[] = {
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R4, R5, R6, R7, R8, R2, R3, R12, R14,
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};
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count = ARRAY_SIZE(allocationOrder);
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return allocationOrder;
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} else if (type == MIPSLoc::FREG) {
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// S16-S31 (D8-D15) are callee-saved. S0-S3 are scratch.
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static const int allocationOrder[] = {
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S16, S17, S18, S19, S20, S21, S22, S23,
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S24, S25, S26, S27, S28, S29, S30, S31,
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S4, S5, S6, S7, S8, S9, S10, S11,
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S12, S13, S14, S15,
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};
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count = ARRAY_SIZE(allocationOrder);
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return allocationOrder;
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} else {
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_assert_msg_(false, "Allocation order not yet implemented");
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count = 0;
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return nullptr;
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}
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}
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void ArmIRRegCache::FlushBeforeCall() {
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// These are not preserved by calls.
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for (int r : { R2, R3, R12, R14 })
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FlushNativeReg((IRNativeReg)r);
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for (int r = S4; r <= S15; ++r)
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FlushNativeReg((IRNativeReg)r);
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}
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ARMReg ArmIRRegCache::TryMapTempImm(IRReg r) {
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_dbg_assert_(IsValidGPR(r));
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// If already mapped, no need for a temporary.
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if (IsGPRMapped(r)) {
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return R(r);
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}
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if (mr[r].loc == MIPSLoc::IMM) {
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// Try our luck - check for an exact match in another reg.
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for (int i = 1; i < TOTAL_MAPPABLE_IRREGS; ++i) {
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if (mr[i].loc == MIPSLoc::REG_IMM && mr[i].imm == mr[r].imm) {
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return (ARMReg)mr[i].nReg;
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}
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}
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}
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return INVALID_REG;
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}
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ARMReg ArmIRRegCache::GetAndLockTempGPR() {
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IRNativeReg reg = AllocateReg(MIPSLoc::REG, MIPSMap::INIT);
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if (reg != -1) {
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nr[reg].tempLockIRIndex = irIndex_;
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}
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return (ARMReg)reg;
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}
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ARMReg ArmIRRegCache::GetAndLockTempFPR() {
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IRNativeReg reg = AllocateReg(MIPSLoc::FREG, MIPSMap::INIT);
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if (reg != -1) {
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nr[reg].tempLockIRIndex = irIndex_;
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}
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return (ARMReg)reg;
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}
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ARMReg ArmIRRegCache::MapWithFPRTemp(const IRInst &inst) {
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return (ARMReg)MapWithTemp(inst, MIPSLoc::FREG);
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}
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ARMReg ArmIRRegCache::MapGPR(IRReg mipsReg, MIPSMap mapFlags) {
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_dbg_assert_(IsValidGPR(mipsReg));
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IRNativeReg nreg = MapNativeReg(MIPSLoc::REG, mipsReg, 1, mapFlags);
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return (ARMReg)nreg;
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}
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ARMReg ArmIRRegCache::MapFPR(IRReg mipsReg, MIPSMap mapFlags) {
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_dbg_assert_(IsValidFPR(mipsReg));
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_dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::MEM || mr[mipsReg + 32].loc == MIPSLoc::FREG);
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IRNativeReg nreg = MapNativeReg(MIPSLoc::FREG, mipsReg + 32, 1, mapFlags);
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if (nreg != -1)
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return (ARMReg)nreg;
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return INVALID_REG;
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}
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void ArmIRRegCache::AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) {
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_assert_(nreg >= 0 && nreg < NUM_GPRS);
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ARMReg r = (ARMReg)nreg;
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// 32-bit builds always mask PSP addresses, which destroys the value.
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if (state) {
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_dbg_assert_(!nr[nreg].isDirty);
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emit_->BIC(r, r, Operand2(0xC0, 4));
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emit_->ADD(r, r, MEMBASEREG);
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} else {
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_dbg_assert_(!nr[nreg].isDirty);
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emit_->SUB(r, r, MEMBASEREG);
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}
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}
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bool ArmIRRegCache::IsNativeRegCompatible(IRNativeReg nreg, MIPSLoc type, MIPSMap flags, int lanes) {
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// Every reg holds one lane.
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return lanes == 1 && IRNativeRegCacheBase::IsNativeRegCompatible(nreg, type, flags, lanes);
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}
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void ArmIRRegCache::LoadNativeReg(IRNativeReg nreg, IRReg first, int lanes) {
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_dbg_assert_(first != MIPS_REG_ZERO);
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_assert_msg_(lanes == 1, "Can't load %d lanes", lanes);
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ARMReg r = (ARMReg)nreg;
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if (nreg < NUM_GPRS) {
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emit_->LDR(r, CTXREG, GetMipsRegOffset(first));
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} else {
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_assert_msg_(mr[first].loc == MIPSLoc::FREG, "Cannot load this type: %d", (int)mr[first].loc);
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emit_->VLDR(r, CTXREG, GetMipsRegOffset(first));
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}
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}
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void ArmIRRegCache::StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) {
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_dbg_assert_(first != MIPS_REG_ZERO);
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_assert_msg_(lanes == 1, "Can't store %d lanes", lanes);
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ARMReg r = (ARMReg)nreg;
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if (nreg < NUM_GPRS) {
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_assert_(mr[first].loc == MIPSLoc::REG || mr[first].loc == MIPSLoc::REG_IMM);
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emit_->STR(r, CTXREG, GetMipsRegOffset(first));
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} else {
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_assert_msg_(mr[first].loc == MIPSLoc::FREG, "Cannot store this type: %d", (int)mr[first].loc);
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emit_->VSTR(r, CTXREG, GetMipsRegOffset(first));
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}
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}
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void ArmIRRegCache::SetNativeRegValue(IRNativeReg nreg, uint32_t imm) {
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_dbg_assert_(nreg >= 0 && nreg < NUM_GPRS);
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emit_->MOVI2R((ARMReg)nreg, imm);
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}
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void ArmIRRegCache::StoreRegValue(IRReg mreg, uint32_t imm) {
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_assert_(IsValidGPRNoZero(mreg));
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// Could we get lucky? Check for an exact match in another reg.
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ARMReg storeReg = INVALID_REG;
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for (int i = 1; i < TOTAL_MAPPABLE_IRREGS; ++i) {
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if (mr[i].loc == MIPSLoc::REG_IMM && mr[i].imm == imm) {
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storeReg = (ARMReg)mr[i].nReg;
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break;
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}
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}
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if (storeReg == INVALID_REG) {
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emit_->MOVI2R(SCRATCH1, imm);
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storeReg = SCRATCH1;
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}
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emit_->STR(storeReg, CTXREG, GetMipsRegOffset(mreg));
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}
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void ArmIRRegCache::FlushAll(bool gprs, bool fprs) {
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// Note: make sure not to change the registers when flushing:
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// Branching code may expect the armreg to retain its value.
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IRNativeRegCacheBase::FlushAll(gprs, fprs);
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}
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ARMReg ArmIRRegCache::R(IRReg mipsReg) {
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_dbg_assert_(IsValidGPR(mipsReg));
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_dbg_assert_(mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM);
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if (mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM) {
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return (ARMReg)mr[mipsReg].nReg;
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} else {
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ERROR_LOG_REPORT(Log::JIT, "Reg %i not in arm reg", mipsReg);
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return INVALID_REG; // BAAAD
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}
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}
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ARMReg ArmIRRegCache::F(IRReg mipsReg) {
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_dbg_assert_(IsValidFPR(mipsReg));
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_dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::FREG);
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if (mr[mipsReg + 32].loc == MIPSLoc::FREG) {
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return (ARMReg)mr[mipsReg + 32].nReg;
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} else {
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ERROR_LOG_REPORT(Log::JIT, "Reg %i not in arm reg", mipsReg);
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return INVALID_REG; // BAAAD
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}
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}
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#endif
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