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ARM32: Start an IR-based JIT
The backend follows the ARM64 one: a dispatcher, a register cache on top of the IR one, and native exits, syscalls, breakpoints and transfers. Everything else goes to the IR interpreter for now. Floats are mapped one lane per S register (no SIMD mapping yet), and addresses are masked, as on every 32-bit build. The JIT core now uses it on ARM32 in place of the old ArmJit. Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
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Henrik RydgårdandClaude Opus 5.5 committed
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// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(ARM)
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#include "Common/Profiler/Profiler.h"
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#include "Core/Core.h"
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#include "Core/Debugger/Breakpoints.h"
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#include "Core/HLE/HLE.h"
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#include "Core/HLE/ReplaceTables.h"
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/MIPS/IR/IRInterpreter.h"
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#include "Core/MIPS/ARM/ArmIRJit.h"
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#include "Core/MIPS/ARM/ArmIRRegCache.h"
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// This file contains compilation for basic PC/downcount accounting, syscalls, debug funcs, etc.
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//
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE. No flags because that's in IR already.
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// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
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#define CONDITIONAL_DISABLE {}
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#define DISABLE { CompIR_Generic(inst); return; }
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#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
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namespace MIPSComp {
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using namespace ArmGen;
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using namespace ArmIRJitConstants;
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void ArmJitBackend::CompIR_Basic(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Downcount:
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SUBI2R(DOWNCOUNTREG, DOWNCOUNTREG, inst.constant, SCRATCH1);
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break;
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case IROp::SetConst:
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regs_.SetGPRImm(inst.dest, inst.constant);
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break;
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case IROp::SetConstF:
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{
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regs_.Map(inst);
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float f;
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memcpy(&f, &inst.constant, sizeof(f));
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MOVI2F(regs_.F(inst.dest), f, SCRATCH1);
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break;
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}
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case IROp::SetPC:
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regs_.Map(inst);
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MovToPC(regs_.R(inst.src1));
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break;
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case IROp::SetPCConst:
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lastConstPC_ = inst.constant;
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MOVI2R(SCRATCH1, inst.constant);
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MovToPC(SCRATCH1);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void ArmJitBackend::CompIR_Breakpoint(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Breakpoint:
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FlushAll();
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// Note: the constant could be a delay slot.
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MOVI2R(R0, inst.constant);
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QuickCallFunction(R12, &IRRunBreakpoint);
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CMP(R0, Operand2(0));
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B_CC(CC_NEQ, dispatcherCheckCoreState_);
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break;
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case IROp::MemoryCheck:
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if (regs_.IsGPRImm(inst.src1)) {
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uint32_t iaddr = regs_.GetGPRImm(inst.src1) + inst.constant;
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uint32_t checkedPC = lastConstPC_ + inst.dest;
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int size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);
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if (size == 0) {
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checkedPC += 4;
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size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);
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}
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bool isWrite = MIPSAnalyst::IsOpMemoryWrite(checkedPC);
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MemCheck check;
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if (g_breakpoints.GetMemCheckInRange(iaddr, size, &check)) {
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if (!(check.cond & MEMCHECK_READ) && !isWrite)
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break;
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if (!(check.cond & (MEMCHECK_WRITE | MEMCHECK_WRITE_ONCHANGE)) && isWrite)
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break;
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// We need to flush, or conditions and log expressions will see old register values.
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FlushAll();
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MOVI2R(R0, checkedPC);
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MOVI2R(R1, iaddr);
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QuickCallFunction(R12, &IRRunMemCheck);
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CMP(R0, Operand2(0));
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B_CC(CC_NEQ, dispatcherCheckCoreState_);
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}
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} else {
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uint32_t checkedPC = lastConstPC_ + inst.dest;
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int size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);
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if (size == 0) {
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checkedPC += 4;
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size = MIPSAnalyst::OpMemoryAccessSize(checkedPC);
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}
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bool isWrite = MIPSAnalyst::IsOpMemoryWrite(checkedPC);
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const auto memchecks = g_breakpoints.GetMemCheckRanges(isWrite);
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// We can trivially skip if there are no checks for this type (i.e. read vs write.)
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if (memchecks.empty())
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break;
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// We need to flush, or conditions and log expressions will see old register values.
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// The flush may use SCRATCH1, so read the address after it. R12 is free after it too.
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FlushAll();
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LDR(SCRATCH1, CTXREG, inst.src1 * 4);
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ADDI2R(SCRATCH1, SCRATCH1, inst.constant, SCRATCH2);
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std::vector<FixupBranch> hitChecks;
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for (auto it : memchecks) {
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if (it.end != 0) {
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// A hit when start - size < addr < end, as an unsigned range check.
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uint32_t lo = it.start - size + 1;
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SUBI2R(R12, SCRATCH1, lo, SCRATCH2);
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CMPI2R(R12, it.end - lo, SCRATCH2);
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hitChecks.push_back(B_CC(CC_LO));
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} else {
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CMPI2R(SCRATCH1, it.start, SCRATCH2);
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hitChecks.push_back(B_CC(CC_EQ));
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}
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}
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FixupBranch noHits = B();
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// Okay, now land any hit here.
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for (auto &fixup : hitChecks)
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SetJumpTarget(fixup);
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hitChecks.clear();
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MOV(R1, SCRATCH1);
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MOVI2R(R0, checkedPC);
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QuickCallFunction(R12, &IRRunMemCheck);
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CMP(R0, Operand2(0));
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B_CC(CC_NEQ, dispatcherCheckCoreState_);
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SetJumpTarget(noHits);
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}
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void ArmJitBackend::CompIR_System(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::Syscall:
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FlushAll();
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SaveStaticRegisters();
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WriteDebugProfilerStatus(IRProfilerStatus::SYSCALL);
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#ifdef USE_PROFILER
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// When profiling, we can't skip CallSyscall, since it times syscalls.
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MOVI2R(R0, inst.constant);
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QuickCallFunction(R12, &CallSyscall);
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#else
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// Skip the CallSyscall where possible.
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{
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MIPSOpcode op(inst.constant);
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const HLEFunction *func = GetSyscallFunctionData(op, 0);
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if (func) {
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void *quickFunc = GetQuickSyscallFunc(func, op);
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if (quickFunc) {
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MOVP2R(R0, func);
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QuickCallFunction(R12, (const u8 *)quickFunc);
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} else {
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MOVI2R(R0, inst.constant);
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QuickCallFunction(R12, &CallSyscall);
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}
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} else {
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// Shouldn't get here.
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MOVI2R(R0, 0);
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QuickCallFunction(R12, &CallSyscallUnresolvedAtPC);
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}
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}
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#endif
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WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);
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LoadStaticRegisters();
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// This is always followed by an ExitToPC, where we check coreState.
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break;
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case IROp::SyscallUnresolved:
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FlushAll();
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SaveStaticRegisters();
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WriteDebugProfilerStatus(IRProfilerStatus::SYSCALL);
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MOVI2R(R0, inst.constant);
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QuickCallFunction(R12, &CallSyscallUnresolvedAtPC);
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WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);
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LoadStaticRegisters();
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break;
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case IROp::CallReplacement:
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FlushAll();
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SaveStaticRegisters();
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WriteDebugProfilerStatus(IRProfilerStatus::REPLACEMENT);
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QuickCallFunction(R12, GetReplacementFunc(inst.constant)->replaceFunc);
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WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT);
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LoadStaticRegisters();
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// Absolute value the result and subtract.
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CMP(R0, Operand2(0));
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SetCC(CC_MI);
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RSB(SCRATCH2, R0, Operand2(0));
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SetCC(CC_PL);
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MOV(SCRATCH2, R0);
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SetCC(CC_AL);
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SUB(DOWNCOUNTREG, DOWNCOUNTREG, SCRATCH2);
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// Everything was flushed, so this can't touch R0.
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// Set dest reg to the sign of the result.
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regs_.Map(inst);
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ASR(regs_.R(inst.dest), R0, 31);
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break;
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case IROp::Break:
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FlushAll();
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// This doesn't naturally have restore/apply around it.
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RestoreRoundingMode(true);
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SaveStaticRegisters();
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MovFromPC(R0);
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QuickCallFunction(R12, &Core_BreakException);
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LoadStaticRegisters();
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ApplyRoundingMode(true);
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MovFromPC(SCRATCH1);
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ADDI2R(SCRATCH1, SCRATCH1, 4, SCRATCH2);
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B(dispatcherPCInSCRATCH1_);
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void ArmJitBackend::CompIR_Transfer(IRInst inst) {
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CONDITIONAL_DISABLE;
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switch (inst.op) {
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case IROp::SetCtrlVFPU:
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regs_.SetGPRImm(IRREG_VFPU_CTRL_BASE + inst.dest, inst.constant);
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break;
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case IROp::SetCtrlVFPUReg:
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regs_.Map(inst);
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MOV(regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.R(inst.src1));
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break;
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case IROp::SetCtrlVFPUFReg:
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regs_.Map(inst);
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VMOV(regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.F(inst.src1));
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break;
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case IROp::FpCondFromReg:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });
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MOV(regs_.R(IRREG_FPCOND), regs_.R(inst.src1));
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break;
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case IROp::FpCondToReg:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::INIT } });
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MOV(regs_.R(inst.dest), regs_.R(IRREG_FPCOND));
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break;
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case IROp::FpCtrlFromReg:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } });
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ANDI2R(SCRATCH1, regs_.R(inst.src1), 0x0181FFFF, SCRATCH2);
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// Extract the new fpcond value.
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UBFX(regs_.R(IRREG_FPCOND), SCRATCH1, 23, 1);
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STR(SCRATCH1, CTXREG, IRREG_FCR31 * 4);
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break;
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case IROp::FpCtrlToReg:
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regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::INIT } });
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// Load fcr31 and clear the fpcond bit.
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LDR(regs_.R(inst.dest), CTXREG, IRREG_FCR31 * 4);
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BFI(regs_.R(inst.dest), regs_.R(IRREG_FPCOND), 23, 1);
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// Also update mips->fcr31 while we're here.
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STR(regs_.R(inst.dest), CTXREG, IRREG_FCR31 * 4);
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break;
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case IROp::VfpuCtrlToReg:
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regs_.Map(inst);
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MOV(regs_.R(inst.dest), regs_.R(IRREG_VFPU_CTRL_BASE + inst.src1));
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break;
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case IROp::FMovFromGPR:
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if (regs_.IsGPRImm(inst.src1) && regs_.GetGPRImm(inst.src1) == 0) {
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regs_.MapFPR(inst.dest, MIPSMap::NOINIT);
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MOVI2F(regs_.F(inst.dest), 0.0f, SCRATCH1);
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} else {
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regs_.Map(inst);
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VMOV(regs_.F(inst.dest), regs_.R(inst.src1));
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}
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break;
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case IROp::FMovToGPR:
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regs_.Map(inst);
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VMOV(regs_.R(inst.dest), regs_.F(inst.src1));
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break;
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default:
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INVALIDOP;
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break;
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}
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}
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void ArmJitBackend::CompIR_ValidateAddress(IRInst inst) {
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CONDITIONAL_DISABLE;
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bool isWrite = inst.src2 & 1;
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int alignment = 0;
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switch (inst.op) {
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case IROp::ValidateAddress8:
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alignment = 1;
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break;
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case IROp::ValidateAddress16:
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alignment = 2;
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break;
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case IROp::ValidateAddress32:
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alignment = 4;
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break;
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case IROp::ValidateAddress128:
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alignment = 16;
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break;
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default:
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INVALIDOP;
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break;
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}
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regs_.Map(inst);
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ADDI2R(SCRATCH1, regs_.R(inst.src1), inst.constant, SCRATCH2);
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BIC(SCRATCH1, SCRATCH1, Operand2(0xC0, 4));
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std::vector<FixupBranch> validJumps;
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FixupBranch unaligned;
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if (alignment != 1) {
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TST(SCRATCH1, Operand2(alignment - 1));
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unaligned = B_CC(CC_NEQ);
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}
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CMPI2R(SCRATCH1, PSP_GetUserMemoryEnd() - alignment, SCRATCH2);
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FixupBranch tooHighRAM = B_CC(CC_HI);
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CMPI2R(SCRATCH1, PSP_GetKernelMemoryBase(), SCRATCH2);
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validJumps.push_back(B_CC(CC_HS));
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CMPI2R(SCRATCH1, PSP_GetVidMemEnd() - alignment, SCRATCH2);
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FixupBranch tooHighVid = B_CC(CC_HI);
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CMPI2R(SCRATCH1, PSP_GetVidMemBase(), SCRATCH2);
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validJumps.push_back(B_CC(CC_HS));
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CMPI2R(SCRATCH1, PSP_GetScratchpadMemoryEnd() - alignment, SCRATCH2);
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FixupBranch tooHighScratch = B_CC(CC_HI);
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CMPI2R(SCRATCH1, PSP_GetScratchpadMemoryBase(), SCRATCH2);
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validJumps.push_back(B_CC(CC_HS));
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if (alignment != 1)
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SetJumpTarget(unaligned);
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SetJumpTarget(tooHighRAM);
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SetJumpTarget(tooHighVid);
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SetJumpTarget(tooHighScratch);
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// If we got here, something unusual and bad happened, so we'll always go back to the dispatcher.
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// Because of that, we can avoid flushing outside this case. The flush may use SCRATCH1, so the
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// address waits on the stack (two regs, to keep it aligned for the call).
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PUSH(2, SCRATCH1, SCRATCH2);
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auto regsCopy = regs_;
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regsCopy.FlushAll();
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POP(2, SCRATCH1, SCRATCH2);
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// Ignores the return value, always returns to the dispatcher.
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// Otherwise would need a thunk to restore regs.
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MOVI2R(R1, alignment);
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MOVI2R(R2, isWrite ? 1 : 0);
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QuickCallFunction(R12, &ReportBadAddress);
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B(dispatcherCheckCoreState_);
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for (FixupBranch &b : validJumps)
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SetJumpTarget(b);
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}
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} // namespace MIPSComp
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#endif
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