From 8c036a889dab62853abe0c14f221546803a07c09 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sun, 13 Aug 2023 09:28:06 -0700 Subject: [PATCH 1/2] riscv: Add debug log of block disasm. --- Core/MIPS/RiscV/RiscVJit.cpp | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Core/MIPS/RiscV/RiscVJit.cpp b/Core/MIPS/RiscV/RiscVJit.cpp index 12477669ef..df77206711 100644 --- a/Core/MIPS/RiscV/RiscVJit.cpp +++ b/Core/MIPS/RiscV/RiscVJit.cpp @@ -15,6 +15,8 @@ // Official git repository and contact information can be found at // https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. +#include +#include "ext/riscv-disas.h" #include "Core/MemMap.h" #include "Core/MIPS/MIPSTables.h" #include "Core/MIPS/RiscV/RiscVJit.h" @@ -29,6 +31,9 @@ using namespace RiscVJitConstants; static constexpr int MIN_BLOCK_NORMAL_LEN = 16; static constexpr int MIN_BLOCK_EXIT_LEN = 8; +// Use this if you want to check a specific block (correlates IR) or -1 for all. +static constexpr uint32_t disasmBlockAddr = 0; + RiscVJitBackend::RiscVJitBackend(MIPSState *mipsState, JitOptions &jitopt, IRBlockCache &blocks) : IRNativeBackend(blocks), jo(jitopt), gpr(mipsState, &jo), fpr(mipsState, &jo) { // Automatically disable incompatible options. @@ -77,10 +82,15 @@ bool RiscVJitBackend::CompileBlock(IRBlock *block, int block_num, bool preload) gpr.Start(block); fpr.Start(block); + // Used only for disasmBlockAddr. + std::map addresses; for (int i = 0; i < block->GetNumInstructions(); ++i) { const IRInst &inst = block->GetInstructions()[i]; gpr.SetIRIndex(i); fpr.SetIRIndex(i); + if constexpr (disasmBlockAddr != 0) { + addresses[GetCodePtr()] = inst; + } CompileIRInst(inst); @@ -127,6 +137,28 @@ bool RiscVJitBackend::CompileBlock(IRBlock *block, int block_num, bool preload) QuickJ(R_RA, outerLoopPCInSCRATCH1_); } + if (disasmBlockAddr == -1 || disasmBlockAddr == startPC) { + INFO_LOG(JIT, "== RISCV =="); + INFO_LOG(JIT, "=============== RISCV (%d bytes) ===============", len); + for (const u8 *p = blockStart; p < GetCodePointer(); ) { + char temp[512]; + rv_inst inst; + size_t len; + + auto it = addresses.find(p); + if (it != addresses.end()) { + DisassembleIR(temp, sizeof(temp), it->second); + INFO_LOG(JIT, "IR: # %s", temp); + } + + riscv_inst_fetch(p, &inst, &len); + riscv_disasm_inst(temp, sizeof(temp), rv64, (uintptr_t)p, inst); + p += len; + + INFO_LOG(JIT, "RV: %s", temp); + } + } + FlushIcache(); compilingBlockNum_ = -1; From 2bb67db43cc94555def5838661ad896c4a00468c Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sun, 13 Aug 2023 10:37:21 -0700 Subject: [PATCH 2/2] riscv: Switch to the logBlocks model for disasm. --- Core/MIPS/RiscV/RiscVJit.cpp | 13 +++++-------- Core/MIPS/RiscV/RiscVJit.h | 1 + 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/Core/MIPS/RiscV/RiscVJit.cpp b/Core/MIPS/RiscV/RiscVJit.cpp index df77206711..1c71239fe8 100644 --- a/Core/MIPS/RiscV/RiscVJit.cpp +++ b/Core/MIPS/RiscV/RiscVJit.cpp @@ -31,9 +31,6 @@ using namespace RiscVJitConstants; static constexpr int MIN_BLOCK_NORMAL_LEN = 16; static constexpr int MIN_BLOCK_EXIT_LEN = 8; -// Use this if you want to check a specific block (correlates IR) or -1 for all. -static constexpr uint32_t disasmBlockAddr = 0; - RiscVJitBackend::RiscVJitBackend(MIPSState *mipsState, JitOptions &jitopt, IRBlockCache &blocks) : IRNativeBackend(blocks), jo(jitopt), gpr(mipsState, &jo), fpr(mipsState, &jo) { // Automatically disable incompatible options. @@ -82,15 +79,13 @@ bool RiscVJitBackend::CompileBlock(IRBlock *block, int block_num, bool preload) gpr.Start(block); fpr.Start(block); - // Used only for disasmBlockAddr. std::map addresses; for (int i = 0; i < block->GetNumInstructions(); ++i) { const IRInst &inst = block->GetInstructions()[i]; gpr.SetIRIndex(i); fpr.SetIRIndex(i); - if constexpr (disasmBlockAddr != 0) { - addresses[GetCodePtr()] = inst; - } + // TODO: This might be a little wasteful when compiling if we're not debugging jit... + addresses[GetCodePtr()] = inst; CompileIRInst(inst); @@ -137,7 +132,9 @@ bool RiscVJitBackend::CompileBlock(IRBlock *block, int block_num, bool preload) QuickJ(R_RA, outerLoopPCInSCRATCH1_); } - if (disasmBlockAddr == -1 || disasmBlockAddr == startPC) { + if (logBlocks_ > 0) { + --logBlocks_; + INFO_LOG(JIT, "== RISCV =="); INFO_LOG(JIT, "=============== RISCV (%d bytes) ===============", len); for (const u8 *p = blockStart; p < GetCodePointer(); ) { diff --git a/Core/MIPS/RiscV/RiscVJit.h b/Core/MIPS/RiscV/RiscVJit.h index 69ed6fb3a0..d8bba616ad 100644 --- a/Core/MIPS/RiscV/RiscVJit.h +++ b/Core/MIPS/RiscV/RiscVJit.h @@ -127,6 +127,7 @@ private: int jitStartOffset_ = 0; int compilingBlockNum_ = -1; + int logBlocks_ = 0; }; class RiscVJit : public IRNativeJit {