diff --git a/Core/MIPS/RiscV/RiscVJit.cpp b/Core/MIPS/RiscV/RiscVJit.cpp
index 12477669ef..1c71239fe8 100644
--- a/Core/MIPS/RiscV/RiscVJit.cpp
+++ b/Core/MIPS/RiscV/RiscVJit.cpp
@@ -15,6 +15,8 @@
 // Official git repository and contact information can be found at
 // https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
 
+#include <cstddef>
+#include "ext/riscv-disas.h"
 #include "Core/MemMap.h"
 #include "Core/MIPS/MIPSTables.h"
 #include "Core/MIPS/RiscV/RiscVJit.h"
@@ -77,10 +79,13 @@ bool RiscVJitBackend::CompileBlock(IRBlock *block, int block_num, bool preload)
 	gpr.Start(block);
 	fpr.Start(block);
 
+	std::map<const u8 *, IRInst> addresses;
 	for (int i = 0; i < block->GetNumInstructions(); ++i) {
 		const IRInst &inst = block->GetInstructions()[i];
 		gpr.SetIRIndex(i);
 		fpr.SetIRIndex(i);
+		// TODO: This might be a little wasteful when compiling if we're not debugging jit...
+		addresses[GetCodePtr()] = inst;
 
 		CompileIRInst(inst);
 
@@ -127,6 +132,30 @@ bool RiscVJitBackend::CompileBlock(IRBlock *block, int block_num, bool preload)
 		QuickJ(R_RA, outerLoopPCInSCRATCH1_);
 	}
 
+	if (logBlocks_ > 0) {
+		--logBlocks_;
+
+		INFO_LOG(JIT, "== RISCV ==");
+		INFO_LOG(JIT, "=============== RISCV (%d bytes) ===============", len);
+		for (const u8 *p = blockStart; p < GetCodePointer(); ) {
+			char temp[512];
+			rv_inst inst;
+			size_t len;
+
+			auto it = addresses.find(p);
+			if (it != addresses.end()) {
+				DisassembleIR(temp, sizeof(temp), it->second);
+				INFO_LOG(JIT, "IR: # %s", temp);
+			}
+
+			riscv_inst_fetch(p, &inst, &len);
+			riscv_disasm_inst(temp, sizeof(temp), rv64, (uintptr_t)p, inst);
+			p += len;
+
+			INFO_LOG(JIT, "RV: %s", temp);
+		}
+	}
+
 	FlushIcache();
 	compilingBlockNum_ = -1;
 
diff --git a/Core/MIPS/RiscV/RiscVJit.h b/Core/MIPS/RiscV/RiscVJit.h
index 69ed6fb3a0..d8bba616ad 100644
--- a/Core/MIPS/RiscV/RiscVJit.h
+++ b/Core/MIPS/RiscV/RiscVJit.h
@@ -127,6 +127,7 @@ private:
 
 	int jitStartOffset_ = 0;
 	int compilingBlockNum_ = -1;
+	int logBlocks_ = 0;
 };
 
 class RiscVJit : public IRNativeJit {