diff --git a/Common/ColorConv.cpp b/Common/ColorConv.cpp index a9628207e4..449dd7b7f5 100644 --- a/Common/ColorConv.cpp +++ b/Common/ColorConv.cpp @@ -489,7 +489,7 @@ void ConvertRGBA5551ToBGRA8888(u32 *dst, const u16 *src, u32 numPixels) { u32 g = Convert5To8((c >> 5) & 0x001f); u32 b = Convert5To8((c >> 10) & 0x001f); // We force an arithmetic shift to get the sign bits. - u32 a = SignExtend16To32(c) & 0xff000000; + u32 a = SignExtend16ToU32(c) & 0xff000000; dst[x] = a | (r << 16) | (g << 8) | b; } diff --git a/Common/Data/Convert/SmallDataConvert.h b/Common/Data/Convert/SmallDataConvert.h index 953f596f53..ac31d5116f 100644 --- a/Common/Data/Convert/SmallDataConvert.h +++ b/Common/Data/Convert/SmallDataConvert.h @@ -181,15 +181,21 @@ inline uint32_t BytesToUint32(uint8_t a, uint8_t b, uint8_t c, uint8_t d) { return (a) | (b << 8) | (c << 16) | (d << 24); } -constexpr uint32_t SignExtend8To32(uint32_t value) { +constexpr int32_t SignExtend8ToS32(uint32_t value) { // This extends this sign at the 8th bit to the other 24 bits. - int32_t signedValue = (int8_t)(value & 0xFF); - // We return as unsigned because we're likely just interested in the bits. - return (uint32_t)signedValue; + return (int8_t)(value & 0xFF); } -constexpr uint32_t SignExtend16To32(uint32_t value) { - // Same as SignExtend8to32, but from the 16th bit. - int32_t signedValue = (int16_t)(value & 0xFFFF); - return (uint32_t)signedValue; +constexpr uint32_t SignExtend8ToU32(uint32_t value) { + // Just treat the bits as unsigned. + return (uint32_t)SignExtend8ToS32(value); +} + +constexpr int32_t SignExtend16ToS32(uint32_t value) { + // Same as SignExtend8toS32, but from the 16th bit. + return (int16_t)(value & 0xFFFF); +} + +constexpr uint32_t SignExtend16ToU32(uint32_t value) { + return (uint32_t)SignExtend16ToS32(value); } diff --git a/Core/HLE/sceKernelModule.cpp b/Core/HLE/sceKernelModule.cpp index 46f64d23ce..5ea2a721c1 100644 --- a/Core/HLE/sceKernelModule.cpp +++ b/Core/HLE/sceKernelModule.cpp @@ -626,7 +626,7 @@ static void WriteVarSymbol(WriteVarSymbolState &state, u32 exportAddress, u32 re case R_MIPS_LO16: { // Sign extend the existing low value (e.g. from addiu.) - const u32 offsetLo = SignExtend16To32(relocData); + const u32 offsetLo = SignExtend16ToU32(relocData); u32 full = exportAddress; // This is only used in the error case (no hi/wrong hi.) if (!reverse) { diff --git a/Core/MIPS/ARM/ArmCompALU.cpp b/Core/MIPS/ARM/ArmCompALU.cpp index 18ea66a6d6..0b5bf067f8 100644 --- a/Core/MIPS/ARM/ArmCompALU.cpp +++ b/Core/MIPS/ARM/ArmCompALU.cpp @@ -77,8 +77,8 @@ namespace MIPSComp { CONDITIONAL_DISABLE(ALU_IMM); u32 uimm = op & 0xFFFF; - u32 suimm = SignExtend16To32(op); - s32 simm = (s32)suimm; + s32 simm = SignExtend16ToS32(op); + u32 suimm = SignExtend16ToU32(op); MIPSGPReg rt = _RT; MIPSGPReg rs = _RS; @@ -602,9 +602,9 @@ namespace MIPSComp return; switch ((op >> 6) & 31) { - case 16: // seb // R(rd) = SignExtend8To32(R(rt)); + case 16: // seb // R(rd) = SignExtend8ToU32(R(rt)); if (gpr.IsImm(rt)) { - gpr.SetImm(rd, SignExtend8To32(gpr.GetImm(rt))); + gpr.SetImm(rd, SignExtend8ToU32(gpr.GetImm(rt))); return; } gpr.MapDirtyIn(rd, rt); @@ -613,7 +613,7 @@ namespace MIPSComp case 24: // seh if (gpr.IsImm(rt)) { - gpr.SetImm(rd, SignExtend16To32(gpr.GetImm(rt))); + gpr.SetImm(rd, SignExtend16ToU32(gpr.GetImm(rt))); return; } gpr.MapDirtyIn(rd, rt); diff --git a/Core/MIPS/ARM/ArmCompBranch.cpp b/Core/MIPS/ARM/ArmCompBranch.cpp index da2300d5f7..b894bc6ea7 100644 --- a/Core/MIPS/ARM/ArmCompBranch.cpp +++ b/Core/MIPS/ARM/ArmCompBranch.cpp @@ -49,7 +49,7 @@ #define _POS ((op>> 6) & 0x1F) #define _SIZE ((op>>11) & 0x1F) #define _IMM26 (op & 0x03FFFFFF) -#define TARGET16 ((int)(SignExtend16To32(op) << 2)) +#define TARGET16 ((int)(SignExtend16ToU32(op) << 2)) #define TARGET26 (_IMM26 << 2) #define LOOPOPTIMIZATION 0 diff --git a/Core/MIPS/ARM/ArmCompVFPU.cpp b/Core/MIPS/ARM/ArmCompVFPU.cpp index 46a9e3c075..d9056c8238 100644 --- a/Core/MIPS/ARM/ArmCompVFPU.cpp +++ b/Core/MIPS/ARM/ArmCompVFPU.cpp @@ -2088,7 +2088,7 @@ namespace MIPSComp u8 dreg; GetVectorRegs(&dreg, V_Single, _VT); - s32 imm = (s32)SignExtend16To32(op); + s32 imm = SignExtend16ToS32(op); fpr.MapRegV(dreg, MAP_DIRTY | MAP_NOINIT); MOVI2F(fpr.V(dreg), (float)imm, SCRATCHREG1); diff --git a/Core/MIPS/ARM/ArmCompVFPUNEON.cpp b/Core/MIPS/ARM/ArmCompVFPUNEON.cpp index bd680b0a2a..f11f1c503d 100644 --- a/Core/MIPS/ARM/ArmCompVFPUNEON.cpp +++ b/Core/MIPS/ARM/ArmCompVFPUNEON.cpp @@ -1348,7 +1348,7 @@ void ArmJit::CompNEON_Viim(MIPSOpcode op) { DestARMReg vt = NEONMapPrefixD(_VT, V_Single, MAP_NOINIT | MAP_DIRTY); - s32 imm = (s32)SignExtend16To32(op); + s32 imm = SignExtend16ToS32(op); // TODO: Optimize for low registers. MOVI2F(S0, (float)imm, R0); VMOV_neon(vt.rd, D0); diff --git a/Core/MIPS/ARM64/Arm64CompALU.cpp b/Core/MIPS/ARM64/Arm64CompALU.cpp index 3ac0e9f6ac..afb8d2b4a8 100644 --- a/Core/MIPS/ARM64/Arm64CompALU.cpp +++ b/Core/MIPS/ARM64/Arm64CompALU.cpp @@ -74,8 +74,8 @@ void Arm64Jit::CompImmLogic(MIPSGPReg rs, MIPSGPReg rt, u32 uimm, void (ARM64XEm void Arm64Jit::Comp_IType(MIPSOpcode op) { CONDITIONAL_DISABLE(ALU_IMM); u32 uimm = op & 0xFFFF; - u32 suimm = SignExtend16To32(op); - s32 simm = (s32)suimm; + s32 simm = SignExtend16ToS32(op); + u32 suimm = SignExtend16ToU32(op); MIPSGPReg rt = _RT; MIPSGPReg rs = _RS; @@ -489,9 +489,9 @@ void Arm64Jit::Comp_Allegrex(MIPSOpcode op) { return; switch ((op >> 6) & 31) { - case 16: // seb // R(rd) = SignExtend8To32(R(rt)); + case 16: // seb // R(rd) = SignExtend8ToU32(R(rt)); if (gpr.IsImm(rt)) { - gpr.SetImm(rd, SignExtend8To32(gpr.GetImm(rt))); + gpr.SetImm(rd, SignExtend8ToU32(gpr.GetImm(rt))); return; } gpr.MapDirtyIn(rd, rt); @@ -500,7 +500,7 @@ void Arm64Jit::Comp_Allegrex(MIPSOpcode op) { case 24: // seh if (gpr.IsImm(rt)) { - gpr.SetImm(rd, SignExtend16To32(gpr.GetImm(rt))); + gpr.SetImm(rd, SignExtend16ToU32(gpr.GetImm(rt))); return; } gpr.MapDirtyIn(rd, rt); diff --git a/Core/MIPS/ARM64/Arm64CompBranch.cpp b/Core/MIPS/ARM64/Arm64CompBranch.cpp index 42ca60750a..6229e5fec8 100644 --- a/Core/MIPS/ARM64/Arm64CompBranch.cpp +++ b/Core/MIPS/ARM64/Arm64CompBranch.cpp @@ -49,7 +49,7 @@ #define _POS ((op>> 6) & 0x1F) #define _SIZE ((op>>11) & 0x1F) #define _IMM26 (op & 0x03FFFFFF) -#define TARGET16 ((int)(SignExtend16To32(op) << 2)) +#define TARGET16 ((int)(SignExtend16ToU32(op) << 2)) #define TARGET26 (_IMM26 << 2) #define LOOPOPTIMIZATION 0 diff --git a/Core/MIPS/ARM64/Arm64CompVFPU.cpp b/Core/MIPS/ARM64/Arm64CompVFPU.cpp index 4bc27fce91..1307baee29 100644 --- a/Core/MIPS/ARM64/Arm64CompVFPU.cpp +++ b/Core/MIPS/ARM64/Arm64CompVFPU.cpp @@ -1812,7 +1812,7 @@ namespace MIPSComp { u8 dreg; GetVectorRegs(&dreg, V_Single, _VT); - s32 imm = (s32)SignExtend16To32(op); + s32 imm = SignExtend16ToS32(op); fpr.MapRegV(dreg, MAP_DIRTY | MAP_NOINIT); fp.MOVI2F(fpr.V(dreg), (float)imm, SCRATCH1); diff --git a/Core/MIPS/IR/IRCompALU.cpp b/Core/MIPS/IR/IRCompALU.cpp index 6a987cc374..62d813f3b2 100644 --- a/Core/MIPS/IR/IRCompALU.cpp +++ b/Core/MIPS/IR/IRCompALU.cpp @@ -47,9 +47,9 @@ namespace MIPSComp { void IRFrontend::Comp_IType(MIPSOpcode op) { CONDITIONAL_DISABLE(ALU_IMM); - s32 simm = (s32)_IMM16; // sign extension u32 uimm = (u16)_IMM16; - u32 suimm = (u32)(s32)simm; + s32 simm = SignExtend16ToS32(op); + u32 suimm = SignExtend16ToU32(op); MIPSGPReg rt = _RT; MIPSGPReg rs = _RS; @@ -274,7 +274,7 @@ void IRFrontend::Comp_Allegrex(MIPSOpcode op) { return; switch ((op >> 6) & 31) { - case 16: // seb // R(rd) = SignExtend8To32(R(rt)); + case 16: // seb // R(rd) = SignExtend8ToU32(R(rt)); ir.Write(IROp::Ext8to32, rd, rt); break; diff --git a/Core/MIPS/IR/IRCompBranch.cpp b/Core/MIPS/IR/IRCompBranch.cpp index c60cf549b0..0f8bbc4ff2 100644 --- a/Core/MIPS/IR/IRCompBranch.cpp +++ b/Core/MIPS/IR/IRCompBranch.cpp @@ -42,7 +42,7 @@ #define _POS ((op>> 6) & 0x1F) #define _SIZE ((op>>11) & 0x1F) #define _IMM26 (op & 0x03FFFFFF) -#define TARGET16 ((int)(SignExtend16To32(op) << 2)) +#define TARGET16 ((int)(SignExtend16ToU32(op) << 2)) #define TARGET26 (_IMM26 << 2) #define LOOPOPTIMIZATION 0 diff --git a/Core/MIPS/IR/IRCompVFPU.cpp b/Core/MIPS/IR/IRCompVFPU.cpp index ddccf33e1b..b201048c9a 100644 --- a/Core/MIPS/IR/IRCompVFPU.cpp +++ b/Core/MIPS/IR/IRCompVFPU.cpp @@ -1778,7 +1778,7 @@ namespace MIPSComp { // Vector integer immediate // d[0] = float(imm) - s32 imm = (s32)SignExtend16To32(op); + s32 imm = SignExtend16ToS32(op); u8 dreg; GetVectorRegsPrefixD(&dreg, V_Single, _VT); ir.Write(IROp::SetConstF, dreg, ir.AddConstantFloat((float)imm)); diff --git a/Core/MIPS/IR/IRInterpreter.cpp b/Core/MIPS/IR/IRInterpreter.cpp index bf01b2d80d..6bae2b74c3 100644 --- a/Core/MIPS/IR/IRInterpreter.cpp +++ b/Core/MIPS/IR/IRInterpreter.cpp @@ -127,10 +127,10 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) { mips->r[inst->dest] = ~mips->r[inst->src1]; break; case IROp::Ext8to32: - mips->r[inst->dest] = SignExtend8To32(mips->r[inst->src1]); + mips->r[inst->dest] = SignExtend8ToU32(mips->r[inst->src1]); break; case IROp::Ext16to32: - mips->r[inst->dest] = SignExtend16To32(mips->r[inst->src1]); + mips->r[inst->dest] = SignExtend16ToU32(mips->r[inst->src1]); break; case IROp::ReverseBits: mips->r[inst->dest] = ReverseBits32(mips->r[inst->src1]); @@ -140,13 +140,13 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) { mips->r[inst->dest] = Memory::ReadUnchecked_U8(mips->r[inst->src1] + inst->constant); break; case IROp::Load8Ext: - mips->r[inst->dest] = SignExtend8To32(Memory::ReadUnchecked_U8(mips->r[inst->src1] + inst->constant)); + mips->r[inst->dest] = SignExtend8ToU32(Memory::ReadUnchecked_U8(mips->r[inst->src1] + inst->constant)); break; case IROp::Load16: mips->r[inst->dest] = Memory::ReadUnchecked_U16(mips->r[inst->src1] + inst->constant); break; case IROp::Load16Ext: - mips->r[inst->dest] = SignExtend16To32(Memory::ReadUnchecked_U16(mips->r[inst->src1] + inst->constant)); + mips->r[inst->dest] = SignExtend16ToU32(Memory::ReadUnchecked_U16(mips->r[inst->src1] + inst->constant)); break; case IROp::Load32: mips->r[inst->dest] = Memory::ReadUnchecked_U32(mips->r[inst->src1] + inst->constant); diff --git a/Core/MIPS/IR/IRPassSimplify.cpp b/Core/MIPS/IR/IRPassSimplify.cpp index 92dd6691d4..d96ad364f2 100644 --- a/Core/MIPS/IR/IRPassSimplify.cpp +++ b/Core/MIPS/IR/IRPassSimplify.cpp @@ -37,8 +37,8 @@ u32 Evaluate(u32 a, IROp op) { case IROp::Neg: return -(s32)a; case IROp::BSwap16: return ((a & 0xFF00FF00) >> 8) | ((a & 0x00FF00FF) << 8); case IROp::BSwap32: return swap32(a); - case IROp::Ext8to32: return SignExtend8To32(a); - case IROp::Ext16to32: return SignExtend16To32(a); + case IROp::Ext8to32: return SignExtend8ToU32(a); + case IROp::Ext16to32: return SignExtend16ToU32(a); case IROp::ReverseBits: return ReverseBits32(a); case IROp::Clz: { int x = 31; diff --git a/Core/MIPS/MIPSCodeUtils.cpp b/Core/MIPS/MIPSCodeUtils.cpp index 5f1253ee0a..faf620d5b1 100644 --- a/Core/MIPS/MIPSCodeUtils.cpp +++ b/Core/MIPS/MIPSCodeUtils.cpp @@ -28,9 +28,8 @@ namespace MIPSCodeUtils #define OP_SYSCALL_MASK 0xFC00003F #define _RS ((op>>21) & 0x1F) #define _RT ((op>>16) & 0x1F) -#define _IMM16 (signed short)(op & 0xFFFF) #define _IMM26 (op & 0x03FFFFFF) -#define TARGET16 ((int)((uint32_t)(int)_IMM16 << 2)) +#define TARGET16 ((int)(SignExtend16ToU32(op) << 2)) #define TARGET26 (_IMM26 << 2) u32 GetJumpTarget(u32 addr) { diff --git a/Core/MIPS/MIPSCodeUtils.h b/Core/MIPS/MIPSCodeUtils.h index fab9aaa7b9..17789f72c7 100644 --- a/Core/MIPS/MIPSCodeUtils.h +++ b/Core/MIPS/MIPSCodeUtils.h @@ -53,12 +53,20 @@ #define MIPS_GET_VS(op) ((op>>8) & 0x7F) #define MIPS_GET_VT(op) ((op>>16) & 0x7F) -inline uint32_t SignExtend8To32(MIPSOpcode op) { - return SignExtend8To32(op.encoding); +inline int32_t SignExtend8ToS32(MIPSOpcode op) { + return SignExtend8ToS32(op.encoding); } -inline uint32_t SignExtend16To32(MIPSOpcode op) { - return SignExtend16To32(op.encoding); +inline uint32_t SignExtend8ToU32(MIPSOpcode op) { + return SignExtend8ToU32(op.encoding); +} + +inline int32_t SignExtend16ToS32(MIPSOpcode op) { + return SignExtend16ToS32(op.encoding); +} + +inline uint32_t SignExtend16ToU32(MIPSOpcode op) { + return SignExtend16ToU32(op.encoding); } namespace MIPSCodeUtils diff --git a/Core/MIPS/MIPSDis.cpp b/Core/MIPS/MIPSDis.cpp index 3750bc15c8..c1c61f6a9c 100644 --- a/Core/MIPS/MIPSDis.cpp +++ b/Core/MIPS/MIPSDis.cpp @@ -173,8 +173,8 @@ namespace MIPSDis void Dis_IType(MIPSOpcode op, char *out) { u32 uimm = op & 0xFFFF; - u32 suimm = SignExtend16To32(op); - s32 simm = (s32)suimm; + u32 suimm = SignExtend16ToU32(op); + s32 simm = SignExtend16ToS32(op); int rt = _RT; int rs = _RS; diff --git a/Core/MIPS/MIPSInt.cpp b/Core/MIPS/MIPSInt.cpp index 6c60ddbff3..fa6f9d19bd 100644 --- a/Core/MIPS/MIPSInt.cpp +++ b/Core/MIPS/MIPSInt.cpp @@ -298,8 +298,8 @@ namespace MIPSInt void Int_IType(MIPSOpcode op) { u32 uimm = op & 0xFFFF; - u32 suimm = SignExtend16To32(op); - s32 simm = (s32)suimm; + u32 suimm = SignExtend16ToU32(op); + s32 simm = SignExtend16ToS32(op); int rt = _RT; int rs = _RS; @@ -412,8 +412,8 @@ namespace MIPSInt switch (op >> 26) { - case 32: R(rt) = SignExtend8To32(Memory::Read_U8(addr)); break; //lb - case 33: R(rt) = SignExtend16To32(Memory::Read_U16(addr)); break; //lh + case 32: R(rt) = SignExtend8ToU32(Memory::Read_U8(addr)); break; //lb + case 33: R(rt) = SignExtend16ToU32(Memory::Read_U16(addr)); break; //lh case 35: R(rt) = Memory::Read_U32(addr); break; //lw case 36: R(rt) = Memory::Read_U8 (addr); break; //lbu case 37: R(rt) = Memory::Read_U16(addr); break; //lhu @@ -739,7 +739,7 @@ namespace MIPSInt switch((op>>6)&31) { case 16: // seb - R(rd) = SignExtend8To32(R(rt)); + R(rd) = SignExtend8ToU32(R(rt)); break; case 20: // bitrev @@ -757,7 +757,7 @@ namespace MIPSInt break; case 24: // seh - R(rd) = SignExtend16To32(R(rt)); + R(rd) = SignExtend16ToU32(R(rt)); break; default: diff --git a/Core/MIPS/x86/CompALU.cpp b/Core/MIPS/x86/CompALU.cpp index 61995792ba..37dd48101f 100644 --- a/Core/MIPS/x86/CompALU.cpp +++ b/Core/MIPS/x86/CompALU.cpp @@ -78,9 +78,9 @@ namespace MIPSComp void Jit::Comp_IType(MIPSOpcode op) { CONDITIONAL_DISABLE(ALU_IMM); - s32 simm = (s32)_IMM16; // sign extension u32 uimm = op & 0xFFFF; - u32 suimm = (u32)(s32)simm; + s32 simm = SignExtend16ToS32(op); + u32 suimm = SignExtend16ToU32(op); MIPSGPReg rt = _RT; MIPSGPReg rs = _RS; @@ -798,10 +798,10 @@ namespace MIPSComp switch ((op >> 6) & 31) { - case 16: // seb // R(rd) = SignExtend8To32(R(rt)); + case 16: // seb // R(rd) = SignExtend8ToU32(R(rt)); if (gpr.IsImm(rt)) { - gpr.SetImm(rd, SignExtend8To32(gpr.GetImm(rt))); + gpr.SetImm(rd, SignExtend8ToU32(gpr.GetImm(rt))); break; } @@ -876,10 +876,10 @@ namespace MIPSComp gpr.UnlockAll(); break; - case 24: // seh // R(rd) = SignExtend16To32(R(rt)); + case 24: // seh // R(rd) = SignExtend16ToU32(R(rt)); if (gpr.IsImm(rt)) { - gpr.SetImm(rd, SignExtend16To32(gpr.GetImm(rt))); + gpr.SetImm(rd, SignExtend16ToU32(gpr.GetImm(rt))); break; } diff --git a/Core/MIPS/x86/CompBranch.cpp b/Core/MIPS/x86/CompBranch.cpp index 7c3cdf326e..e7de2513f9 100644 --- a/Core/MIPS/x86/CompBranch.cpp +++ b/Core/MIPS/x86/CompBranch.cpp @@ -48,7 +48,7 @@ #define _POS ((op>> 6) & 0x1F) #define _SIZE ((op>>11) & 0x1F) #define _IMM26 (op & 0x03FFFFFF) -#define TARGET16 ((int)(SignExtend16To32(op) << 2)) +#define TARGET16 ((int)(SignExtend16ToU32(op) << 2)) #define TARGET26 (_IMM26 << 2) #define LOOPOPTIMIZATION 0 diff --git a/Core/MIPS/x86/CompLoadStore.cpp b/Core/MIPS/x86/CompLoadStore.cpp index 215e75797f..dcb18be225 100644 --- a/Core/MIPS/x86/CompLoadStore.cpp +++ b/Core/MIPS/x86/CompLoadStore.cpp @@ -309,11 +309,11 @@ namespace MIPSComp { CompITypeMemRead(op, 32, &XEmitter::MOVZX, safeMemFuncs.readU32); break; - case 32: //R(rt) = SignExtend8To32 (ReadMem8 (addr)); break; //lb + case 32: //R(rt) = SignExtend8ToU32 (ReadMem8 (addr)); break; //lb CompITypeMemRead(op, 8, &XEmitter::MOVSX, safeMemFuncs.readU8); break; - case 33: //R(rt) = SignExtend16To32(ReadMem16(addr)); break; //lh + case 33: //R(rt) = SignExtend16ToU32(ReadMem16(addr)); break; //lh CompITypeMemRead(op, 16, &XEmitter::MOVSX, safeMemFuncs.readU16); break; diff --git a/Core/MIPS/x86/CompVFPU.cpp b/Core/MIPS/x86/CompVFPU.cpp index 143d3f5a87..b661cbf5d1 100644 --- a/Core/MIPS/x86/CompVFPU.cpp +++ b/Core/MIPS/x86/CompVFPU.cpp @@ -3452,7 +3452,7 @@ void Jit::Comp_Viim(MIPSOpcode op) { // Flush SIMD. fpr.SimpleRegsV(&dreg, V_Single, MAP_NOINIT | MAP_DIRTY); - s32 imm = (s32)SignExtend16To32(op); + s32 imm = SignExtend16ToS32(op); FP32 fp; fp.f = (float)imm; MOV(32, R(TEMPREG), Imm32(fp.u));