From 5b507e5bb34ca030e4c2353b7d5c8ce4ab22d4fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Henrik=20Rydg=C3=A5rd?= Date: Tue, 22 Sep 2026 10:56:07 -0600 Subject: [PATCH] Add pspautotests for the div-by-zero, rounding, scaled convert and call-out JIT paths Covers the cases fixed on the riscv-loongarch-fixes branch, none of which the suite reached before. Five go in tests_good, and two in tests_next: - cpu/cpu_alu/cpu_div: hardware leaves HI = 0 for INT_MIN / -1. The x86 JIT, both interpreters and every IR backend set it to -1 on purpose; the classic arm64 JIT passes by not special-casing it at all. - cpu/vfpu/minmax_zero: signed zero and denormals in vmin/vmax. Co-Authored-By: Claude Fable 5.1 --- pspautotests | 2 +- test.py | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/pspautotests b/pspautotests index 830c78b5bd..257cfb5ad7 160000 --- a/pspautotests +++ b/pspautotests @@ -1 +1 @@ -Subproject commit 830c78b5bd2c0a21a02c0e4aed017d95f294e15f +Subproject commit 257cfb5ad77fe51d9c8d361fea4e0a9bfaf2026c diff --git a/test.py b/test.py index 01f5959d80..a820f38382 100755 --- a/test.py +++ b/test.py @@ -87,14 +87,18 @@ tests_good = [ "cpu/cpu_alu/cpu_alu", "cpu/cpu_alu/cpu_branch", "cpu/cpu_alu/cpu_branch2", + "cpu/vfpu/callout", "cpu/vfpu/colors", "cpu/vfpu/convert", + "cpu/vfpu/convert_scaled", + "cpu/vfpu/minmax", "cpu/vfpu/gum", "cpu/vfpu/matrix", "cpu/vfpu/vavg", "cpu/icache/icache", "cpu/lsu/lsu", "cpu/fpu/fpu", + "cpu/fpu/rounding", "audio/atrac/addstreamdata", "audio/atrac/atractest", @@ -263,6 +267,7 @@ tests_good = [ "malloc/malloc", "misc/dcache", "misc/deadbeef", + "modules/unresolved/unresolved", "misc/libc", "misc/sdkver", "misc/testgp", @@ -462,7 +467,9 @@ known_failures = { tests_next = [ # These are the next tests up for fixing. These run by default. + "cpu/cpu_alu/cpu_div", # INT_MIN / -1 leaves HI = 0 on hardware, the interpreters and IR backends say -1 "cpu/fpu/fcr", + "cpu/vfpu/minmax_zero", # signed zero and denormals in vmin/vmax "cpu/vfpu/prefixes", "cpu/vfpu/vector", "cpu/vfpu/vregs",