From 5a02ea9ff4891fb2c155d518bf274c020e2f6a5e Mon Sep 17 00:00:00 2001 From: Henrik Rydgard Date: Tue, 10 Dec 2013 13:26:32 +0100 Subject: [PATCH] Fix cache instruction on ARM --- Core/MIPS/ARM/ArmCompLoadStore.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/Core/MIPS/ARM/ArmCompLoadStore.cpp b/Core/MIPS/ARM/ArmCompLoadStore.cpp index 5e4be873c9..6a10aa31ca 100644 --- a/Core/MIPS/ARM/ArmCompLoadStore.cpp +++ b/Core/MIPS/ARM/ArmCompLoadStore.cpp @@ -385,8 +385,6 @@ namespace MIPSComp } void Jit::Comp_Cache(MIPSOpcode op) { - CONDITIONAL_DISABLE; - // TODO: Could use this as a hint, and technically required to handle icache, etc. - // But right now Int_Cache does nothing, so let's not even call it. + DISABLE; } }