diff --git a/CMakeLists.txt b/CMakeLists.txt
index a2fec3d2b4..7aeeb85377 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1612,7 +1612,10 @@ list(APPEND CoreExtra
Core/MIPS/RiscV/RiscVAsm.cpp
Core/MIPS/RiscV/RiscVJit.cpp
Core/MIPS/RiscV/RiscVJit.h
+ Core/MIPS/RiscV/RiscVRegCache.cpp
Core/MIPS/RiscV/RiscVRegCache.h
+ Core/MIPS/RiscV/RiscVRegCacheFPU.cpp
+ Core/MIPS/RiscV/RiscVRegCacheFPU.h
GPU/Common/VertexDecoderRiscV.cpp
)
diff --git a/Core/Core.vcxproj b/Core/Core.vcxproj
index 044a5c4830..fae61b7fbd 100644
--- a/Core/Core.vcxproj
+++ b/Core/Core.vcxproj
@@ -595,6 +595,8 @@
+
+
@@ -1165,6 +1167,7 @@
+
diff --git a/Core/Core.vcxproj.filters b/Core/Core.vcxproj.filters
index 5226d44737..910a58a806 100644
--- a/Core/Core.vcxproj.filters
+++ b/Core/Core.vcxproj.filters
@@ -1213,6 +1213,12 @@
MIPS\RiscV
+
+ MIPS\RiscV
+
+
+ MIPS\RiscV
+
@@ -1965,6 +1971,9 @@
MIPS\RiscV
+
+ MIPS\RiscV
+
diff --git a/Core/MIPS/RiscV/RiscVAsm.cpp b/Core/MIPS/RiscV/RiscVAsm.cpp
index 58420de286..77ab1238db 100644
--- a/Core/MIPS/RiscV/RiscVAsm.cpp
+++ b/Core/MIPS/RiscV/RiscVAsm.cpp
@@ -48,22 +48,21 @@ void RiscVJit::GenerateFixedCode(const JitOptions &jo) {
BeginWrite(GetMemoryProtectPageSize());
const u8 *start = AlignCodePage();
- // TODO
if (jo.useStaticAlloc) {
- //saveStaticRegisters = AlignCode16();
- //SW(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
- //gpr.EmitSaveStaticRegisters();
- //RET();
+ saveStaticRegisters_ = AlignCode16();
+ SW(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
+ gpr.EmitSaveStaticRegisters();
+ RET();
- //loadStaticRegisters = AlignCode16();
- //gpr.EmitLoadStaticRegisters();
- //LW(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
- //RET();
+ loadStaticRegisters_ = AlignCode16();
+ gpr.EmitLoadStaticRegisters();
+ LW(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
+ RET();
- //start = saveStaticRegisters;
+ start = saveStaticRegisters_;
} else {
- //saveStaticRegisters = nullptr;
- //loadStaticRegisters = nullptr;
+ saveStaticRegisters_ = nullptr;
+ loadStaticRegisters_ = nullptr;
}
// TODO: Do we actually need updateRoundingMode_? Hm.
diff --git a/Core/MIPS/RiscV/RiscVJit.cpp b/Core/MIPS/RiscV/RiscVJit.cpp
index 00ffdbf393..8f5608ac4e 100644
--- a/Core/MIPS/RiscV/RiscVJit.cpp
+++ b/Core/MIPS/RiscV/RiscVJit.cpp
@@ -28,7 +28,7 @@ using namespace RiscVJitConstants;
static constexpr int MAX_ALLOWED_JIT_BLOCKS = 262144;
-RiscVJit::RiscVJit(MIPSState *mipsState) : IRJit(mipsState) {
+RiscVJit::RiscVJit(MIPSState *mipsState) : IRJit(mipsState), gpr(mipsState, &jo) {
// Automatically disable incompatible options.
if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) {
jo.enablePointerify = false;
@@ -39,7 +39,8 @@ RiscVJit::RiscVJit(MIPSState *mipsState) : IRJit(mipsState) {
// TODO: Consider replacing block num method form IRJit - this is 2MB.
blockStartAddrs_ = new const u8 *[MAX_ALLOWED_JIT_BLOCKS];
- // TODO: gpr, fpr
+ gpr.Init(this);
+ // TODO: fpr
GenerateFixedCode(jo);
}
@@ -67,14 +68,16 @@ bool RiscVJit::CompileBlock(u32 em_address, std::vector &instructions, u
_assert_msg_(blockStartAddrs_[block_num] == nullptr, "Block reused before clear");
blockStartAddrs_[block_num] = GetCodePointer();
- // TODO: gpr, fpr.
+ gpr.Start();
+ // TODO: fpr.
+
for (const IRInst &inst : instructions) {
CompileIRInst(inst);
- // TODO
if (jo.Disabled(JitDisable::REGALLOC_GPR)) {
- //gpr.FlushAll();
+ gpr.FlushAll();
}
+ // TODO
if (jo.Disabled(JitDisable::REGALLOC_FPR)) {
//fpr.FlushAll();
}
@@ -107,6 +110,7 @@ void RiscVJit::CompileIRInst(IRInst inst) {
uint64_t value;
memcpy(&value, &inst, sizeof(inst));
+ FlushAll();
LI(X10, value, SCRATCH2);
SaveStaticRegisters();
QuickCallFunction(SCRATCH2, &DoIRInst);
@@ -123,6 +127,11 @@ void RiscVJit::CompileIRInst(IRInst inst) {
}
}
+void RiscVJit::FlushAll() {
+ gpr.FlushAll();
+ // TODO: fpr.
+}
+
bool RiscVJit::DescribeCodePtr(const u8 *ptr, std::string &name) {
// Used in disassembly viewer.
if (ptr == dispatcher_) {
@@ -131,6 +140,10 @@ bool RiscVJit::DescribeCodePtr(const u8 *ptr, std::string &name) {
name = "dispatcher (PC in SCRATCH1)";
} else if (ptr == dispatcherNoCheck_) {
name = "dispatcherNoCheck";
+ } else if (ptr == saveStaticRegisters_) {
+ name = "saveStaticRegisters";
+ } else if (ptr == loadStaticRegisters_) {
+ name = "loadStaticRegisters";
} else if (ptr == enterDispatcher_) {
name = "enterDispatcher";
} else if (!IsInSpace(ptr)) {
@@ -217,22 +230,20 @@ void RiscVJit::MovToPC(RiscVGen::RiscVReg r) {
}
void RiscVJit::SaveStaticRegisters() {
- // TODO
- //if (jo.useStaticAlloc) {
- // QuickCallFunction(SCRATCH2, saveStaticRegisters_);
- //} else {
+ if (jo.useStaticAlloc) {
+ QuickCallFunction(SCRATCH2, saveStaticRegisters_);
+ } else {
// Inline the single operation
SW(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
- //}
+ }
}
void RiscVJit::LoadStaticRegisters() {
- // TODO
- //if (jo.useStaticAlloc) {
- // QuickCallFunction(SCRATCH2, loadStaticRegisters_);
- //} else {
+ if (jo.useStaticAlloc) {
+ QuickCallFunction(SCRATCH2, loadStaticRegisters_);
+ } else {
LW(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount));
- //}
+ }
}
} // namespace MIPSComp
diff --git a/Core/MIPS/RiscV/RiscVJit.h b/Core/MIPS/RiscV/RiscVJit.h
index f51a66006a..13e4e6cf71 100644
--- a/Core/MIPS/RiscV/RiscVJit.h
+++ b/Core/MIPS/RiscV/RiscVJit.h
@@ -23,6 +23,7 @@
#include "Core/MIPS/IR/IRJit.h"
#include "Core/MIPS/JitCommon/JitState.h"
#include "Core/MIPS/JitCommon/JitCommon.h"
+#include "Core/MIPS/RiscV/RiscVRegCache.h"
namespace MIPSComp {
@@ -60,6 +61,10 @@ private:
void SaveStaticRegisters();
void LoadStaticRegisters();
+ void FlushAll();
+
+ RiscVRegCache gpr;
+
const u8 *enterDispatcher_ = nullptr;
const u8 *outerLoop_ = nullptr;
@@ -70,6 +75,9 @@ private:
const u8 *dispatcherNoCheck_ = nullptr;
const u8 *dispatcherFetch_ = nullptr;
+ const u8 *saveStaticRegisters_ = nullptr;
+ const u8 *loadStaticRegisters_ = nullptr;
+
const u8 *crashHandler_ = nullptr;
int jitStartOffset_ = 0;
diff --git a/Core/MIPS/RiscV/RiscVRegCache.cpp b/Core/MIPS/RiscV/RiscVRegCache.cpp
new file mode 100644
index 0000000000..20aff331fa
--- /dev/null
+++ b/Core/MIPS/RiscV/RiscVRegCache.cpp
@@ -0,0 +1,935 @@
+// Copyright (c) 2023- PPSSPP Project.
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, version 2.0 or later versions.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License 2.0 for more details.
+
+// A copy of the GPL 2.0 should have been included with the program.
+// If not, see http://www.gnu.org/licenses/
+
+// Official git repository and contact information can be found at
+// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
+
+#include "Core/MIPS/RiscV/RiscVRegCache.h"
+#include "Core/MIPS/JitCommon/JitState.h"
+#include "Core/Reporting.h"
+
+#ifndef offsetof
+#include "stddef.h"
+#endif
+
+using namespace RiscVGen;
+using namespace RiscVJitConstants;
+
+RiscVRegCache::RiscVRegCache(MIPSState *mipsState, MIPSComp::JitOptions *jo)
+ : mips_(mipsState), jo_(jo) {
+}
+
+void RiscVRegCache::Init(RiscVEmitter *emitter) {
+ emit_ = emitter;
+}
+
+void RiscVRegCache::Start() {
+ for (int i = 0; i < NUM_RVREG; i++) {
+ ar[i].mipsReg = IRREG_INVALID;
+ ar[i].isDirty = false;
+ ar[i].pointerified = false;
+ ar[i].tempLocked = false;
+ }
+ for (int i = 0; i < NUM_MIPSREG; i++) {
+ mr[i].loc = MIPSLoc::MEM;
+ mr[i].reg = INVALID_REG;
+ mr[i].imm = -1;
+ mr[i].spillLock = false;
+ mr[i].isStatic = false;
+ }
+ int numStatics;
+ const StaticAllocation *statics = GetStaticAllocations(numStatics);
+ for (int i = 0; i < numStatics; i++) {
+ ar[statics[i].ar].mipsReg = statics[i].mr;
+ ar[statics[i].ar].pointerified = statics[i].pointerified && jo_->enablePointerify;
+ mr[statics[i].mr].loc = MIPSLoc::RVREG;
+ mr[statics[i].mr].reg = statics[i].ar;
+ mr[statics[i].mr].isStatic = true;
+ mr[statics[i].mr].spillLock = true;
+ }
+
+ // Treat R_ZERO a bit specially, but it's basically static alloc too.
+ ar[R_ZERO].mipsReg = MIPS_REG_ZERO;
+ mr[MIPS_REG_ZERO].loc = MIPSLoc::RVREG_IMM;
+ mr[MIPS_REG_ZERO].reg = R_ZERO;
+ mr[MIPS_REG_ZERO].imm = 0;
+ mr[MIPS_REG_ZERO].isStatic = true;
+}
+
+const RiscVReg *RiscVRegCache::GetMIPSAllocationOrder(int &count) {
+ // X8 and X9 are the most ideal for static alloc because they can be used with compression.
+ // Otherwise we stick to saved regs - might not be necessary.
+ static const RiscVReg allocationOrder[] = {
+ X7, X8, X9, X12, X13, X14, X1, X5, X6, X15, X16, X17, X18, X19, X20, X21, X22, X23, X28, X29, X30, X31,
+ };
+ static const RiscVReg allocationOrderStaticAlloc[] = {
+ X7, X12, X13, X14, X1, X5, X6, X15, X16, X17, X21, X22, X23, X28, X29, X30, X31,
+ };
+
+ if (jo_->useStaticAlloc) {
+ count = ARRAY_SIZE(allocationOrderStaticAlloc);
+ return allocationOrderStaticAlloc;
+ } else {
+ count = ARRAY_SIZE(allocationOrder);
+ return allocationOrder;
+ }
+}
+
+const RiscVRegCache::StaticAllocation *RiscVRegCache::GetStaticAllocations(int &count) {
+ static const StaticAllocation allocs[] = {
+ { MIPS_REG_SP, X8, true },
+ { MIPS_REG_V0, X9 },
+ { MIPS_REG_V1, X18 },
+ { MIPS_REG_A0, X19 },
+ { MIPS_REG_RA, X20 },
+ };
+
+ if (jo_->useStaticAlloc) {
+ count = ARRAY_SIZE(allocs);
+ return allocs;
+ } else {
+ count = 0;
+ return nullptr;
+ }
+}
+
+void RiscVRegCache::EmitLoadStaticRegisters() {
+ int count;
+ const StaticAllocation *allocs = GetStaticAllocations(count);
+ for (int i = 0; i < count; i++) {
+ int offset = GetMipsRegOffset(allocs[i].mr);
+ emit_->LWU(allocs[i].ar, CTXREG, offset);
+ if (allocs[i].pointerified && jo_->enablePointerify) {
+ emit_->ADD(allocs[i].ar, allocs[i].ar, MEMBASEREG);
+ }
+ }
+}
+
+void RiscVRegCache::EmitSaveStaticRegisters() {
+ int count;
+ const StaticAllocation *allocs = GetStaticAllocations(count);
+ // This only needs to run once (by Asm) so checks don't need to be fast.
+ for (int i = 0; i < count; i++) {
+ int offset = GetMipsRegOffset(allocs[i].mr);
+ // TODO: Check dirty?
+ emit_->SW(allocs[i].ar, CTXREG, offset);
+ }
+}
+
+void RiscVRegCache::FlushBeforeCall() {
+ // These registers are not preserved by function calls.
+ for (int i = 5; i <= 7; ++i) {
+ FlushRiscVReg(RiscVReg(X0 + i));
+ }
+ for (int i = 10; i <= 17; ++i) {
+ FlushRiscVReg(RiscVReg(X0 + i));
+ }
+ for (int i = 28; i <= 31; ++i) {
+ FlushRiscVReg(RiscVReg(X0 + i));
+ }
+}
+
+bool RiscVRegCache::IsInRAM(IRRegIndex reg) {
+ _dbg_assert_(IsValidReg(reg));
+ return mr[reg].loc == MIPSLoc::MEM;
+}
+
+bool RiscVRegCache::IsMapped(IRRegIndex mipsReg) {
+ _dbg_assert_(IsValidReg(mipsReg));
+ return mr[mipsReg].loc == MIPSLoc::RVREG || mr[mipsReg].loc == MIPSLoc::RVREG_IMM;
+}
+
+bool RiscVRegCache::IsMappedAsPointer(IRRegIndex mipsReg) {
+ _dbg_assert_(IsValidReg(mipsReg));
+ if (mr[mipsReg].loc == MIPSLoc::RVREG) {
+ return ar[mr[mipsReg].reg].pointerified;
+ } else if (mr[mipsReg].loc == MIPSLoc::RVREG_IMM) {
+ if (ar[mr[mipsReg].reg].pointerified) {
+ ERROR_LOG(JIT, "Really shouldn't be pointerified here");
+ }
+ } else if (mr[mipsReg].loc == MIPSLoc::RVREG_AS_PTR) {
+ return true;
+ }
+ return false;
+}
+
+void RiscVRegCache::MarkDirty(RiscVReg reg) {
+ // Can't mark X0 dirty.
+ _dbg_assert_(reg > X0 && reg <= X31);
+ ar[reg].isDirty = true;
+}
+
+void RiscVRegCache::SetRegImm(RiscVReg reg, u64 imm) {
+ _dbg_assert_(reg != R_ZERO || imm == 0);
+ _dbg_assert_(reg >= X0 && reg <= X31);
+ // TODO: Could optimize this more for > 32 bit constants.
+ emit_->LI(reg, imm);
+ _dbg_assert_(!ar[reg].pointerified);
+}
+
+void RiscVRegCache::MapRegTo(RiscVReg reg, IRRegIndex mipsReg, int mapFlags) {
+ _dbg_assert_(reg > X0 && reg <= X31);
+ _dbg_assert_(IsValidReg(mipsReg));
+ _dbg_assert_(!mr[mipsReg].isStatic);
+ if (mr[mipsReg].isStatic) {
+ ERROR_LOG(JIT, "Cannot MapRegTo static register %d", mipsReg);
+ return;
+ }
+ ar[reg].isDirty = (mapFlags & MAP_DIRTY) != 0;
+ if ((mapFlags & MAP_NOINIT) != MAP_NOINIT) {
+ if (mipsReg == MIPS_REG_ZERO) {
+ // If we get a request to load the zero register, at least we won't spend
+ // time on a memory access...
+ emit_->LI(reg, 0);
+
+ // This way, if we SetImm() it, we'll keep it.
+ mr[mipsReg].loc = MIPSLoc::RVREG_IMM;
+ mr[mipsReg].imm = 0;
+ } else {
+ switch (mr[mipsReg].loc) {
+ case MIPSLoc::MEM:
+ emit_->LWU(reg, CTXREG, GetMipsRegOffset(mipsReg));
+ mr[mipsReg].loc = MIPSLoc::RVREG;
+ break;
+ case MIPSLoc::IMM:
+ SetRegImm(reg, mr[mipsReg].imm);
+ // IMM is always dirty.
+ ar[reg].isDirty = true;
+
+ // If we are mapping dirty, it means we're gonna overwrite.
+ // So the imm value is no longer valid.
+ if (mapFlags & MAP_DIRTY)
+ mr[mipsReg].loc = MIPSLoc::RVREG;
+ else
+ mr[mipsReg].loc = MIPSLoc::RVREG_IMM;
+ break;
+ case MIPSLoc::RVREG_IMM:
+ // If it's not dirty, we can keep it.
+ if (ar[reg].isDirty)
+ mr[mipsReg].loc = MIPSLoc::RVREG;
+ break;
+ default:
+ _assert_msg_(mr[mipsReg].loc != MIPSLoc::RVREG_AS_PTR, "MapRegTo with a pointer?");
+ mr[mipsReg].loc = MIPSLoc::RVREG;
+ break;
+ }
+ }
+ } else {
+ _dbg_assert_(mipsReg != MIPS_REG_ZERO);
+ _dbg_assert_(ar[reg].isDirty);
+ mr[mipsReg].loc = MIPSLoc::RVREG;
+ }
+ ar[reg].mipsReg = mipsReg;
+ ar[reg].pointerified = false;
+ mr[mipsReg].reg = reg;
+}
+
+RiscVReg RiscVRegCache::AllocateReg() {
+ int allocCount;
+ const RiscVReg *allocOrder = GetMIPSAllocationOrder(allocCount);
+
+allocate:
+ for (int i = 0; i < allocCount; i++) {
+ RiscVReg reg = allocOrder[i];
+
+ if (ar[reg].mipsReg == IRREG_INVALID && !ar[reg].tempLocked) {
+ return reg;
+ }
+ }
+
+ // Still nothing. Let's spill a reg and goto 10.
+ // TODO: Use age or something to choose which register to spill?
+ // TODO: Spill dirty regs first? or opposite?
+ bool clobbered;
+ RiscVReg bestToSpill = FindBestToSpill(true, &clobbered);
+ if (bestToSpill == INVALID_REG) {
+ bestToSpill = FindBestToSpill(false, &clobbered);
+ }
+
+ if (bestToSpill != INVALID_REG) {
+ if (clobbered) {
+ DiscardR(ar[bestToSpill].mipsReg);
+ } else {
+ FlushRiscVReg(bestToSpill);
+ }
+ // Now one must be free.
+ goto allocate;
+ }
+
+ // Uh oh, we have all of them spilllocked....
+ ERROR_LOG_REPORT(JIT, "Out of spillable registers near PC %08x", mips_->pc);
+ _assert_(bestToSpill != INVALID_REG);
+ return INVALID_REG;
+}
+
+RiscVReg RiscVRegCache::FindBestToSpill(bool unusedOnly, bool *clobbered) {
+ int allocCount;
+ const RiscVReg *allocOrder = GetMIPSAllocationOrder(allocCount);
+
+ static const int UNUSED_LOOKAHEAD_OPS = 30;
+
+ *clobbered = false;
+ for (int i = 0; i < allocCount; i++) {
+ RiscVReg reg = allocOrder[i];
+ if (ar[reg].mipsReg != IRREG_INVALID && mr[ar[reg].mipsReg].spillLock)
+ continue;
+ if (ar[reg].tempLocked)
+ continue;
+
+ // As it's in alloc-order, we know it's not static so we don't need to check for that.
+
+ // TODO: Look for clobbering in the IRInst array with index?
+
+ // Not awesome. A used reg. Let's try to avoid spilling.
+ // TODO: Actually check if we'd be spilling.
+ if (unusedOnly) {
+ continue;
+ }
+
+ return reg;
+ }
+
+ return INVALID_REG;
+}
+
+RiscVReg RiscVRegCache::TryMapTempImm(IRRegIndex r) {
+ _dbg_assert_(IsValidReg(r));
+ // If already mapped, no need for a temporary.
+ if (IsMapped(r)) {
+ return R(r);
+ }
+
+ if (mr[r].loc == MIPSLoc::IMM) {
+ if (mr[r].imm == 0) {
+ return R_ZERO;
+ }
+
+ // Try our luck - check for an exact match in another rvreg.
+ for (int i = 0; i < NUM_MIPSREG; ++i) {
+ if (mr[i].loc == MIPSLoc::RVREG_IMM && mr[i].imm == mr[r].imm) {
+ // Awesome, let's just use this reg.
+ return mr[i].reg;
+ }
+ }
+ }
+
+ return INVALID_REG;
+}
+
+RiscVReg RiscVRegCache::GetAndLockTempR() {
+ RiscVReg reg = AllocateReg();
+ if (reg != INVALID_REG) {
+ ar[reg].tempLocked = true;
+ }
+ return reg;
+}
+
+RiscVReg RiscVRegCache::MapReg(IRRegIndex mipsReg, int mapFlags) {
+ _dbg_assert_(IsValidReg(mipsReg));
+
+ // TODO: Optimization to force HI/LO to be combined?
+
+ if (mipsReg == IRREG_INVALID) {
+ ERROR_LOG(JIT, "Cannot map invalid register");
+ return INVALID_REG;
+ }
+
+ RiscVReg riscvReg = mr[mipsReg].reg;
+
+ if (mr[mipsReg].isStatic) {
+ _dbg_assert_(riscvReg != INVALID_REG);
+ if (riscvReg == INVALID_REG) {
+ ERROR_LOG(JIT, "MapReg on statically mapped reg %d failed - riscvReg got lost", mipsReg);
+ }
+ if (mr[mipsReg].loc == MIPSLoc::IMM) {
+ // Back into the register, with or without the imm value.
+ // If noinit, the MAP_DIRTY check below will take care of the rest.
+ if ((mapFlags & MAP_NOINIT) != MAP_NOINIT) {
+ SetRegImm(riscvReg, mr[mipsReg].imm);
+ mr[mipsReg].loc = MIPSLoc::RVREG_IMM;
+ ar[riscvReg].pointerified = false;
+ }
+ } else if (mr[mipsReg].loc == MIPSLoc::RVREG_AS_PTR) {
+ // Was mapped as pointer, now we want it mapped as a value, presumably to
+ // add or subtract stuff to it.
+ if ((mapFlags & MAP_NOINIT) != MAP_NOINIT) {
+#ifdef MASKED_PSP_MEMORY
+ _dbg_assert_(!ar[riscvReg].isDirty && (mapFlags & MAP_DIRTY) == 0);
+#endif
+ emit_->SUB(riscvReg, riscvReg, MEMBASEREG);
+ }
+ mr[mipsReg].loc = MIPSLoc::RVREG;
+ }
+ // Erasing the imm on dirty (necessary since otherwise we will still think it's ML_RVREG_IMM and return
+ // true for IsImm and calculate crazily wrong things). /unknown
+ if (mapFlags & MAP_DIRTY) {
+ // As we are dirty, can't keep RVREG_IMM, we will quickly drift out of sync
+ mr[mipsReg].loc = MIPSLoc::RVREG;
+ ar[riscvReg].pointerified = false;
+ ar[riscvReg].isDirty = true;
+ }
+ return mr[mipsReg].reg;
+ }
+
+ // Let's see if it's already mapped. If so we just need to update the dirty flag.
+ // We don't need to check for ML_NOINIT because we assume that anyone who maps
+ // with that flag immediately writes a "known" value to the register.
+ if (mr[mipsReg].loc == MIPSLoc::RVREG || mr[mipsReg].loc == MIPSLoc::RVREG_IMM) {
+ _dbg_assert_(riscvReg != INVALID_REG && ar[riscvReg].mipsReg == mipsReg);
+ if (ar[riscvReg].mipsReg != mipsReg) {
+ ERROR_LOG_REPORT(JIT, "Register mapping out of sync! %i", mipsReg);
+ }
+ if (mapFlags & MAP_DIRTY) {
+ // Mapping dirty means the old imm value is invalid.
+ mr[mipsReg].loc = MIPSLoc::RVREG;
+ ar[riscvReg].isDirty = true;
+ // If reg is written to, pointerification is lost.
+ ar[riscvReg].pointerified = false;
+ }
+
+ return mr[mipsReg].reg;
+ } else if (mr[mipsReg].loc == MIPSLoc::RVREG_AS_PTR) {
+ // Was mapped as pointer, now we want it mapped as a value, presumably to
+ // add or subtract stuff to it.
+ if ((mapFlags & MAP_NOINIT) != MAP_NOINIT) {
+#ifdef MASKED_PSP_MEMORY
+ _dbg_assert_(!ar[riscvReg].isDirty && (mapFlags & MAP_DIRTY) == 0);
+#endif
+ emit_->SUB(riscvReg, riscvReg, MEMBASEREG);
+ }
+ mr[mipsReg].loc = MIPSLoc::RVREG;
+ if (mapFlags & MAP_DIRTY) {
+ ar[riscvReg].isDirty = true;
+ }
+ return mr[mipsReg].reg;
+ }
+
+ // Okay, not mapped, so we need to allocate an RV register.
+ RiscVReg reg = AllocateReg();
+ if (reg != INVALID_REG) {
+ // Grab it, and load the value into it (if requested).
+ MapRegTo(reg, mipsReg, mapFlags);
+ }
+
+ return reg;
+}
+
+RiscVReg RiscVRegCache::MapRegAsPointer(IRRegIndex reg) {
+ _dbg_assert_(IsValidRegNoZero(reg));
+
+ // Already mapped.
+ if (mr[reg].loc == MIPSLoc::RVREG_AS_PTR) {
+ return mr[reg].reg;
+ }
+
+ RiscVReg riscvReg = INVALID_REG;
+ if (mr[reg].loc != MIPSLoc::RVREG && mr[reg].loc != MIPSLoc::RVREG_IMM) {
+ riscvReg = MapReg(reg);
+ } else {
+ riscvReg = mr[reg].reg;
+ }
+
+ if (mr[reg].loc == MIPSLoc::RVREG || mr[reg].loc == MIPSLoc::RVREG_IMM) {
+ // If there was an imm attached, discard it.
+ mr[reg].loc = MIPSLoc::RVREG;
+ if (!jo_->enablePointerify) {
+ // Convert to a pointer by adding the base and clearing off the top bits.
+ // If SP, we can probably avoid the top bit clear, let's play with that later.
+#ifdef MASKED_PSP_MEMORY
+ // This destroys the value...
+ _dbg_assert_(!ar[riscvReg].isDirty);
+ emit_->SLLIW(riscvReg, riscvReg, 2);
+ emit_->SRLIW(riscvReg, riscvReg, 2);
+#endif
+ emit_->ADD(riscvReg, riscvReg, MEMBASEREG);
+ mr[reg].loc = MIPSLoc::RVREG_AS_PTR;
+ } else if (!ar[riscvReg].pointerified) {
+ emit_->ADD(riscvReg, riscvReg, MEMBASEREG);
+ ar[riscvReg].pointerified = true;
+ }
+ } else {
+ ERROR_LOG(JIT, "MapRegAsPointer : MapReg failed to allocate a register?");
+ }
+ return riscvReg;
+}
+
+void RiscVRegCache::MapIn(IRRegIndex rs) {
+ MapReg(rs);
+}
+
+void RiscVRegCache::MapInIn(IRRegIndex rd, IRRegIndex rs) {
+ SpillLock(rd, rs);
+ MapReg(rd);
+ MapReg(rs);
+ ReleaseSpillLock(rd, rs);
+}
+
+void RiscVRegCache::MapDirtyIn(IRRegIndex rd, IRRegIndex rs, bool avoidLoad) {
+ SpillLock(rd, rs);
+ bool load = !avoidLoad || rd == rs;
+ MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
+ MapReg(rs);
+ ReleaseSpillLock(rd, rs);
+}
+
+void RiscVRegCache::MapDirtyInIn(IRRegIndex rd, IRRegIndex rs, IRRegIndex rt, bool avoidLoad) {
+ SpillLock(rd, rs, rt);
+ bool load = !avoidLoad || (rd == rs || rd == rt);
+ MapReg(rd, load ? MAP_DIRTY : MAP_NOINIT);
+ MapReg(rt);
+ MapReg(rs);
+ ReleaseSpillLock(rd, rs, rt);
+}
+
+void RiscVRegCache::MapDirtyDirtyIn(IRRegIndex rd1, IRRegIndex rd2, IRRegIndex rs, bool avoidLoad) {
+ SpillLock(rd1, rd2, rs);
+ bool load1 = !avoidLoad || rd1 == rs;
+ bool load2 = !avoidLoad || rd2 == rs;
+ MapReg(rd1, load1 ? MAP_DIRTY : MAP_NOINIT);
+ MapReg(rd2, load2 ? MAP_DIRTY : MAP_NOINIT);
+ MapReg(rs);
+ ReleaseSpillLock(rd1, rd2, rs);
+}
+
+void RiscVRegCache::MapDirtyDirtyInIn(IRRegIndex rd1, IRRegIndex rd2, IRRegIndex rs, IRRegIndex rt, bool avoidLoad) {
+ SpillLock(rd1, rd2, rs, rt);
+ bool load1 = !avoidLoad || (rd1 == rs || rd1 == rt);
+ bool load2 = !avoidLoad || (rd2 == rs || rd2 == rt);
+ MapReg(rd1, load1 ? MAP_DIRTY : MAP_NOINIT);
+ MapReg(rd2, load2 ? MAP_DIRTY : MAP_NOINIT);
+ MapReg(rt);
+ MapReg(rs);
+ ReleaseSpillLock(rd1, rd2, rs, rt);
+}
+
+void RiscVRegCache::FlushRiscVReg(RiscVReg r) {
+ _dbg_assert_(r > X0 && r <= X31);
+ _dbg_assert_(ar[r].mipsReg != MIPS_REG_ZERO);
+ _dbg_assert_(!mr[ar[r].mipsReg].isStatic);
+ if (r == INVALID_REG) {
+ ERROR_LOG(JIT, "FlushRiscVReg called on invalid register %d", r);
+ return;
+ }
+ if (ar[r].mipsReg == IRREG_INVALID) {
+ // Nothing to do, reg not mapped.
+ _dbg_assert_(!ar[r].isDirty);
+ return;
+ }
+ if (mr[ar[r].mipsReg].isStatic) {
+ ERROR_LOG(JIT, "Cannot FlushRiscVReg a statically mapped register");
+ return;
+ }
+ auto &mreg = mr[ar[r].mipsReg];
+ if (mreg.loc == MIPSLoc::RVREG_IMM || ar[r].mipsReg == MIPS_REG_ZERO) {
+ // We know its immediate value, no need to STR now.
+ mreg.loc = MIPSLoc::IMM;
+ mreg.reg = INVALID_REG;
+ } else {
+ if (mreg.loc == MIPSLoc::IMM || ar[r].isDirty) {
+ if (mreg.loc == MIPSLoc::RVREG_AS_PTR) {
+ // Unpointerify, in case dirty.
+#ifdef MASKED_PSP_MEMORY
+ _dbg_assert_(!ar[r].isDirty && (mapFlags & MAP_DIRTY) == 0);
+#endif
+ emit_->SUB(r, r, MEMBASEREG);
+ mreg.loc = MIPSLoc::RVREG;
+ }
+ RiscVReg storeReg = RiscVRegForFlush(ar[r].mipsReg);
+ if (storeReg != INVALID_REG)
+ emit_->SW(storeReg, CTXREG, GetMipsRegOffset(ar[r].mipsReg));
+ }
+ mreg.loc = MIPSLoc::MEM;
+ mreg.reg = INVALID_REG;
+ mreg.imm = -1;
+ }
+ ar[r].isDirty = false;
+ ar[r].mipsReg = IRREG_INVALID;
+ ar[r].pointerified = false;
+}
+
+void RiscVRegCache::DiscardR(IRRegIndex mipsReg) {
+ _dbg_assert_(IsValidRegNoZero(mipsReg));
+ if (mr[mipsReg].isStatic) {
+ // Simply do nothing unless it's an IMM/RVREG_IMM/RVREG_AS_PTR, in case we just switch it over to RVREG, losing the value.
+ RiscVReg riscvReg = mr[mipsReg].reg;
+ _dbg_assert_(riscvReg != INVALID_REG);
+ if (mipsReg == MIPS_REG_ZERO) {
+ // Shouldn't happen, but in case it does.
+ mr[mipsReg].loc = MIPSLoc::RVREG_IMM;
+ mr[mipsReg].reg = R_ZERO;
+ mr[mipsReg].imm = 0;
+ } else if (mr[mipsReg].loc == MIPSLoc::RVREG_IMM || mr[mipsReg].loc == MIPSLoc::IMM || mr[mipsReg].loc == MIPSLoc::RVREG_AS_PTR) {
+ // Ignore the imm value, restore sanity
+ mr[mipsReg].loc = MIPSLoc::RVREG;
+ ar[riscvReg].pointerified = false;
+ ar[riscvReg].isDirty = false;
+ }
+ return;
+ }
+ const MIPSLoc prevLoc = mr[mipsReg].loc;
+ if (prevLoc == MIPSLoc::RVREG || prevLoc == MIPSLoc::RVREG_IMM || prevLoc == MIPSLoc::RVREG_AS_PTR) {
+ RiscVReg riscvReg = mr[mipsReg].reg;
+ _dbg_assert_(riscvReg != INVALID_REG);
+ ar[riscvReg].mipsReg = IRREG_INVALID;
+ ar[riscvReg].pointerified = false;
+ ar[riscvReg].isDirty = false;
+ mr[mipsReg].reg = INVALID_REG;
+ mr[mipsReg].loc = MIPSLoc::MEM;
+ mr[mipsReg].imm = -1;
+ }
+ if (prevLoc == MIPSLoc::IMM && mipsReg != MIPS_REG_ZERO) {
+ mr[mipsReg].loc = MIPSLoc::MEM;
+ mr[mipsReg].imm = -1;
+ }
+}
+
+RiscVReg RiscVRegCache::RiscVRegForFlush(IRRegIndex r) {
+ _dbg_assert_(IsValidReg(r));
+ if (mr[r].isStatic)
+ return INVALID_REG; // No flushing needed
+
+ switch (mr[r].loc) {
+ case MIPSLoc::IMM:
+ if (r == MIPS_REG_ZERO) {
+ return INVALID_REG;
+ }
+ // Zero is super easy.
+ if (mr[r].imm == 0) {
+ return R_ZERO;
+ }
+ // Could we get lucky? Check for an exact match in another rvreg.
+ for (int i = 0; i < NUM_MIPSREG; ++i) {
+ if (mr[i].loc == MIPSLoc::RVREG_IMM && mr[i].imm == mr[r].imm) {
+ // Awesome, let's just store this reg.
+ return mr[i].reg;
+ }
+ }
+ return INVALID_REG;
+
+ case MIPSLoc::RVREG:
+ case MIPSLoc::RVREG_IMM:
+ if (mr[r].reg == INVALID_REG) {
+ ERROR_LOG_REPORT(JIT, "RiscVRegForFlush: MipsReg %d had bad riscvReg", r);
+ return INVALID_REG;
+ }
+ // No need to flush if it's zero or not dirty.
+ if (r == MIPS_REG_ZERO || !ar[mr[r].reg].isDirty) {
+ return INVALID_REG;
+ }
+ // TODO: Lo/hi optimization?
+ return mr[r].reg;
+
+ case MIPSLoc::RVREG_AS_PTR:
+ return INVALID_REG;
+
+ case MIPSLoc::MEM:
+ return INVALID_REG;
+
+ default:
+ ERROR_LOG_REPORT(JIT, "RiscVRegForFlush: MipsReg %d with invalid location %d", r, (int)mr[r].loc);
+ return INVALID_REG;
+ }
+}
+
+void RiscVRegCache::FlushR(IRRegIndex r) {
+ _dbg_assert_(IsValidRegNoZero(r));
+ if (mr[r].isStatic) {
+ ERROR_LOG(JIT, "Cannot flush static reg %d", r);
+ return;
+ }
+
+ switch (mr[r].loc) {
+ case MIPSLoc::IMM:
+ // IMM is always "dirty".
+ // TODO: HI/LO optimization?
+ if (r != MIPS_REG_ZERO) {
+ // Try to optimize using a different reg.
+ RiscVReg storeReg = RiscVRegForFlush(r);
+ if (storeReg == INVALID_REG) {
+ SetRegImm(SCRATCH1, mr[r].imm);
+ storeReg = SCRATCH1;
+ }
+ emit_->SW(storeReg, CTXREG, GetMipsRegOffset(r));
+ }
+ break;
+
+ case MIPSLoc::RVREG:
+ case MIPSLoc::RVREG_IMM:
+ if (ar[mr[r].reg].isDirty) {
+ RiscVReg storeReg = RiscVRegForFlush(r);
+ if (storeReg != INVALID_REG) {
+ emit_->SW(storeReg, CTXREG, GetMipsRegOffset(r));
+ }
+ ar[mr[r].reg].isDirty = false;
+ }
+ ar[mr[r].reg].mipsReg = IRREG_INVALID;
+ ar[mr[r].reg].pointerified = false;
+ break;
+
+ case MIPSLoc::RVREG_AS_PTR:
+ if (ar[mr[r].reg].isDirty) {
+#ifdef MASKED_PSP_MEMORY
+ // This is kinda bad, because we've cleared bits in it.
+ _dbg_assert_(!ar[mr[r].reg].isDirty);
+#endif
+ emit_->SUB(mr[r].reg, mr[r].reg, MEMBASEREG);
+ // We set this so RiscVRegForFlush knows it's no longer a pointer.
+ mr[r].loc = MIPSLoc::RVREG;
+ RiscVReg storeReg = RiscVRegForFlush(r);
+ if (storeReg != INVALID_REG) {
+ emit_->SW(storeReg, CTXREG, GetMipsRegOffset(r));
+ }
+ ar[mr[r].reg].isDirty = false;
+ }
+ ar[mr[r].reg].mipsReg = IRREG_INVALID;
+ break;
+
+ case MIPSLoc::MEM:
+ // Already there, nothing to do.
+ break;
+
+ default:
+ ERROR_LOG_REPORT(JIT, "FlushR: MipsReg %d with invalid location %d", r, (int)mr[r].loc);
+ break;
+ }
+ if (r == MIPS_REG_ZERO) {
+ mr[r].loc = MIPSLoc::RVREG_IMM;
+ mr[r].reg = R_ZERO;
+ mr[r].imm = 0;
+ } else {
+ mr[r].loc = MIPSLoc::MEM;
+ mr[r].reg = INVALID_REG;
+ mr[r].imm = -1;
+ }
+}
+
+void RiscVRegCache::FlushAll() {
+ // Note: make sure not to change the registers when flushing:
+ // Branching code expects the armreg to retain its value.
+
+ // TODO: HI/LO optimization?
+
+ // Final pass to grab any that were left behind.
+ for (int i = 1; i < NUM_MIPSREG; i++) {
+ IRRegIndex mipsReg = IRRegIndex(i);
+ if (mr[i].isStatic) {
+ RiscVReg riscvReg = mr[i].reg;
+ // Cannot leave any IMMs in registers, not even ML_ARMREG_IMM, can confuse the regalloc later if this flush is mid-block
+ // due to an interpreter fallback that changes the register.
+ if (mr[i].loc == MIPSLoc::IMM) {
+ SetRegImm(mr[i].reg, mr[i].imm);
+ mr[i].loc = MIPSLoc::RVREG;
+ ar[riscvReg].pointerified = false;
+ } else if (mr[i].loc == MIPSLoc::RVREG_IMM) {
+ // The register already contains the immediate.
+ if (ar[riscvReg].pointerified) {
+ ERROR_LOG(JIT, "RVREG_IMM but pointerified. Wrong.");
+ ar[riscvReg].pointerified = false;
+ }
+ mr[i].loc = MIPSLoc::RVREG;
+ } else if (mr[i].loc == MIPSLoc::RVREG_AS_PTR) {
+#ifdef MASKED_PSP_MEMORY
+ _dbg_assert_(!ar[riscvReg].isDirty);
+#endif
+ emit_->SUB(riscvReg, riscvReg, MEMBASEREG);
+ mr[i].loc = MIPSLoc::RVREG;
+ }
+ if (i != MIPS_REG_ZERO && mr[i].reg == INVALID_REG) {
+ ERROR_LOG(JIT, "RV reg of static %i is invalid", i);
+ continue;
+ }
+ } else if (IsValidRegNoZero(mipsReg)) {
+ FlushR(mipsReg);
+ }
+ }
+
+ int count = 0;
+ const StaticAllocation *allocs = GetStaticAllocations(count);
+ for (int i = 0; i < count; i++) {
+ if (allocs[i].pointerified && !ar[allocs[i].ar].pointerified && jo_->enablePointerify) {
+ // Re-pointerify
+ emit_->ADD(allocs[i].ar, allocs[i].ar, MEMBASEREG);
+ ar[allocs[i].ar].pointerified = true;
+ } else {
+ // If this register got pointerified on the way, mark it as not.
+ // This nis so that after save/reload (like in an interpreter fallback),
+ // it won't be regarded as such, as it may no longer be.
+ ar[allocs[i].ar].pointerified = false;
+ }
+ }
+ // Sanity check
+ for (int i = 0; i < NUM_RVREG; i++) {
+ if (ar[i].mipsReg != IRREG_INVALID && mr[ar[i].mipsReg].isStatic == false) {
+ ERROR_LOG_REPORT(JIT, "Flush fail: ar[%i].mipsReg=%i", i, ar[i].mipsReg);
+ }
+ }
+}
+
+void RiscVRegCache::SetImm(IRRegIndex r, u64 immVal) {
+ _dbg_assert_(IsValidReg(r));
+ if (r == MIPS_REG_ZERO && immVal != 0) {
+ ERROR_LOG_REPORT(JIT, "Trying to set immediate %08x to r0", (u32)immVal);
+ return;
+ }
+
+ if (mr[r].loc == MIPSLoc::RVREG_IMM && mr[r].imm == immVal) {
+ // Already have that value, let's keep it in the reg.
+ return;
+ }
+
+ // TODO: HI/LO optimization?
+ // All regs on the PSP are 32 bit, but LO we treat as HI:LO so is 64 full bits.
+ immVal = immVal & 0xFFFFFFFF;
+
+ if (mr[r].isStatic) {
+ mr[r].loc = MIPSLoc::IMM;
+ mr[r].imm = immVal;
+ ar[mr[r].reg].pointerified = false;
+ // We do not change reg to INVALID_REG for obvious reasons..
+ } else {
+ // Zap existing value if cached in a reg
+ if (mr[r].reg != INVALID_REG) {
+ ar[mr[r].reg].mipsReg = IRREG_INVALID;
+ ar[mr[r].reg].isDirty = false;
+ ar[mr[r].reg].pointerified = false;
+ }
+ mr[r].loc = MIPSLoc::IMM;
+ mr[r].imm = immVal;
+ mr[r].reg = INVALID_REG;
+ }
+}
+
+bool RiscVRegCache::IsImm(IRRegIndex r) const {
+ _dbg_assert_(IsValidReg(r));
+ if (r == MIPS_REG_ZERO)
+ return true;
+ else
+ return mr[r].loc == MIPSLoc::IMM || mr[r].loc == MIPSLoc::RVREG_IMM;
+}
+
+bool RiscVRegCache::IsPureImm(IRRegIndex r) const {
+ _dbg_assert_(IsValidReg(r));
+ if (r == MIPS_REG_ZERO)
+ return true;
+ else
+ return mr[r].loc == MIPSLoc::IMM;
+}
+
+u64 RiscVRegCache::GetImm(IRRegIndex r) const {
+ _dbg_assert_(IsValidReg(r));
+ if (r == MIPS_REG_ZERO)
+ return 0;
+ if (mr[r].loc != MIPSLoc::IMM && mr[r].loc != MIPSLoc::RVREG_IMM) {
+ ERROR_LOG_REPORT(JIT, "Trying to get imm from non-imm register %i", r);
+ }
+ return mr[r].imm;
+}
+
+int RiscVRegCache::GetMipsRegOffset(IRRegIndex r) {
+ _dbg_assert_(IsValidReg(r));
+ return r * 4;
+}
+
+bool RiscVRegCache::IsValidReg(IRRegIndex r) const {
+ if (r < 0 || r >= NUM_MIPSREG)
+ return false;
+
+ // See MIPSState for these offsets.
+
+ // Don't allow FPU or VFPU regs here.
+ if (r >= 32 && r < 32 + 32 + 128)
+ return false;
+ // Also disallow VFPU temps.
+ if (r >= 224 && r < 224 + 16)
+ return false;
+ // Don't allow nextPC, etc. since it's probably a mistake.
+ if (r > 245)
+ return false;
+ // Don't allow PC either.
+ if (r == 241)
+ return false;
+
+ return true;
+}
+
+bool RiscVRegCache::IsValidRegNoZero(IRRegIndex r) const {
+ return IsValidReg(r) && r != MIPS_REG_ZERO;
+}
+
+void RiscVRegCache::SpillLock(IRRegIndex r1, IRRegIndex r2, IRRegIndex r3, IRRegIndex r4) {
+ _dbg_assert_(IsValidReg(r1));
+ _dbg_assert_(r2 == IRREG_INVALID || IsValidReg(r2));
+ _dbg_assert_(r3 == IRREG_INVALID || IsValidReg(r3));
+ _dbg_assert_(r4 == IRREG_INVALID || IsValidReg(r4));
+ mr[r1].spillLock = true;
+ if (r2 != IRREG_INVALID) mr[r2].spillLock = true;
+ if (r3 != IRREG_INVALID) mr[r3].spillLock = true;
+ if (r4 != IRREG_INVALID) mr[r4].spillLock = true;
+}
+
+void RiscVRegCache::ReleaseSpillLocksAndDiscardTemps() {
+ for (int i = 0; i < NUM_MIPSREG; i++) {
+ if (!mr[i].isStatic)
+ mr[i].spillLock = false;
+ }
+ for (int i = 0; i < NUM_RVREG; i++) {
+ ar[i].tempLocked = false;
+ }
+}
+
+void RiscVRegCache::ReleaseSpillLock(IRRegIndex r1, IRRegIndex r2, IRRegIndex r3, IRRegIndex r4) {
+ _dbg_assert_(IsValidReg(r1));
+ _dbg_assert_(r2 == IRREG_INVALID || IsValidReg(r2));
+ _dbg_assert_(r3 == IRREG_INVALID || IsValidReg(r3));
+ _dbg_assert_(r4 == IRREG_INVALID || IsValidReg(r4));
+ if (!mr[r1].isStatic)
+ mr[r1].spillLock = false;
+ if (r2 != IRREG_INVALID && !mr[r2].isStatic)
+ mr[r2].spillLock = false;
+ if (r3 != IRREG_INVALID && !mr[r3].isStatic)
+ mr[r3].spillLock = false;
+ if (r4 != IRREG_INVALID && !mr[r4].isStatic)
+ mr[r4].spillLock = false;
+}
+
+RiscVReg RiscVRegCache::R(IRRegIndex mipsReg) {
+ _dbg_assert_(IsValidReg(mipsReg));
+ _dbg_assert_(mr[mipsReg].loc == MIPSLoc::RVREG || mr[mipsReg].loc == MIPSLoc::RVREG_IMM);
+ if (mr[mipsReg].loc == MIPSLoc::RVREG || mr[mipsReg].loc == MIPSLoc::RVREG_IMM) {
+ return mr[mipsReg].reg;
+ } else {
+ ERROR_LOG_REPORT(JIT, "Reg %i not in riscv reg", mipsReg);
+ return INVALID_REG; // BAAAD
+ }
+}
+
+RiscVReg RiscVRegCache::RPtr(IRRegIndex mipsReg) {
+ _dbg_assert_(IsValidReg(mipsReg));
+ _dbg_assert_(mr[mipsReg].loc == MIPSLoc::RVREG || mr[mipsReg].loc == MIPSLoc::RVREG_IMM || mr[mipsReg].loc == MIPSLoc::RVREG_AS_PTR);
+ if (mr[mipsReg].loc == MIPSLoc::RVREG_AS_PTR) {
+ return mr[mipsReg].reg;
+ } else if (mr[mipsReg].loc == MIPSLoc::RVREG || mr[mipsReg].loc == MIPSLoc::RVREG_IMM) {
+ int rv = mr[mipsReg].reg;
+ _dbg_assert_(ar[rv].pointerified);
+ if (ar[rv].pointerified) {
+ return mr[mipsReg].reg;
+ } else {
+ ERROR_LOG(JIT, "Tried to use a non-pointer register as a pointer");
+ return INVALID_REG;
+ }
+ } else {
+ ERROR_LOG_REPORT(JIT, "Reg %i not in riscv reg", mipsReg);
+ return INVALID_REG; // BAAAD
+ }
+}
diff --git a/Core/MIPS/RiscV/RiscVRegCache.h b/Core/MIPS/RiscV/RiscVRegCache.h
index a52eb95ec9..644687c40f 100644
--- a/Core/MIPS/RiscV/RiscVRegCache.h
+++ b/Core/MIPS/RiscV/RiscVRegCache.h
@@ -18,6 +18,7 @@
#pragma once
#include "Common/RiscVEmitter.h"
+#include "Core/MIPS/MIPS.h"
namespace RiscVJitConstants {
@@ -32,4 +33,138 @@ const RiscVGen::RiscVReg MEMBASEREG = RiscVGen::X27;
const RiscVGen::RiscVReg SCRATCH1 = RiscVGen::X10;
const RiscVGen::RiscVReg SCRATCH2 = RiscVGen::X11;
+// Have to account for all of them due to temps, etc.
+constexpr int TOTAL_MAPPABLE_MIPSREGS = 256;
+
+enum class MIPSLoc {
+ IMM,
+ RVREG,
+ // In a native reg, but an adjusted pointer (not pointerified - unaligned.)
+ RVREG_AS_PTR,
+ // In a native reg, but also has a known immediate value.
+ RVREG_IMM,
+ MEM,
+};
+
+// Initing is the default so the flag is reversed.
+enum {
+ MAP_DIRTY = 1,
+ MAP_NOINIT = 2 | MAP_DIRTY,
+};
+
} // namespace RiscVJitConstants
+
+namespace MIPSAnalyst {
+struct AnalysisResults;
+};
+
+namespace MIPSComp {
+struct JitOptions;
+}
+
+// Not using IRReg since this can be -1.
+typedef int IRRegIndex;
+constexpr IRRegIndex IRREG_INVALID = -1;
+
+struct RegStatusRiscV {
+ IRRegIndex mipsReg; // if -1, no mipsreg attached.
+ bool isDirty; // Should the register be written back?
+ bool pointerified; // Has added the memory base into the top part of the reg. Note - still usable as 32-bit reg (in some cases.)
+ bool tempLocked; // Reserved for a temp register.
+};
+
+struct RegStatusMIPS {
+ // Where is this MIPS register?
+ RiscVJitConstants::MIPSLoc loc;
+ // Data (both or only one may be used, depending on loc.)
+ u64 imm;
+ RiscVGen::RiscVReg reg; // reg index
+ bool spillLock; // if true, this register cannot be spilled.
+ bool isStatic; // if true, this register will not be written back to ram by the regcache
+ // If loc == ML_MEM, it's back in its location in the CPU context struct.
+};
+
+class RiscVRegCache {
+public:
+ RiscVRegCache(MIPSState *mipsState, MIPSComp::JitOptions *jo);
+ ~RiscVRegCache() {}
+
+ void Init(RiscVGen::RiscVEmitter *emitter);
+ // TODO: Maybe pass in IR block and start PC for logging/debugging?
+ void Start();
+
+ // Protect the arm register containing a MIPS register from spilling, to ensure that
+ // it's being kept allocated.
+ void SpillLock(IRRegIndex reg, IRRegIndex reg2 = IRREG_INVALID, IRRegIndex reg3 = IRREG_INVALID, IRRegIndex reg4 = IRREG_INVALID);
+ void ReleaseSpillLock(IRRegIndex reg, IRRegIndex reg2 = IRREG_INVALID, IRRegIndex reg3 = IRREG_INVALID, IRRegIndex reg4 = IRREG_INVALID);
+ void ReleaseSpillLocksAndDiscardTemps();
+
+ void SetImm(IRRegIndex reg, u64 immVal);
+ bool IsImm(IRRegIndex reg) const;
+ bool IsPureImm(IRRegIndex reg) const;
+ u64 GetImm(IRRegIndex reg) const;
+ // Optimally set a register to an imm value (possibly using another register.)
+ void SetRegImm(RiscVGen::RiscVReg reg, u64 imm);
+
+ // May fail and return INVALID_REG if it needs flushing.
+ RiscVGen::RiscVReg TryMapTempImm(IRRegIndex);
+
+ // Returns an ARM register containing the requested MIPS register.
+ RiscVGen::RiscVReg MapReg(IRRegIndex reg, int mapFlags = 0);
+ RiscVGen::RiscVReg MapRegAsPointer(IRRegIndex reg);
+
+ bool IsMapped(IRRegIndex reg);
+ bool IsMappedAsPointer(IRRegIndex reg);
+ bool IsInRAM(IRRegIndex reg);
+
+ void MarkDirty(RiscVGen::RiscVReg reg);
+ void MapIn(IRRegIndex rs);
+ void MapInIn(IRRegIndex rd, IRRegIndex rs);
+ void MapDirtyIn(IRRegIndex rd, IRRegIndex rs, bool avoidLoad = true);
+ void MapDirtyInIn(IRRegIndex rd, IRRegIndex rs, IRRegIndex rt, bool avoidLoad = true);
+ void MapDirtyDirtyIn(IRRegIndex rd1, IRRegIndex rd2, IRRegIndex rs, bool avoidLoad = true);
+ void MapDirtyDirtyInIn(IRRegIndex rd1, IRRegIndex rd2, IRRegIndex rs, IRRegIndex rt, bool avoidLoad = true);
+ void FlushRiscVReg(RiscVGen::RiscVReg r);
+ void FlushBeforeCall();
+ void FlushAll();
+ void FlushR(IRRegIndex r);
+ void DiscardR(IRRegIndex r);
+
+ RiscVGen::RiscVReg GetAndLockTempR();
+
+ RiscVGen::RiscVReg R(IRRegIndex preg); // Returns a cached register, while checking that it's NOT mapped as a pointer
+ RiscVGen::RiscVReg RPtr(IRRegIndex preg); // Returns a cached register, if it has been mapped as a pointer
+
+ // These are called once on startup to generate functions, that you should then call.
+ void EmitLoadStaticRegisters();
+ void EmitSaveStaticRegisters();
+
+private:
+ struct StaticAllocation {
+ IRRegIndex mr;
+ RiscVGen::RiscVReg ar;
+ bool pointerified;
+ };
+ const StaticAllocation *GetStaticAllocations(int &count);
+ const RiscVGen::RiscVReg *GetMIPSAllocationOrder(int &count);
+ void MapRegTo(RiscVGen::RiscVReg reg, IRRegIndex mipsReg, int mapFlags);
+ RiscVGen::RiscVReg AllocateReg();
+ RiscVGen::RiscVReg FindBestToSpill(bool unusedOnly, bool *clobbered);
+ RiscVGen::RiscVReg RiscVRegForFlush(IRRegIndex r);
+ int GetMipsRegOffset(IRRegIndex r);
+
+ bool IsValidReg(IRRegIndex r) const;
+ bool IsValidRegNoZero(IRRegIndex r) const;
+
+ MIPSState *mips_;
+ RiscVGen::RiscVEmitter *emit_ = nullptr;
+ MIPSComp::JitOptions *jo_;
+
+ enum {
+ NUM_RVREG = 32, // 31 actual registers, plus the zero/sp register which is not mappable.
+ NUM_MIPSREG = RiscVJitConstants::TOTAL_MAPPABLE_MIPSREGS,
+ };
+
+ RegStatusRiscV ar[NUM_RVREG]{};
+ RegStatusMIPS mr[NUM_MIPSREG]{};
+};
diff --git a/Core/MIPS/RiscV/RiscVRegCacheFPU.cpp b/Core/MIPS/RiscV/RiscVRegCacheFPU.cpp
new file mode 100644
index 0000000000..7287ea10b7
--- /dev/null
+++ b/Core/MIPS/RiscV/RiscVRegCacheFPU.cpp
@@ -0,0 +1,16 @@
+// Copyright (c) 2023- PPSSPP Project.
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, version 2.0 or later versions.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License 2.0 for more details.
+
+// A copy of the GPL 2.0 should have been included with the program.
+// If not, see http://www.gnu.org/licenses/
+
+// Official git repository and contact information can be found at
+// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
diff --git a/Core/MIPS/RiscV/RiscVRegCacheFPU.h b/Core/MIPS/RiscV/RiscVRegCacheFPU.h
new file mode 100644
index 0000000000..48b5ab53e0
--- /dev/null
+++ b/Core/MIPS/RiscV/RiscVRegCacheFPU.h
@@ -0,0 +1,18 @@
+// Copyright (c) 2023- PPSSPP Project.
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, version 2.0 or later versions.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License 2.0 for more details.
+
+// A copy of the GPL 2.0 should have been included with the program.
+// If not, see http://www.gnu.org/licenses/
+
+// Official git repository and contact information can be found at
+// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
+
+#pragma once