diff --git a/Core/MIPS/ARM/ArmCompLoadStore.cpp b/Core/MIPS/ARM/ArmCompLoadStore.cpp
index 920c53139b..b88fb40979 100644
--- a/Core/MIPS/ARM/ArmCompLoadStore.cpp
+++ b/Core/MIPS/ARM/ArmCompLoadStore.cpp
@@ -376,4 +376,10 @@ namespace MIPSComp
 		}
 
 	}
+
+	void Jit::Comp_Cache(MIPSOpcode op) {
+		CONDITIONAL_DISABLE;
+		// TODO: Could use this as a hint, and technically required to handle icache, etc.
+		// But right now Int_Cache does nothing, so let's not even call it.
+	}
 }
diff --git a/Core/MIPS/ARM/ArmJit.h b/Core/MIPS/ARM/ArmJit.h
index ce2e7c8022..189865153e 100644
--- a/Core/MIPS/ARM/ArmJit.h
+++ b/Core/MIPS/ARM/ArmJit.h
@@ -67,6 +67,7 @@ public:
 
 	// Ops
 	void Comp_ITypeMem(MIPSOpcode op);
+	void Comp_Cache(MIPSOpcode op);
 
 	void Comp_RelBranch(MIPSOpcode op);
 	void Comp_RelBranchRI(MIPSOpcode op);
diff --git a/Core/MIPS/MIPSTables.cpp b/Core/MIPS/MIPSTables.cpp
index dd60fb4758..b8c437e3bf 100644
--- a/Core/MIPS/MIPSTables.cpp
+++ b/Core/MIPS/MIPSTables.cpp
@@ -147,7 +147,7 @@ const MIPSInstruction tableImmediate[64] = // xxxxxx ..... ..... ...............
 	INVALID,
 	INVALID,
 	INSTR("swr", &Jit::Comp_ITypeMem, Dis_ITypeMem, Int_ITypeMem, IN_IMM16|IN_RS_ADDR|IN_RT|OUT_MEM|MEMTYPE_WORD),
-	INSTR("cache", &Jit::Comp_Generic, Dis_Generic, Int_Cache, IN_MEM|IN_IMM16|IN_RS_ADDR|IN_OTHER|OUT_OTHER),
+	INSTR("cache", &Jit::Comp_Cache, Dis_Generic, Int_Cache, IN_MEM|IN_IMM16|IN_RS_ADDR|IN_OTHER|OUT_OTHER),
 	//48
 	INSTR("ll", &Jit::Comp_Generic, Dis_Generic, Int_StoreSync, IN_MEM|IN_IMM16|IN_RS_ADDR|OUT_RT|OUT_OTHER|MEMTYPE_WORD),
 	INSTR("lwc1", &Jit::Comp_FPULS, Dis_FPULS, Int_FPULS, IN_MEM|IN_IMM16|IN_RS_ADDR|OUT_OTHER|MEMTYPE_FLOAT),
diff --git a/Core/MIPS/PPC/PpcCompLoadStore.cpp b/Core/MIPS/PPC/PpcCompLoadStore.cpp
index 6f266cfb8e..a061cca748 100644
--- a/Core/MIPS/PPC/PpcCompLoadStore.cpp
+++ b/Core/MIPS/PPC/PpcCompLoadStore.cpp
@@ -140,3 +140,9 @@ void Jit::Comp_ITypeMem(MIPSOpcode op) {
 		}
 	}
 }
+
+void Jit::Comp_Cache(MIPSOpcode op) {
+	CONDITIONAL_DISABLE;
+	// TODO: Could use this as a hint, and technically required to handle icache, etc.
+	// But right now Int_Cache does nothing, so let's not even call it.
+}
diff --git a/Core/MIPS/PPC/PpcJit.h b/Core/MIPS/PPC/PpcJit.h
index d5c430846a..aef427332b 100644
--- a/Core/MIPS/PPC/PpcJit.h
+++ b/Core/MIPS/PPC/PpcJit.h
@@ -176,6 +176,7 @@ namespace MIPSComp
 
 		// Ops
 		void Comp_ITypeMem(MIPSOpcode op);
+		void Comp_Cache(MIPSOpcode op);
 
 		void Comp_RelBranch(MIPSOpcode op);
 		void Comp_RelBranchRI(MIPSOpcode op);
diff --git a/Core/MIPS/x86/CompLoadStore.cpp b/Core/MIPS/x86/CompLoadStore.cpp
index 5077e9dbb2..29e9df1c21 100644
--- a/Core/MIPS/x86/CompLoadStore.cpp
+++ b/Core/MIPS/x86/CompLoadStore.cpp
@@ -370,4 +370,8 @@ namespace MIPSComp
 		}
 
 	}
+
+	void Jit::Comp_Cache(MIPSOpcode op) {
+		DISABLE;
+	}
 }
diff --git a/Core/MIPS/x86/Jit.h b/Core/MIPS/x86/Jit.h
index 628d8c6d5d..692f472755 100644
--- a/Core/MIPS/x86/Jit.h
+++ b/Core/MIPS/x86/Jit.h
@@ -84,6 +84,7 @@ public:
 
 	// Ops
 	void Comp_ITypeMem(MIPSOpcode op);
+	void Comp_Cache(MIPSOpcode op);
 
 	void Comp_RelBranch(MIPSOpcode op);
 	void Comp_RelBranchRI(MIPSOpcode op);