diff --git a/Core/MIPS/PPC/PpcCompFpu.cpp b/Core/MIPS/PPC/PpcCompFpu.cpp
index 972423d309..b52c131495 100644
--- a/Core/MIPS/PPC/PpcCompFpu.cpp
+++ b/Core/MIPS/PPC/PpcCompFpu.cpp
@@ -1,4 +1,5 @@
 #include "Common/ChunkFile.h"
+#include "Core/Config.h"
 #include "Core/Core.h"
 #include "Core/CoreTiming.h"
 #include "Core/MIPS/MIPS.h"
@@ -67,6 +68,10 @@ void Jit::Comp_FPULS(MIPSOpcode op) {
 	// logBlocks = 1;
 	bool doCheck = false;
 
+	if (!g_Config.bFastMemory) {
+		DISABLE;
+	}
+
 	switch(op >> 26)
 	{
 	case 49: //FI(ft) = Memory::Read_U32(addr); break; //lwc1
diff --git a/Core/MIPS/PPC/PpcCompLoadStore.cpp b/Core/MIPS/PPC/PpcCompLoadStore.cpp
index a061cca748..a83c53ce7c 100644
--- a/Core/MIPS/PPC/PpcCompLoadStore.cpp
+++ b/Core/MIPS/PPC/PpcCompLoadStore.cpp
@@ -1,4 +1,5 @@
 #include "Common/ChunkFile.h"
+#include "Core/Config.h"
 #include "Core/Core.h"
 #include "Core/CoreTiming.h"
 #include "Core/MIPS/MIPS.h"
@@ -43,6 +44,7 @@ void Jit::SetRegToEffectiveAddress(PpcGen::PPCReg r, int rs, s16 offset) {
 }
 void Jit::Comp_ITypeMem(MIPSOpcode op) {
 	CONDITIONAL_DISABLE;
+
 		int offset = (signed short)(op&0xFFFF);
 		bool load = false;
 		int rt = _RT;
@@ -53,6 +55,10 @@ void Jit::Comp_ITypeMem(MIPSOpcode op) {
 			return;
 		}
 
+		if (!g_Config.bFastMemory) {
+			DISABLE;
+		}
+
 		u32 iaddr = gpr.IsImm(rs) ? offset + gpr.GetImm(rs) : 0xFFFFFFFF;
 		bool doCheck = false;
 
diff --git a/Core/MIPS/PPC/PpcCompVFPU.cpp b/Core/MIPS/PPC/PpcCompVFPU.cpp
index d90146cf6c..df376a2f34 100644
--- a/Core/MIPS/PPC/PpcCompVFPU.cpp
+++ b/Core/MIPS/PPC/PpcCompVFPU.cpp
@@ -2,6 +2,7 @@
 #include "math/math_util.h"
 
 #include "Common/ChunkFile.h"
+#include "Core/Config.h"
 #include "Core/Core.h"
 #include "Core/CoreTiming.h"
 #include "Core/MIPS/MIPS.h"
@@ -173,6 +174,10 @@ namespace MIPSComp
 		int vt = ((op >> 16) & 0x1f) | ((op & 3) << 5);
 		int rs = _RS;
 
+		if (!g_Config.bFastMemory) {
+			DISABLE;
+		}
+
 		bool doCheck = false;
 		switch (op >> 26)
 		{
@@ -221,6 +226,10 @@ namespace MIPSComp
 		int vt = (((op >> 16) & 0x1f)) | ((op&1) << 5);
 		int rs = _RS;
 
+		if (!g_Config.bFastMemory) {
+			DISABLE;
+		}
+
 		bool doCheck = false;
 		switch (op >> 26)
 		{