From 4100767b5e744d9043a94b6d7d239eccb990c780 Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Sun, 23 Jul 2023 09:52:05 -0700
Subject: [PATCH] riscv: Optimize SetConst a bit.

---
 Core/MIPS/RiscV/RiscVCompSystem.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Core/MIPS/RiscV/RiscVCompSystem.cpp b/Core/MIPS/RiscV/RiscVCompSystem.cpp
index 6c3bd07f78..63eb555d31 100644
--- a/Core/MIPS/RiscV/RiscVCompSystem.cpp
+++ b/Core/MIPS/RiscV/RiscVCompSystem.cpp
@@ -39,7 +39,9 @@ void RiscVJit::CompIR_Basic(IRInst inst) {
 
 	switch (inst.op) {
 	case IROp::SetConst:
-		gpr.SetImm(inst.dest, inst.constant);
+		// Sign extend all constants.  We get 0xFFFFFFFF sometimes, and it's more work to truncate.
+		// The register only holds 32 bits in the end anyway.
+		gpr.SetImm(inst.dest, (int32_t)inst.constant);
 		break;
 
 	case IROp::SetConstF: