From 32c95af820a83fa2bf4a45f77338e0a128c1bb00 Mon Sep 17 00:00:00 2001
From: Henrik Rydgard <hrydgard@gmail.com>
Date: Thu, 7 Nov 2013 13:38:25 +0100
Subject: [PATCH] ARM: Some zero-register fixes

---
 Core/MIPS/ARM/ArmCompALU.cpp       |  2 +-
 Core/MIPS/ARM/ArmCompLoadStore.cpp |  3 +--
 Core/MIPS/ARM/ArmRegCache.cpp      | 28 ++++++++++++++++------------
 3 files changed, 18 insertions(+), 15 deletions(-)

diff --git a/Core/MIPS/ARM/ArmCompALU.cpp b/Core/MIPS/ARM/ArmCompALU.cpp
index 4e4f67f004..6aefbff4f3 100644
--- a/Core/MIPS/ARM/ArmCompALU.cpp
+++ b/Core/MIPS/ARM/ArmCompALU.cpp
@@ -55,7 +55,7 @@ namespace MIPSComp
 			gpr.SetImm(rt, (*eval)(gpr.GetImm(rs), uimm));
 		} else {
 			gpr.MapDirtyIn(rt, rs);
-			// TODO: Special case when uimm can be represented as an Operand2
+			// Special case when uimm can be represented as an Operand2
 			Operand2 op2;
 			if (TryMakeOperand2(uimm, op2)) {
 				(this->*arith)(gpr.R(rt), gpr.R(rs), op2);
diff --git a/Core/MIPS/ARM/ArmCompLoadStore.cpp b/Core/MIPS/ARM/ArmCompLoadStore.cpp
index c60be3f779..0f24287165 100644
--- a/Core/MIPS/ARM/ArmCompLoadStore.cpp
+++ b/Core/MIPS/ARM/ArmCompLoadStore.cpp
@@ -142,8 +142,7 @@ namespace MIPSComp
 		u32 iaddr = gpr.IsImm(rs) ? offset + gpr.GetImm(rs) : 0xFFFFFFFF;
 		bool doCheck = false;
 
-		switch (o)
-		{
+		switch (o) {
 		case 32: //lb
 		case 33: //lh
 		case 35: //lw
diff --git a/Core/MIPS/ARM/ArmRegCache.cpp b/Core/MIPS/ARM/ArmRegCache.cpp
index e1405220b0..c1573a77c6 100644
--- a/Core/MIPS/ARM/ArmRegCache.cpp
+++ b/Core/MIPS/ARM/ArmRegCache.cpp
@@ -103,17 +103,17 @@ allocate:
 			// That means it's free. Grab it, and load the value into it (if requested).
 			ar[reg].isDirty = (mapFlags & MAP_DIRTY) ? true : false;
 			if (!(mapFlags & MAP_NOINIT)) {
-				if (mr[mipsReg].loc == ML_MEM) {
-					if (mipsReg != 0) {
+				if (mipsReg == 0) {
+					// If we get a request to load the zero register, at least we won't spend
+					// time on a memory access...
+					emit_->MOV((ARMReg)reg, 0);
+				} else {
+					if (mr[mipsReg].loc == ML_MEM) {
 						emit_->LDR((ARMReg)reg, CTXREG, GetMipsRegOffset(mipsReg));
-					} else {
-						// If we get a request to load the zero register, at least we won't spend
-						// time on a memory access...
-						emit_->MOV((ARMReg)reg, 0);
+					} else if (mr[mipsReg].loc == ML_IMM) {
+						emit_->MOVI2R((ARMReg)reg, mr[mipsReg].imm);
+						ar[reg].isDirty = true;  // IMM is always dirty.
 					}
-				} else if (mr[mipsReg].loc == ML_IMM) {
-					emit_->MOVI2R((ARMReg)reg, mr[mipsReg].imm);
-					ar[reg].isDirty = true;  // IMM is always dirty.
 				}
 			}
 			ar[reg].mipsReg = mipsReg;
@@ -204,8 +204,10 @@ void ArmRegCache::FlushR(MIPSReg r) {
 	switch (mr[r].loc) {
 	case ML_IMM:
 		// IMM is always "dirty".
-		emit_->MOVI2R(R0, mr[r].imm);
-		emit_->STR(R0, CTXREG, GetMipsRegOffset(r));
+		if (r != 0) {
+			emit_->MOVI2R(R0, mr[r].imm);
+			emit_->STR(R0, CTXREG, GetMipsRegOffset(r));
+		}
 		break;
 
 	case ML_ARMREG:
@@ -213,7 +215,9 @@ void ArmRegCache::FlushR(MIPSReg r) {
 			ERROR_LOG(JIT, "FlushMipsReg: MipsReg had bad ArmReg");
 		}
 		if (ar[mr[r].reg].isDirty) {
-			emit_->STR((ARMReg)mr[r].reg, CTXREG, GetMipsRegOffset(r));
+			if (r != 0) {
+				emit_->STR((ARMReg)mr[r].reg, CTXREG, GetMipsRegOffset(r));
+			}
 			ar[mr[r].reg].isDirty = false;
 		}
 		ar[mr[r].reg].mipsReg = -1;