diff --git a/Common/ArmEmitter.cpp b/Common/ArmEmitter.cpp
index 15c60f8a6f..80cb17f91a 100644
--- a/Common/ArmEmitter.cpp
+++ b/Common/ArmEmitter.cpp
@@ -580,7 +580,17 @@ void ARMXEmitter::LDRH(ARMReg dest, ARMReg src, Operand2 op)
 	u8 Imm = op.Imm8();
 	Write32(condition | (0x05 << 20) | (src << 16) | (dest << 12) | ((Imm >> 4) << 8) | (0xB << 4) | (Imm & 0x0F));
 }
+void ARMXEmitter::LDRSH(ARMReg dest, ARMReg src, Operand2 op)
+{
+	u8 Imm = op.Imm8();
+	Write32(condition | (0x05 << 20) | (src << 16) | (dest << 12) | ((Imm >> 4) << 8) | (0xF << 4) | (Imm & 0x0F));
+}
 void ARMXEmitter::LDRB(ARMReg dest, ARMReg src, Operand2 op) { WriteStoreOp(0x45, src, dest, op);}
+void ARMXEmitter::LDRSB(ARMReg dest, ARMReg src, Operand2 op)
+{
+	u8 Imm = op.Imm8();
+	Write32(condition | (0x05 << 20) | (src << 16) | (dest << 12) | ((Imm >> 4) << 8) | (0xD << 4) | (Imm & 0x0F));
+}
 
 void ARMXEmitter::LDR (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add)
 {
diff --git a/Common/ArmEmitter.h b/Common/ArmEmitter.h
index 90160707e1..fbf6363385 100644
--- a/Common/ArmEmitter.h
+++ b/Common/ArmEmitter.h
@@ -469,7 +469,9 @@ public:
 	// Memory load/store operations
 	void LDR (ARMReg dest, ARMReg src, Operand2 op2 = 0);
 	void LDRH(ARMReg dest, ARMReg src, Operand2 op2 = 0);
+	void LDRSH(ARMReg dest, ARMReg src, Operand2 op2 = 0);
 	void LDRB(ARMReg dest, ARMReg src, Operand2 op2 = 0);
+	void LDRBH(ARMReg dest, ARMReg src, Operand2 op2 = 0);
 	// Offset adds to the base register in LDR
 	void LDR (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
 	void LDRB (ARMReg dest, ARMReg base, ARMReg offset, bool Index, bool Add);
diff --git a/Core/MIPS/ARM/ArmCompLoadStore.cpp b/Core/MIPS/ARM/ArmCompLoadStore.cpp
index db7e843474..8794545383 100644
--- a/Core/MIPS/ARM/ArmCompLoadStore.cpp
+++ b/Core/MIPS/ARM/ArmCompLoadStore.cpp
@@ -94,6 +94,8 @@ namespace MIPSComp
 		}
 		switch (o)
 		{
+		case 32: //R(rt) = (u32)(s32)(s8) ReadMem8 (addr); break; //lb
+		case 33: //R(rt) = (u32)(s32)(s16)ReadMem16(addr); break; //lh
 		case 35: //R(rt) = ReadMem32(addr); break; //lw
 		case 36: //R(rt) = ReadMem8 (addr); break; //lbu
 		case 37: //R(rt) = ReadMem16(addr); break; //lhu
@@ -108,12 +110,21 @@ namespace MIPSComp
 					SetR0ToEffectiveAddress(rs, offset);
 				}
 				if (o == 35) {
+					// 32-bit
 					LDR(gpr.R(rt), R11, R0, true, true);
-				} else if (o == 36) {
-					LDRB(gpr.R(rt), R11, R0, true, true);
 				} else if (o == 37) {
+					// 16-bit
 					ADD(R0, R0, R11);   // TODO: Merge with next instruction
 					LDRH(gpr.R(rt), R0);
+				} else if (o == 33) {
+					ADD(R0, R0, R11);   // TODO: Merge with next instruction
+					LDRSH(gpr.R(rt), R0);
+				} else if (o == 36) {
+					// 8-bit
+					LDRB(gpr.R(rt), R11, R0, true, true);
+				} else if (o == 32) {
+					ADD(R0, R0, R11);   // TODO: Merge with next instruction
+					LDRSB(gpr.R(rt), R0);
 				}
 			} else {
 				Comp_Generic(op);