From 26f5922174e8ebb1c8a1859817a20044b035b12f Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Wed, 13 Nov 2013 22:41:25 -0800
Subject: [PATCH] Return the correct value for fcr0/fir.

This is what the PSP actually returns, it's read only.
---
 Core/HLE/sceKernelThread.cpp |  8 ++++++--
 Core/HLE/sceKernelThread.h   |  1 -
 Core/MIPS/ARM/ArmCompFPU.cpp | 10 +++-------
 Core/MIPS/MIPS.cpp           | 10 ++++++----
 Core/MIPS/MIPS.h             |  3 ++-
 5 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/Core/HLE/sceKernelThread.cpp b/Core/HLE/sceKernelThread.cpp
index a2dcc48858..85a5d2348f 100644
--- a/Core/HLE/sceKernelThread.cpp
+++ b/Core/HLE/sceKernelThread.cpp
@@ -520,7 +520,7 @@ public:
 
 	virtual void DoState(PointerWrap &p)
 	{
-		auto s = p.Section("Thread", 1, 2);
+		auto s = p.Section("Thread", 1, 3);
 		if (!s)
 			return;
 
@@ -531,6 +531,11 @@ public:
 		p.Do(currentMipscallId);
 		p.Do(currentCallbackId);
 		p.Do(context);
+		if (s <= 2)
+		{
+			context.other[4] = context.other[5];
+			context.other[3] = context.other[4];
+		}
 
 		p.Do(callbacks);
 
@@ -1928,7 +1933,6 @@ void ThreadContext::reset()
 	vfpuCtrl[VFPU_CTRL_RCX6] = 0x3f800000;
 	vfpuCtrl[VFPU_CTRL_RCX7] = 0x3f800000;
 	fpcond = 0;
-	fcr0 = 0;
 	fcr31 = 0;
 	hi = 0xDEADBEEF;
 	lo = 0xDEADBEEF;
diff --git a/Core/HLE/sceKernelThread.h b/Core/HLE/sceKernelThread.h
index 4562509f70..b33582b589 100644
--- a/Core/HLE/sceKernelThread.h
+++ b/Core/HLE/sceKernelThread.h
@@ -132,7 +132,6 @@ struct ThreadContext
 			u32 hi;
 			u32 lo;
 
-			u32 fcr0;
 			u32 fcr31;
 			u32 fpcond;
 		};
diff --git a/Core/MIPS/ARM/ArmCompFPU.cpp b/Core/MIPS/ARM/ArmCompFPU.cpp
index f615808b4a..47ec38c4cf 100644
--- a/Core/MIPS/ARM/ArmCompFPU.cpp
+++ b/Core/MIPS/ARM/ArmCompFPU.cpp
@@ -339,8 +339,7 @@ void Jit::Comp_mxc1(MIPSOpcode op)
 		return;
 
 	case 2: //cfc1
-		if (fs == 31)
-		{
+		if (fs == 31) {
 			gpr.MapDirtyIn(rt, MIPS_REG_FPCOND);
 			LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr31));
 #ifdef HAVE_ARMV7
@@ -350,11 +349,8 @@ void Jit::Comp_mxc1(MIPSOpcode op)
 			ANDI2R(gpr.R(rt), gpr.R(rt), ~(0x1 << 23), R1);  // R1 won't be used, this turns into a simple BIC.
 			ORR(gpr.R(rt), gpr.R(rt), Operand2(R0, ST_LSL, 23));
 #endif
-		}
-		else if (fs == 0)
-		{
-			gpr.MapReg(rt, MAP_DIRTY | MAP_NOINIT);
-			LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, fcr0));
+		} else if (fs == 0) {
+			gpr.SetImm(rt, MIPSState::FCR0_VALUE);
 		}
 		return;
 
diff --git a/Core/MIPS/MIPS.cpp b/Core/MIPS/MIPS.cpp
index f1a4214e1f..153a2f4155 100644
--- a/Core/MIPS/MIPS.cpp
+++ b/Core/MIPS/MIPS.cpp
@@ -134,7 +134,6 @@ void MIPSState::Reset()
 	hi = 0;
 	lo = 0;
 	fpcond = 0;
-	fcr0 = 0;
 	fcr31 = 0;
 	debugCount = 0;
 	currentMIPS = this;
@@ -147,7 +146,7 @@ void MIPSState::Reset()
 }
 
 void MIPSState::DoState(PointerWrap &p) {
-	auto s = p.Section("MIPSState", 1);
+	auto s = p.Section("MIPSState", 1, 2);
 	if (!s)
 		return;
 
@@ -169,7 +168,10 @@ void MIPSState::DoState(PointerWrap &p) {
 	p.Do(hi);
 	p.Do(lo);
 	p.Do(fpcond);
-	p.Do(fcr0);
+	if (s <= 1) {
+		u32 fcr0_unusued = 0;
+		p.Do(fcr0_unusued);
+	}
 	p.Do(fcr31);
 	p.Do(rng.m_w);
 	p.Do(rng.m_z);
@@ -225,7 +227,7 @@ u32 MIPSState::ReadFCR(int reg)
 	}
 	else if (reg == 0)
 	{
-		return fcr0;
+		return FCR0_VALUE;
 	}
 	else
 	{
diff --git a/Core/MIPS/MIPS.h b/Core/MIPS/MIPS.h
index 53b2349ce0..84c047c64b 100644
--- a/Core/MIPS/MIPS.h
+++ b/Core/MIPS/MIPS.h
@@ -146,7 +146,6 @@ public:
 			u32 hi;
 			u32 lo;
 
-			u32 fcr0;
 			u32 fcr31; //fpu control register
 			u32 fpcond;  // cache the cond flag of fcr31  (& 1 << 23)
 		};
@@ -165,6 +164,8 @@ public:
 	// Debug stuff
 	u32 debugCount;	// can be used to count basic blocks before crashes, etc.
 
+	static const u32 FCR0_VALUE = 0x00003351;
+
 	void WriteFCR(int reg, int value);
 	u32 ReadFCR(int reg);