diff --git a/CMakeLists.txt b/CMakeLists.txt index 19a2ab8893..8d2e359ec8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -600,6 +600,8 @@ source_group(RISCV64 FILES ${CommonRISCV64}) set(CommonLOONGARCH64 ${CommonJIT} Common/LoongArchCPUDetect.cpp + Common/LoongArch64Emitter.cpp + Common/LoongArch64Emitter.h Core/MIPS/fake/FakeJit.cpp Core/MIPS/fake/FakeJit.h ) @@ -1825,6 +1827,20 @@ list(APPEND CoreExtra GPU/Common/VertexDecoderRiscV.cpp ) +list(APPEND CoreExtra + Core/MIPS/LoongArch64/LoongArch64Asm.cpp + Core/MIPS/LoongArch64/LoongArch64CompALU.cpp + Core/MIPS/LoongArch64/LoongArch64CompBranch.cpp + Core/MIPS/LoongArch64/LoongArch64CompFPU.cpp + Core/MIPS/LoongArch64/LoongArch64CompLoadStore.cpp + Core/MIPS/LoongArch64/LoongArch64CompSystem.cpp + Core/MIPS/LoongArch64/LoongArch64CompVec.cpp + Core/MIPS/LoongArch64/LoongArch64Jit.cpp + Core/MIPS/LoongArch64/LoongArch64Jit.h + Core/MIPS/LoongArch64/LoongArch64RegCache.cpp + Core/MIPS/LoongArch64/LoongArch64RegCache.h +) + if(NOT MOBILE_DEVICE) set(CoreExtra ${CoreExtra} Core/AVIDump.cpp @@ -2436,6 +2452,8 @@ add_library(${CoreLibName} ${CoreLinkType} ext/disarm.h ext/riscv-disas.cpp ext/riscv-disas.h + ext/loongarch-disasm.cpp + ext/loongarch-disasm.h ${CMAKE_CURRENT_BINARY_DIR}/git-version.cpp ) @@ -2810,6 +2828,7 @@ if(UNITTEST) unittest/TestVertexJit.cpp unittest/TestVFS.cpp unittest/TestRiscVEmitter.cpp + unittest/TestLoongArch64Emitter.cpp unittest/TestSoftwareGPUJit.cpp unittest/TestThreadManager.cpp unittest/JitHarness.cpp diff --git a/Common/Common.vcxproj b/Common/Common.vcxproj index 0a43b74b4b..7bea24a69d 100644 --- a/Common/Common.vcxproj +++ b/Common/Common.vcxproj @@ -440,6 +440,7 @@ + @@ -897,6 +898,7 @@ + diff --git a/Common/Common.vcxproj.filters b/Common/Common.vcxproj.filters index da68d55a89..10c2cc8417 100644 --- a/Common/Common.vcxproj.filters +++ b/Common/Common.vcxproj.filters @@ -688,6 +688,7 @@ Audio + @@ -1288,6 +1289,7 @@ ext\imgui + diff --git a/Common/CommonFuncs.h b/Common/CommonFuncs.h index 515c4606e8..32b44d3d11 100644 --- a/Common/CommonFuncs.h +++ b/Common/CommonFuncs.h @@ -41,6 +41,8 @@ #define Crash() {asm ("brk #0");} #elif PPSSPP_ARCH(RISCV64) #define Crash() {asm ("ebreak");} +#elif PPSSPP_ARCH(LOONGARCH64) +#define Crash() {asm ("break 0");} #else #include #define Crash() {kill(getpid(), SIGINT);} diff --git a/Common/LoongArch64Emitter.cpp b/Common/LoongArch64Emitter.cpp new file mode 100644 index 0000000000..34814fb142 --- /dev/null +++ b/Common/LoongArch64Emitter.cpp @@ -0,0 +1,6333 @@ +// Copyright (c) 2025- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + + +#include "ppsspp_config.h" +#include +#include +#include "Common/BitScan.h" +#include "Common/CPUDetect.h" +#include "Common/LoongArch64Emitter.h" + +namespace LoongArch64Gen { + +enum class Opcode32 { + // Note: invalid, just used for FixupBranch. + ZERO = 0x0, + + ADD_W = 0x00100000, + ADD_D = 0x00108000, + SUB_W = 0x00110000, + SUB_D = 0x00118000, + + ADDI_W = 0x02800000, + ADDI_D = 0x02c00000, + ADDU16I_D = 0x10000000, + + ALSL_W = 0x00040000, + ALSL_D = 0X002c0000, + ALSL_WU = 0x00060000, + + LU12I_W = 0x14000000, + LU32I_D = 0x16000000, + LU52I_D = 0x03000000, + + SLT = 0x00120000, + SLTU = 0x00128000, + + SLTI = 0x02000000, + SLTUI = 0x02400000, + + PCADDI = 0x18000000, + PCADDU12I = 0x1c000000, + PCADDU18I = 0x1e000000, + PCALAU12I = 0x1a000000, + + AND = 0x00148000, + OR = 0x00150000, + NOR = 0x00140000, + XOR = 0x00158000, + ANDN = 0x00168000, + ORN = 0x00160000, + + ANDI = 0x03400000, + ORI = 0x03800000, + XORI = 0x03c00000, + + MUL_W = 0x001c0000, + MULH_W = 0x001c8000, + MULH_WU = 0x001d0000, + MUL_D = 0x001d8000, + MULH_D = 0x001e0000, + MULH_DU = 0x001e8000, + + MULW_D_W = 0x001f0000, + MULW_D_WU = 0x001f8000, + + DIV_W = 0x00200000, + MOD_W = 0x00208000, + DIV_WU = 0x00210000, + MOD_WU = 0x00218000, + DIV_D = 0x00220000, + MOD_D = 0x00228000, + DIV_DU = 0x00230000, + MOD_DU = 0x00238000, + + SLL_W = 0x00170000, + SRL_W = 0x00178000, + SRA_W = 0x00180000, + ROTR_W = 0x001b0000, + + SLLI_W = 0x00408000, + SRLI_W = 0x00448000, + SRAI_W = 0x00488000, + ROTRI_W = 0x004c8000, + + SLL_D = 0x00188000, + SRL_D = 0x00190000, + SRA_D = 0x00198000, + ROTR_D = 0x001b8000, + + SLLI_D = 0x00410000, + SRLI_D = 0x00450000, + SRAI_D = 0x00490000, + ROTRI_D = 0x004d0000, + + EXT_W_B = 0x00005c00, + EXT_W_H = 0x00005800, + + CLO_W = 0x00001000, + CLO_D = 0x00002000, + CLZ_W = 0x00001400, + CLZ_D = 0x00002400, + CTO_W = 0x00001800, + CTO_D = 0x00002800, + CTZ_W = 0x00001c00, + CTZ_D = 0x00002c00, + + BYTEPICK_W = 0x00080000, + BYTEPICK_D = 0x000c0000, + + REVB_2H = 0x00003000, + REVB_4H = 0x00003400, + REVB_2W = 0x00003800, + REVB_D = 0x00003c00, + + BITREV_4B = 0x00004800, + BITREV_8B = 0x00004c00, + + BITREV_W = 0x00005000, + BITREV_D = 0x00005400, + + BSTRINS_W = 0x00600000, + BSTRINS_D = 0x00800000, + + BSTRPICK_W = 0x00608000, + BSTRPICK_D = 0x00c00000, + + MASKEQZ = 0x00130000, + MASKNEZ = 0x00138000, + + BEQ = 0x58000000, + BNE = 0x5c000000, + BLT = 0x60000000, + BGE = 0x64000000, + BLTU = 0x68000000, + BGEU = 0x6c000000, + + BEQZ = 0x40000000, + BNEZ = 0x44000000, + + B = 0x50000000, + BL = 0x54000000, + + JIRL = 0x4c000000, + + LD_B = 0x28000000, + LD_H = 0x28400000, + LD_W = 0x28800000, + LD_D = 0x28c00000, + LD_BU = 0x2a000000, + LD_HU = 0x2a400000, + LD_WU = 0x2a800000, + ST_B = 0x29000000, + ST_H = 0x29400000, + ST_W = 0x29800000, + ST_D = 0x29c00000, + + LDX_B = 0x38000000, + LDX_H = 0x38040000, + LDX_W = 0x38080000, + LDX_D = 0x380c0000, + LDX_BU = 0x38200000, + LDX_HU = 0x38240000, + LDX_WU = 0x38280000, + STX_B = 0x38100000, + STX_H = 0x38140000, + STX_W = 0x38180000, + STX_D = 0x381c0000, + + LDPTR_W = 0x24000000, + LDPTR_D = 0x26000000, + STPTR_W = 0x25000000, + STPTR_D = 0x27000000, + + PRELD = 0x2ac00000, + PRELDX = 0x382c0000, + + LDGT_B = 0x38780000, + LDGT_H = 0x38788000, + LDGT_W = 0x38790000, + LDGT_D = 0x38798000, + LDLE_B = 0x387a0000, + LDLE_H = 0x387a8000, + LDLE_W = 0x387b0000, + LDLE_D = 0x387b8000, + STGT_B = 0x387c0000, + STGT_H = 0x387c8000, + STGT_W = 0x387d0000, + STGT_D = 0x387d8000, + STLE_B = 0x387e0000, + STLE_H = 0x387e8000, + STLE_W = 0x387f0000, + STLE_D = 0x387f8000, + + AMSWAP_W = 0x38600000, + AMSWAP_DB_W = 0x38690000, + AMSWAP_D = 0x38608000, + AMSWAP_DB_D = 0x38698000, + + AMADD_W = 0x38610000, + AMADD_DB_W = 0x386a0000, + AMADD_D = 0x38618000, + AMADD_DB_D = 0x386a8000, + + AMAND_W = 0x38620000, + AMAND_DB_W = 0x386b0000, + AMAND_D = 0x38628000, + AMAND_DB_D = 0x386b8000, + + AMOR_W = 0x38630000, + AMOR_DB_W = 0x386c0000, + AMOR_D = 0x38638000, + AMOR_DB_D = 0x386c8000, + + AMXOR_W = 0x38640000, + AMXOR_DB_W = 0x386d0000, + AMXOR_D = 0x38648000, + AMXOR_DB_D = 0x386d8000, + + AMMAX_W = 0x38650000, + AMMAX_DB_W = 0x386e0000, + AMMAX_D = 0x38658000, + AMMAX_DB_D = 0x386e8000, + + AMMIN_W = 0x38660000, + AMMIN_DB_W = 0x386f0000, + AMMIN_D = 0x38668000, + AMMIN_DB_D = 0x386f8000, + + AMMAX_WU = 0x38670000, + AMMAX_DB_WU = 0x38700000, + AMMAX_DU = 0x38678000, + AMMAX_DB_DU = 0x38708000, + + AMMIN_WU = 0x38680000, + AMMIN_DB_WU = 0x38710000, + AMMIN_DU = 0x38688000, + AMMIN_DB_DU = 0x38718000, + + AMSWAP_B = 0x385c0000, + AMSWAP_DB_B = 0x385e0000, + AMSWAP_H = 0x385c8000, + AMSWAP_DB_H = 0x385e8000, + + AMADD_B = 0x385d0000, + AMADD_DB_B = 0x385f0000, + AMADD_H = 0x385d8000, + AMADD_DB_H = 0x385f8000, + + AMCAS_B = 0x38580000, + AMCAS_DB_B = 0x385a0000, + AMCAS_H = 0x38588000, + AMCAS_DB_H = 0x385a8000, + AMCAS_W = 0x38590000, + AMCAS_DB_W = 0x385b0000, + AMCAS_D = 0x38598000, + AMCAS_DB_D = 0x38698000, + + CRC_W_B_W = 0x00240000, + CRC_W_H_W = 0x00248000, + CRC_W_W_W = 0x00250000, + CRC_W_D_W = 0x00258000, + CRCC_W_B_W = 0x00260000, + CRCC_W_H_W = 0x00268000, + CRCC_W_W_W = 0x00270000, + CRCC_W_D_W = 0x00278000, + + SYSCALL = 0x002b0000, + BREAK = 0x002a0000, + + ASRTLE_D = 0x00010000, + ASRTGT_D = 0x00018000, + + RDTIMEL_W = 0x00006000, + RDTIMEH_W = 0x00006400, + RDTIME_D = 0x00006800, + + CPUCFG = 0x00006c00, + + FADD_S = 0x01008000, + FADD_D = 0x01010000, + FSUB_S = 0x01028000, + FSUB_D = 0x01030000, + FMUL_S = 0x01048000, + FMUL_D = 0x01050000, + FDIV_S = 0x01068000, + FDIV_D = 0x01070000, + + FMADD_S = 0x08100000, + FMADD_D = 0x08200000, + FMSUB_S = 0x08500000, + FMSUB_D = 0x08600000, + FNMADD_S= 0x08900000, + FNMADD_D= 0x08a00000, + FNMSUB_S= 0x08d00000, + FNMSUB_D= 0x08e00000, + + FMAX_S = 0x01088000, + FMAX_D = 0x01090000, + FMIN_S = 0x010a8000, + FMIN_D = 0x010b0000, + + FMAXA_S = 0x010c8000, + FMAXA_D = 0x010d0000, + FMINA_S = 0x010e8000, + FMINA_D = 0x010f0000, + + FABS_S = 0x01140400, + FABS_D = 0x01140800, + FNEG_S = 0x01141400, + FNEG_D = 0x01141800, + + FSQRT_S = 0x01144400, + FSQRT_D = 0x01144800, + FRECIP_S = 0x01145400, + FRECIP_D = 0x01145800, + FRSQRT_S = 0x01146400, + FRSQRT_D = 0x01146800, + + FSCALEB_S = 0x01108000, + FSCALEB_D = 0x01110000, + FLOGB_S = 0x01142400, + FLOGB_D = 0x01142800, + FCOPYSIGN_S = 0x01128000, + FCOPYSIGN_D = 0x01130000, + + FCLASS_S = 0x01143400, + FCLASS_D = 0x01143800, + FRECIPE_S = 0x01147400, + FRECIPE_D = 0x01147800, + FRSQRTE_S = 0x01148400, + FRSQRTE_D = 0x01148800, + + FCMP_COND_S = 0x0c100000, + FCMP_COND_D = 0x0c200000, + + FCVT_S_D = 0x01191800, + FCVT_D_S = 0x01192400, + + FFINT_S_W = 0x011d1000, + FFINT_S_L = 0x011d1800, + FFINT_D_W = 0x011d2000, + FFINT_D_L = 0x011d2800, + FTINT_W_S = 0x011b0400, + FTINT_W_D = 0x011b0800, + FTINT_L_S = 0x011b2400, + FTINT_L_D = 0x011b2800, + + FTINTRM_W_S = 0x011a0400, + FTINTRM_W_D = 0x011a0800, + FTINTRM_L_S = 0x011a2400, + FTINTRM_L_D = 0x011a2800, + FTINTRP_W_S = 0x011a4400, + FTINTRP_W_D = 0x011a4800, + FTINTRP_L_S = 0x011a6400, + FTINTRP_L_D = 0x011a6800, + FTINTRZ_W_S = 0x011a8400, + FTINTRZ_W_D = 0x011a8800, + FTINTRZ_L_S = 0x011aa400, + FTINTRZ_L_D = 0x011aa800, + FTINTRNE_W_S = 0x011ac400, + FTINTRNE_W_D = 0x011ac800, + FTINTRNE_L_S = 0x011ae400, + FTINTRNE_L_D = 0x011ae800, + + FRINT_S = 0x011e4400, + FRINT_D = 0x011e4800, + + FMOV_S = 0x01149400, + FMOV_D = 0x01149800, + + FSEL = 0x0d000000, + + MOVGR2FR_W = 0x0114a400, + MOVGR2FR_D = 0x00114a800, + MOVGR2FRH_W = 0x0114ac00, + + MOVFR2GR_S = 0x0114b400, + MOVFR2GR_D = 0x0114b800, + MOVFRH2GR_S = 0x0114bc00, + + MOVGR2FCSR = 0x0114c000, + MOVFCSR2GR = 0x0114c800, + + MOVFR2CF = 0x0114d000, + MOVCF2FR = 0x0114d400, + + MOVGR2CF = 0x0114d800, + MOVCF2GR = 0x0114dc00, + + BCEQZ = 0x48000000, + BCNEZ = 0x48000100, + + FLD_S = 0x2b000000, + FLD_D = 0x2b800000, + FST_S = 0x2b400000, + FST_D = 0x2bc00000, + + FLDX_S = 0x38300000, + FLDX_D = 0x38340000, + FSTX_S = 0x38380000, + FSTX_D = 0x383c0000, + + FLDGT_S = 0x38740000, + FLDGT_D = 0x38748000, + FLDLE_S = 0x38750000, + FLDLE_D = 0x38758000, + FSTGT_S = 0x38760000, + FSTGT_D = 0x38768000, + FSTLE_S = 0x38770000, + FSTLE_D = 0x38778000, + + VFMADD_S = 0x09100000, + VFMADD_D = 0x09200000, + VFMSUB_S = 0x09500000, + VFMSUB_D = 0x09600000, + VFNMADD_S = 0x09900000, + VFNMADD_D = 0x09a00000, + VFNMSUB_S = 0x09d00000, + VFNMSUB_D = 0x09e00000, + VFCMP_CAF_S = 0x0c500000, + VFCMP_SAF_S = 0x0c508000, + VFCMP_CLT_S = 0x0c510000, + VFCMP_SLT_S = 0x0c518000, + VFCMP_CEQ_S = 0x0c520000, + VFCMP_SEQ_S = 0x0c528000, + VFCMP_CLE_S = 0x0c530000, + VFCMP_SLE_S = 0x0c538000, + VFCMP_CUN_S = 0x0c540000, + VFCMP_SUN_S = 0x0c548000, + VFCMP_CULT_S = 0x0c550000, + VFCMP_SULT_S = 0x0c558000, + VFCMP_CUEQ_S = 0x0c560000, + VFCMP_SUEQ_S = 0x0c568000, + VFCMP_CULE_S = 0x0c570000, + VFCMP_SULE_S = 0x0c578000, + VFCMP_CNE_S = 0x0c580000, + VFCMP_SNE_S = 0x0c588000, + VFCMP_COR_S = 0x0c5a0000, + VFCMP_SOR_S = 0x0c5a8000, + VFCMP_CUNE_S = 0x0c5c0000, + VFCMP_SUNE_S = 0x0c5c8000, + VFCMP_CAF_D = 0x0c600000, + VFCMP_SAF_D = 0x0c608000, + VFCMP_CLT_D = 0x0c610000, + VFCMP_SLT_D = 0x0c618000, + VFCMP_CEQ_D = 0x0c620000, + VFCMP_SEQ_D = 0x0c628000, + VFCMP_CLE_D = 0x0c630000, + VFCMP_SLE_D = 0x0c638000, + VFCMP_CUN_D = 0x0c640000, + VFCMP_SUN_D = 0x0c648000, + VFCMP_CULT_D = 0x0c650000, + VFCMP_SULT_D = 0x0c658000, + VFCMP_CUEQ_D = 0x0c660000, + VFCMP_SUEQ_D = 0x0c668000, + VFCMP_CULE_D = 0x0c670000, + VFCMP_SULE_D = 0x0c678000, + VFCMP_CNE_D = 0x0c680000, + VFCMP_SNE_D = 0x0c688000, + VFCMP_COR_D = 0x0c6a0000, + VFCMP_SOR_D = 0x0c6a8000, + VFCMP_CUNE_D = 0x0c6c0000, + VFCMP_SUNE_D = 0x0c6c8000, + VBITSEL_V = 0x0d100000, + VSHUF_B = 0x0d500000, + VLD = 0x2c000000, + VST = 0x2c400000, + VLDREPL_D = 0x30100000, + VLDREPL_W = 0x30200000, + VLDREPL_H = 0x30400000, + VLDREPL_B = 0x30800000, + VSTELM_D = 0x31100000, + VSTELM_W = 0x31200000, + VSTELM_H = 0x31400000, + VSTELM_B = 0x31800000, + VLDX = 0x38400000, + VSTX = 0x38440000, + VSEQ_B = 0x70000000, + VSEQ_H = 0x70008000, + VSEQ_W = 0x70010000, + VSEQ_D = 0x70018000, + VSLE_B = 0x70020000, + VSLE_H = 0x70028000, + VSLE_W = 0x70030000, + VSLE_D = 0x70038000, + VSLE_BU = 0x70040000, + VSLE_HU = 0x70048000, + VSLE_WU = 0x70050000, + VSLE_DU = 0x70058000, + VSLT_B = 0x70060000, + VSLT_H = 0x70068000, + VSLT_W = 0x70070000, + VSLT_D = 0x70078000, + VSLT_BU = 0x70080000, + VSLT_HU = 0x70088000, + VSLT_WU = 0x70090000, + VSLT_DU = 0x70098000, + VADD_B = 0x700a0000, + VADD_H = 0x700a8000, + VADD_W = 0x700b0000, + VADD_D = 0x700b8000, + VSUB_B = 0x700c0000, + VSUB_H = 0x700c8000, + VSUB_W = 0x700d0000, + VSUB_D = 0x700d8000, + VADDWEV_H_B = 0x701e0000, + VADDWEV_W_H = 0x701e8000, + VADDWEV_D_W = 0x701f0000, + VADDWEV_Q_D = 0x701f8000, + VSUBWEV_H_B = 0x70200000, + VSUBWEV_W_H = 0x70208000, + VSUBWEV_D_W = 0x70210000, + VSUBWEV_Q_D = 0x70218000, + VADDWOD_H_B = 0x70220000, + VADDWOD_W_H = 0x70228000, + VADDWOD_D_W = 0x70230000, + VADDWOD_Q_D = 0x70238000, + VSUBWOD_H_B = 0x70240000, + VSUBWOD_W_H = 0x70248000, + VSUBWOD_D_W = 0x70250000, + VSUBWOD_Q_D = 0x70258000, + VADDWEV_H_BU = 0x702e0000, + VADDWEV_W_HU = 0x702e8000, + VADDWEV_D_WU = 0x702f0000, + VADDWEV_Q_DU = 0x702f8000, + VSUBWEV_H_BU = 0x70300000, + VSUBWEV_W_HU = 0x70308000, + VSUBWEV_D_WU = 0x70310000, + VSUBWEV_Q_DU = 0x70318000, + VADDWOD_H_BU = 0x70320000, + VADDWOD_W_HU = 0x70328000, + VADDWOD_D_WU = 0x70330000, + VADDWOD_Q_DU = 0x70338000, + VSUBWOD_H_BU = 0x70340000, + VSUBWOD_W_HU = 0x70348000, + VSUBWOD_D_WU = 0x70350000, + VSUBWOD_Q_DU = 0x70358000, + VADDWEV_H_BU_B = 0x703e0000, + VADDWEV_W_HU_H = 0x703e8000, + VADDWEV_D_WU_W = 0x703f0000, + VADDWEV_Q_DU_D = 0x703f8000, + VADDWOD_H_BU_B = 0x70400000, + VADDWOD_W_HU_H = 0x70408000, + VADDWOD_D_WU_W = 0x70410000, + VADDWOD_Q_DU_D = 0x70418000, + VSADD_B = 0x70460000, + VSADD_H = 0x70468000, + VSADD_W = 0x70470000, + VSADD_D = 0x70478000, + VSSUB_B = 0x70480000, + VSSUB_H = 0x70488000, + VSSUB_W = 0x70490000, + VSSUB_D = 0x70498000, + VSADD_BU = 0x704a0000, + VSADD_HU = 0x704a8000, + VSADD_WU = 0x704b0000, + VSADD_DU = 0x704b8000, + VSSUB_BU = 0x704c0000, + VSSUB_HU = 0x704c8000, + VSSUB_WU = 0x704d0000, + VSSUB_DU = 0x704d8000, + VHADDW_H_B = 0x70540000, + VHADDW_W_H = 0x70548000, + VHADDW_D_W = 0x70550000, + VHADDW_Q_D = 0x70558000, + VHSUBW_H_B = 0x70560000, + VHSUBW_W_H = 0x70568000, + VHSUBW_D_W = 0x70570000, + VHSUBW_Q_D = 0x70578000, + VHADDW_HU_BU = 0x70580000, + VHADDW_WU_HU = 0x70588000, + VHADDW_DU_WU = 0x70590000, + VHADDW_QU_DU = 0x70598000, + VHSUBW_HU_BU = 0x705a0000, + VHSUBW_WU_HU = 0x705a8000, + VHSUBW_DU_WU = 0x705b0000, + VHSUBW_QU_DU = 0x705b8000, + VADDA_B = 0x705c0000, + VADDA_H = 0x705c8000, + VADDA_W = 0x705d0000, + VADDA_D = 0x705d8000, + VABSD_B = 0x70600000, + VABSD_H = 0x70608000, + VABSD_W = 0x70610000, + VABSD_D = 0x70618000, + VABSD_BU = 0x70620000, + VABSD_HU = 0x70628000, + VABSD_WU = 0x70630000, + VABSD_DU = 0x70638000, + VAVG_B = 0x70640000, + VAVG_H = 0x70648000, + VAVG_W = 0x70650000, + VAVG_D = 0x70658000, + VAVG_BU = 0x70660000, + VAVG_HU = 0x70668000, + VAVG_WU = 0x70670000, + VAVG_DU = 0x70678000, + VAVGR_B = 0x70680000, + VAVGR_H = 0x70688000, + VAVGR_W = 0x70690000, + VAVGR_D = 0x70698000, + VAVGR_BU = 0x706a0000, + VAVGR_HU = 0x706a8000, + VAVGR_WU = 0x706b0000, + VAVGR_DU = 0x706b8000, + VMAX_B = 0x70700000, + VMAX_H = 0x70708000, + VMAX_W = 0x70710000, + VMAX_D = 0x70718000, + VMIN_B = 0x70720000, + VMIN_H = 0x70728000, + VMIN_W = 0x70730000, + VMIN_D = 0x70738000, + VMAX_BU = 0x70740000, + VMAX_HU = 0x70748000, + VMAX_WU = 0x70750000, + VMAX_DU = 0x70758000, + VMIN_BU = 0x70760000, + VMIN_HU = 0x70768000, + VMIN_WU = 0x70770000, + VMIN_DU = 0x70778000, + VMUL_B = 0x70840000, + VMUL_H = 0x70848000, + VMUL_W = 0x70850000, + VMUL_D = 0x70858000, + VMUH_B = 0x70860000, + VMUH_H = 0x70868000, + VMUH_W = 0x70870000, + VMUH_D = 0x70878000, + VMUH_BU = 0x70880000, + VMUH_HU = 0x70888000, + VMUH_WU = 0x70890000, + VMUH_DU = 0x70898000, + VMULWEV_H_B = 0x70900000, + VMULWEV_W_H = 0x70908000, + VMULWEV_D_W = 0x70910000, + VMULWEV_Q_D = 0x70918000, + VMULWOD_H_B = 0x70920000, + VMULWOD_W_H = 0x70928000, + VMULWOD_D_W = 0x70930000, + VMULWOD_Q_D = 0x70938000, + VMULWEV_H_BU = 0x70980000, + VMULWEV_W_HU = 0x70988000, + VMULWEV_D_WU = 0x70990000, + VMULWEV_Q_DU = 0x70998000, + VMULWOD_H_BU = 0x709a0000, + VMULWOD_W_HU = 0x709a8000, + VMULWOD_D_WU = 0x709b0000, + VMULWOD_Q_DU = 0x709b8000, + VMULWEV_H_BU_B = 0x70a00000, + VMULWEV_W_HU_H = 0x70a08000, + VMULWEV_D_WU_W = 0x70a10000, + VMULWEV_Q_DU_D = 0x70a18000, + VMULWOD_H_BU_B = 0x70a20000, + VMULWOD_W_HU_H = 0x70a28000, + VMULWOD_D_WU_W = 0x70a30000, + VMULWOD_Q_DU_D = 0x70a38000, + VMADD_B = 0x70a80000, + VMADD_H = 0x70a88000, + VMADD_W = 0x70a90000, + VMADD_D = 0x70a98000, + VMSUB_B = 0x70aa0000, + VMSUB_H = 0x70aa8000, + VMSUB_W = 0x70ab0000, + VMSUB_D = 0x70ab8000, + VMADDWEV_H_B = 0x70ac0000, + VMADDWEV_W_H = 0x70ac8000, + VMADDWEV_D_W = 0x70ad0000, + VMADDWEV_Q_D = 0x70ad8000, + VMADDWOD_H_B = 0x70ae0000, + VMADDWOD_W_H = 0x70ae8000, + VMADDWOD_D_W = 0x70af0000, + VMADDWOD_Q_D = 0x70af8000, + VMADDWEV_H_BU = 0x70b40000, + VMADDWEV_W_HU = 0x70b48000, + VMADDWEV_D_WU = 0x70b50000, + VMADDWEV_Q_DU = 0x70b58000, + VMADDWOD_H_BU = 0x70b60000, + VMADDWOD_W_HU = 0x70b68000, + VMADDWOD_D_WU = 0x70b70000, + VMADDWOD_Q_DU = 0x70b78000, + VMADDWEV_H_BU_B = 0x70bc0000, + VMADDWEV_W_HU_H = 0x70bc8000, + VMADDWEV_D_WU_W = 0x70bd0000, + VMADDWEV_Q_DU_D = 0x70bd8000, + VMADDWOD_H_BU_B = 0x70be0000, + VMADDWOD_W_HU_H = 0x70be8000, + VMADDWOD_D_WU_W = 0x70bf0000, + VMADDWOD_Q_DU_D = 0x70bf8000, + VDIV_B = 0x70e00000, + VDIV_H = 0x70e08000, + VDIV_W = 0x70e10000, + VDIV_D = 0x70e18000, + VMOD_B = 0x70e20000, + VMOD_H = 0x70e28000, + VMOD_W = 0x70e30000, + VMOD_D = 0x70e38000, + VDIV_BU = 0x70e40000, + VDIV_HU = 0x70e48000, + VDIV_WU = 0x70e50000, + VDIV_DU = 0x70e58000, + VMOD_BU = 0x70e60000, + VMOD_HU = 0x70e68000, + VMOD_WU = 0x70e70000, + VMOD_DU = 0x70e78000, + VSLL_B = 0x70e80000, + VSLL_H = 0x70e88000, + VSLL_W = 0x70e90000, + VSLL_D = 0x70e98000, + VSRL_B = 0x70ea0000, + VSRL_H = 0x70ea8000, + VSRL_W = 0x70eb0000, + VSRL_D = 0x70eb8000, + VSRA_B = 0x70ec0000, + VSRA_H = 0x70ec8000, + VSRA_W = 0x70ed0000, + VSRA_D = 0x70ed8000, + VROTR_B = 0x70ee0000, + VROTR_H = 0x70ee8000, + VROTR_W = 0x70ef0000, + VROTR_D = 0x70ef8000, + VSRLR_B = 0x70f00000, + VSRLR_H = 0x70f08000, + VSRLR_W = 0x70f10000, + VSRLR_D = 0x70f18000, + VSRAR_B = 0x70f20000, + VSRAR_H = 0x70f28000, + VSRAR_W = 0x70f30000, + VSRAR_D = 0x70f38000, + VSRLN_B_H = 0x70f48000, + VSRLN_H_W = 0x70f50000, + VSRLN_W_D = 0x70f58000, + VSRAN_B_H = 0x70f68000, + VSRAN_H_W = 0x70f70000, + VSRAN_W_D = 0x70f78000, + VSRLRN_B_H = 0x70f88000, + VSRLRN_H_W = 0x70f90000, + VSRLRN_W_D = 0x70f98000, + VSRARN_B_H = 0x70fa8000, + VSRARN_H_W = 0x70fb0000, + VSRARN_W_D = 0x70fb8000, + VSSRLN_B_H = 0x70fc8000, + VSSRLN_H_W = 0x70fd0000, + VSSRLN_W_D = 0x70fd8000, + VSSRAN_B_H = 0x70fe8000, + VSSRAN_H_W = 0x70ff0000, + VSSRAN_W_D = 0x70ff8000, + VSSRLRN_B_H = 0x71008000, + VSSRLRN_H_W = 0x71010000, + VSSRLRN_W_D = 0x71018000, + VSSRARN_B_H = 0x71028000, + VSSRARN_H_W = 0x71030000, + VSSRARN_W_D = 0x71038000, + VSSRLN_BU_H = 0x71048000, + VSSRLN_HU_W = 0x71050000, + VSSRLN_WU_D = 0x71058000, + VSSRAN_BU_H = 0x71068000, + VSSRAN_HU_W = 0x71070000, + VSSRAN_WU_D = 0x71078000, + VSSRLRN_BU_H = 0x71088000, + VSSRLRN_HU_W = 0x71090000, + VSSRLRN_WU_D = 0x71098000, + VSSRARN_BU_H = 0x710a8000, + VSSRARN_HU_W = 0x710b0000, + VSSRARN_WU_D = 0x710b8000, + VBITCLR_B = 0x710c0000, + VBITCLR_H = 0x710c8000, + VBITCLR_W = 0x710d0000, + VBITCLR_D = 0x710d8000, + VBITSET_B = 0x710e0000, + VBITSET_H = 0x710e8000, + VBITSET_W = 0x710f0000, + VBITSET_D = 0x710f8000, + VBITREV_B = 0x71100000, + VBITREV_H = 0x71108000, + VBITREV_W = 0x71110000, + VBITREV_D = 0x71118000, + VPACKEV_B = 0x71160000, + VPACKEV_H = 0x71168000, + VPACKEV_W = 0x71170000, + VPACKEV_D = 0x71178000, + VPACKOD_B = 0x71180000, + VPACKOD_H = 0x71188000, + VPACKOD_W = 0x71190000, + VPACKOD_D = 0x71198000, + VILVL_B = 0x711a0000, + VILVL_H = 0x711a8000, + VILVL_W = 0x711b0000, + VILVL_D = 0x711b8000, + VILVH_B = 0x711c0000, + VILVH_H = 0x711c8000, + VILVH_W = 0x711d0000, + VILVH_D = 0x711d8000, + VPICKEV_B = 0x711e0000, + VPICKEV_H = 0x711e8000, + VPICKEV_W = 0x711f0000, + VPICKEV_D = 0x711f8000, + VPICKOD_B = 0x71200000, + VPICKOD_H = 0x71208000, + VPICKOD_W = 0x71210000, + VPICKOD_D = 0x71218000, + VREPLVE_B = 0x71220000, + VREPLVE_H = 0x71228000, + VREPLVE_W = 0x71230000, + VREPLVE_D = 0x71238000, + VAND_V = 0x71260000, + VOR_V = 0x71268000, + VXOR_V = 0x71270000, + VNOR_V = 0x71278000, + VANDN_V = 0x71280000, + VORN_V = 0x71288000, + VFRSTP_B = 0x712b0000, + VFRSTP_H = 0x712b8000, + VADD_Q = 0x712d0000, + VSUB_Q = 0x712d8000, + VSIGNCOV_B = 0x712e0000, + VSIGNCOV_H = 0x712e8000, + VSIGNCOV_W = 0x712f0000, + VSIGNCOV_D = 0x712f8000, + VFADD_S = 0x71308000, + VFADD_D = 0x71310000, + VFSUB_S = 0x71328000, + VFSUB_D = 0x71330000, + VFMUL_S = 0x71388000, + VFMUL_D = 0x71390000, + VFDIV_S = 0x713a8000, + VFDIV_D = 0x713b0000, + VFMAX_S = 0x713c8000, + VFMAX_D = 0x713d0000, + VFMIN_S = 0x713e8000, + VFMIN_D = 0x713f0000, + VFMAXA_S = 0x71408000, + VFMAXA_D = 0x71410000, + VFMINA_S = 0x71428000, + VFMINA_D = 0x71430000, + VFCVT_H_S = 0x71460000, + VFCVT_S_D = 0x71468000, + VFFINT_S_L = 0x71480000, + VFTINT_W_D = 0x71498000, + VFTINTRM_W_D = 0x714a0000, + VFTINTRP_W_D = 0x714a8000, + VFTINTRZ_W_D = 0x714b0000, + VFTINTRNE_W_D = 0x714b8000, + VSHUF_H = 0x717a8000, + VSHUF_W = 0x717b0000, + VSHUF_D = 0x717b8000, + VSEQI_B = 0x72800000, + VSEQI_H = 0x72808000, + VSEQI_W = 0x72810000, + VSEQI_D = 0x72818000, + VSLEI_B = 0x72820000, + VSLEI_H = 0x72828000, + VSLEI_W = 0x72830000, + VSLEI_D = 0x72838000, + VSLEI_BU = 0x72840000, + VSLEI_HU = 0x72848000, + VSLEI_WU = 0x72850000, + VSLEI_DU = 0x72858000, + VSLTI_B = 0x72860000, + VSLTI_H = 0x72868000, + VSLTI_W = 0x72870000, + VSLTI_D = 0x72878000, + VSLTI_BU = 0x72880000, + VSLTI_HU = 0x72888000, + VSLTI_WU = 0x72890000, + VSLTI_DU = 0x72898000, + VADDI_BU = 0x728a0000, + VADDI_HU = 0x728a8000, + VADDI_WU = 0x728b0000, + VADDI_DU = 0x728b8000, + VSUBI_BU = 0x728c0000, + VSUBI_HU = 0x728c8000, + VSUBI_WU = 0x728d0000, + VSUBI_DU = 0x728d8000, + VBSLL_V = 0x728e0000, + VBSRL_V = 0x728e8000, + VMAXI_B = 0x72900000, + VMAXI_H = 0x72908000, + VMAXI_W = 0x72910000, + VMAXI_D = 0x72918000, + VMINI_B = 0x72920000, + VMINI_H = 0x72928000, + VMINI_W = 0x72930000, + VMINI_D = 0x72938000, + VMAXI_BU = 0x72940000, + VMAXI_HU = 0x72948000, + VMAXI_WU = 0x72950000, + VMAXI_DU = 0x72958000, + VMINI_BU = 0x72960000, + VMINI_HU = 0x72968000, + VMINI_WU = 0x72970000, + VMINI_DU = 0x72978000, + VFRSTPI_B = 0x729a0000, + VFRSTPI_H = 0x729a8000, + VCLO_B = 0x729c0000, + VCLO_H = 0x729c0400, + VCLO_W = 0x729c0800, + VCLO_D = 0x729c0c00, + VCLZ_B = 0x729c1000, + VCLZ_H = 0x729c1400, + VCLZ_W = 0x729c1800, + VCLZ_D = 0x729c1c00, + VPCNT_B = 0x729c2000, + VPCNT_H = 0x729c2400, + VPCNT_W = 0x729c2800, + VPCNT_D = 0x729c2c00, + VNEG_B = 0x729c3000, + VNEG_H = 0x729c3400, + VNEG_W = 0x729c3800, + VNEG_D = 0x729c3c00, + VMSKLTZ_B = 0x729c4000, + VMSKLTZ_H = 0x729c4400, + VMSKLTZ_W = 0x729c4800, + VMSKLTZ_D = 0x729c4c00, + VMSKGEZ_B = 0x729c5000, + VMSKNZ_B = 0x729c6000, + VSETEQZ_V = 0x729c9800, + VSETNEZ_V = 0x729c9c00, + VSETANYEQZ_B = 0x729ca000, + VSETANYEQZ_H = 0x729ca400, + VSETANYEQZ_W = 0x729ca800, + VSETANYEQZ_D = 0x729cac00, + VSETALLNEZ_B = 0x729cb000, + VSETALLNEZ_H = 0x729cb400, + VSETALLNEZ_W = 0x729cb800, + VSETALLNEZ_D = 0x729cbc00, + VFLOGB_S = 0x729cc400, + VFLOGB_D = 0x729cc800, + VFCLASS_S = 0x729cd400, + VFCLASS_D = 0x729cd800, + VFSQRT_S = 0x729ce400, + VFSQRT_D = 0x729ce800, + VFRECIP_S = 0x729cf400, + VFRECIP_D = 0x729cf800, + VFRSQRT_S = 0x729d0400, + VFRSQRT_D = 0x729d0800, + VFRECIPE_S = 0x729d1400, + VFRECIPE_D = 0x729d1800, + VFRSQRTE_S = 0x729d2400, + VFRSQRTE_D = 0x729d2800, + VFRINT_S = 0x729d3400, + VFRINT_D = 0x729d3800, + VFRINTRM_S = 0x729d4400, + VFRINTRM_D = 0x729d4800, + VFRINTRP_S = 0x729d5400, + VFRINTRP_D = 0x729d5800, + VFRINTRZ_S = 0x729d6400, + VFRINTRZ_D = 0x729d6800, + VFRINTRNE_S = 0x729d7400, + VFRINTRNE_D = 0x729d7800, + VFCVTL_S_H = 0x729de800, + VFCVTH_S_H = 0x729dec00, + VFCVTL_D_S = 0x729df000, + VFCVTH_D_S = 0x729df400, + VFFINT_S_W = 0x729e0000, + VFFINT_S_WU = 0x729e0400, + VFFINT_D_L = 0x729e0800, + VFFINT_D_LU = 0x729e0c00, + VFFINTL_D_W = 0x729e1000, + VFFINTH_D_W = 0x729e1400, + VFTINT_W_S = 0x729e3000, + VFTINT_L_D = 0x729e3400, + VFTINTRM_W_S = 0x729e3800, + VFTINTRM_L_D = 0x729e3c00, + VFTINTRP_W_S = 0x729e4000, + VFTINTRP_L_D = 0x729e4400, + VFTINTRZ_W_S = 0x729e4800, + VFTINTRZ_L_D = 0x729e4c00, + VFTINTRNE_W_S = 0x729e5000, + VFTINTRNE_L_D = 0x729e5400, + VFTINT_WU_S = 0x729e5800, + VFTINT_LU_D = 0x729e5c00, + VFTINTRZ_WU_S = 0x729e7000, + VFTINTRZ_LU_D = 0x729e7400, + VFTINTL_L_S = 0x729e8000, + VFTINTH_L_S = 0x729e8400, + VFTINTRML_L_S = 0x729e8800, + VFTINTRMH_L_S = 0x729e8c00, + VFTINTRPL_L_S = 0x729e9000, + VFTINTRPH_L_S = 0x729e9400, + VFTINTRZL_L_S = 0x729e9800, + VFTINTRZH_L_S = 0x729e9c00, + VFTINTRNEL_L_S = 0x729ea000, + VFTINTRNEH_L_S = 0x729ea400, + VEXTH_H_B = 0x729ee000, + VEXTH_W_H = 0x729ee400, + VEXTH_D_W = 0x729ee800, + VEXTH_Q_D = 0x729eec00, + VEXTH_HU_BU = 0x729ef000, + VEXTH_WU_HU = 0x729ef400, + VEXTH_DU_WU = 0x729ef800, + VEXTH_QU_DU = 0x729efc00, + VREPLGR2VR_B = 0x729f0000, + VREPLGR2VR_H = 0x729f0400, + VREPLGR2VR_W = 0x729f0800, + VREPLGR2VR_D = 0x729f0c00, + VROTRI_B = 0x72a02000, + VROTRI_H = 0x72a04000, + VROTRI_W = 0x72a08000, + VROTRI_D = 0x72a10000, + VSRLRI_B = 0x72a42000, + VSRLRI_H = 0x72a44000, + VSRLRI_W = 0x72a48000, + VSRLRI_D = 0x72a50000, + VSRARI_B = 0x72a82000, + VSRARI_H = 0x72a84000, + VSRARI_W = 0x72a88000, + VSRARI_D = 0x72a90000, + VINSGR2VR_B = 0x72eb8000, + VINSGR2VR_H = 0x72ebc000, + VINSGR2VR_W = 0x72ebe000, + VINSGR2VR_D = 0x72ebf000, + VPICKVE2GR_B = 0x72ef8000, + VPICKVE2GR_H = 0x72efc000, + VPICKVE2GR_W = 0x72efe000, + VPICKVE2GR_D = 0x72eff000, + VPICKVE2GR_BU = 0x72f38000, + VPICKVE2GR_HU = 0x72f3c000, + VPICKVE2GR_WU = 0x72f3e000, + VPICKVE2GR_DU = 0x72f3f000, + VREPLVEI_B = 0x72f78000, + VREPLVEI_H = 0x72f7c000, + VREPLVEI_W = 0x72f7e000, + VREPLVEI_D = 0x72f7f000, + VSLLWIL_H_B = 0x73082000, + VSLLWIL_W_H = 0x73084000, + VSLLWIL_D_W = 0x73088000, + VEXTL_Q_D = 0x73090000, + VSLLWIL_HU_BU = 0x730c2000, + VSLLWIL_WU_HU = 0x730c4000, + VSLLWIL_DU_WU = 0x730c8000, + VEXTL_QU_DU = 0x730d0000, + VBITCLRI_B = 0x73102000, + VBITCLRI_H = 0x73104000, + VBITCLRI_W = 0x73108000, + VBITCLRI_D = 0x73110000, + VBITSETI_B = 0x73142000, + VBITSETI_H = 0x73144000, + VBITSETI_W = 0x73148000, + VBITSETI_D = 0x73150000, + VBITREVI_B = 0x73182000, + VBITREVI_H = 0x73184000, + VBITREVI_W = 0x73188000, + VBITREVI_D = 0x73190000, + VSAT_B = 0x73242000, + VSAT_H = 0x73244000, + VSAT_W = 0x73248000, + VSAT_D = 0x73250000, + VSAT_BU = 0x73282000, + VSAT_HU = 0x73284000, + VSAT_WU = 0x73288000, + VSAT_DU = 0x73290000, + VSLLI_B = 0x732c2000, + VSLLI_H = 0x732c4000, + VSLLI_W = 0x732c8000, + VSLLI_D = 0x732d0000, + VSRLI_B = 0x73302000, + VSRLI_H = 0x73304000, + VSRLI_W = 0x73308000, + VSRLI_D = 0x73310000, + VSRAI_B = 0x73342000, + VSRAI_H = 0x73344000, + VSRAI_W = 0x73348000, + VSRAI_D = 0x73350000, + VSRLNI_B_H = 0x73404000, + VSRLNI_H_W = 0x73408000, + VSRLNI_W_D = 0x73410000, + VSRLNI_D_Q = 0x73420000, + VSRLRNI_B_H = 0x73444000, + VSRLRNI_H_W = 0x73448000, + VSRLRNI_W_D = 0x73450000, + VSRLRNI_D_Q = 0x73460000, + VSSRLNI_B_H = 0x73484000, + VSSRLNI_H_W = 0x73488000, + VSSRLNI_W_D = 0x73490000, + VSSRLNI_D_Q = 0x734a0000, + VSSRLNI_BU_H = 0x734c4000, + VSSRLNI_HU_W = 0x734c8000, + VSSRLNI_WU_D = 0x734d0000, + VSSRLNI_DU_Q = 0x734e0000, + VSSRLRNI_B_H = 0x73504000, + VSSRLRNI_H_W = 0x73508000, + VSSRLRNI_W_D = 0x73510000, + VSSRLRNI_D_Q = 0x73520000, + VSSRLRNI_BU_H = 0x73544000, + VSSRLRNI_HU_W = 0x73548000, + VSSRLRNI_WU_D = 0x73550000, + VSSRLRNI_DU_Q = 0x73560000, + VSRANI_B_H = 0x73584000, + VSRANI_H_W = 0x73588000, + VSRANI_W_D = 0x73590000, + VSRANI_D_Q = 0x735a0000, + VSRARNI_B_H = 0x735c4000, + VSRARNI_H_W = 0x735c8000, + VSRARNI_W_D = 0x735d0000, + VSRARNI_D_Q = 0x735e0000, + VSSRANI_B_H = 0x73604000, + VSSRANI_H_W = 0x73608000, + VSSRANI_W_D = 0x73610000, + VSSRANI_D_Q = 0x73620000, + VSSRANI_BU_H = 0x73644000, + VSSRANI_HU_W = 0x73648000, + VSSRANI_WU_D = 0x73650000, + VSSRANI_DU_Q = 0x73660000, + VSSRARNI_B_H = 0x73684000, + VSSRARNI_H_W = 0x73688000, + VSSRARNI_W_D = 0x73690000, + VSSRARNI_D_Q = 0x736a0000, + VSSRARNI_BU_H = 0x736c4000, + VSSRARNI_HU_W = 0x736c8000, + VSSRARNI_WU_D = 0x736d0000, + VSSRARNI_DU_Q = 0x736e0000, + VEXTRINS_D = 0x73800000, + VEXTRINS_W = 0x73840000, + VEXTRINS_H = 0x73880000, + VEXTRINS_B = 0x738c0000, + VSHUF4I_B = 0x73900000, + VSHUF4I_H = 0x73940000, + VSHUF4I_W = 0x73980000, + VSHUF4I_D = 0x739c0000, + VBITSELI_B = 0x73c40000, + VANDI_B = 0x73d00000, + VORI_B = 0x73d40000, + VXORI_B = 0x73d80000, + VNORI_B = 0x73dc0000, + VLDI = 0x73e00000, + VPERMI_W = 0x73e40000, +}; + +static inline s32 SignReduce32(s32 v, int width) { + int shift = 32 - width; + return (v << shift) >> shift; +} + +static inline s64 SignReduce64(s64 v, int width) { + int shift = 64 - width; + return (v << shift) >> shift; +} + +static inline bool SupportsCPUCFG() { + return cpu_info.LOONGARCH_CPUCFG; +} + +static inline bool SupportsLAM() { + return cpu_info.LOONGARCH_LAM; +} + +static inline bool SupportsUAL() { + return cpu_info.LOONGARCH_UAL; +} + +static inline bool SupportsFPU() { + return cpu_info.LOONGARCH_FPU; +} + +static inline bool SupportsLSX() { + return cpu_info.LOONGARCH_LSX; +} + +static inline bool SupportsLASX() { + return cpu_info.LOONGARCH_LASX; +} + +static inline bool SupportsCRC32() { + return cpu_info.LOONGARCH_CRC32; +} + +static inline bool SupportsComplex() { + return cpu_info.LOONGARCH_COMPLEX; +} + +static inline bool SupportsCrypto() { + return cpu_info.LOONGARCH_CRYPTO; +} + +static inline bool SupportsLVZ() { + return cpu_info.LOONGARCH_LVZ; +} + +static inline bool SupportsLBT_X86() { + return cpu_info.LOONGARCH_LBT_X86; +} + +static inline bool SupportsLBT_ARM() { + return cpu_info.LOONGARCH_LBT_ARM; +} + +static inline bool SupportsLBT_MIPS() { + return cpu_info.LOONGARCH_LBT_MIPS; +} + +static inline bool SupportsPTW() { + return cpu_info.LOONGARCH_PTW; +} + +LoongArch64Emitter::LoongArch64Emitter(const u8 *ptr, u8 *writePtr) { + SetCodePointer(ptr, writePtr); +} + +void LoongArch64Emitter::SetCodePointer(const u8 *ptr, u8 *writePtr) { + code_ = ptr; + writable_ = writePtr; + lastCacheFlushEnd_ = ptr; +} + +const u8 *LoongArch64Emitter::GetCodePointer() const { + return code_; +} + +u8 *LoongArch64Emitter::GetWritableCodePtr() { + return writable_; +} + +static inline u32 EncodeDJK(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(IsGPR(rd), "DJK instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJK instruction rj must be GPR"); + _assert_msg_(IsGPR(rk), "DJK instruction rk must be GPR"); + return (u32)opcode | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDJSk12(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(IsGPR(rd), "DJSk12 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJSk12 instruction rj must be GPR"); + return (u32)opcode | ((u32)(si12 & 0xFFF) << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDJUk12(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, u16 ui12) { + _assert_msg_(IsGPR(rd), "DJUk12 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJUk12 instruction rj must be GPR"); + return (u32)opcode | ((u32)(ui12 & 0xFFF) << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDJSk16(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, s16 si16) { + _assert_msg_(IsGPR(rd), "DJSk16 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJSk16 instruction rj must be GPR"); + return (u32)opcode | ((u32)si16 << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDJKUa2pp1(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) { + _assert_msg_(IsGPR(rd), "DJKUa2pp1 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJKUa2pp1 instruction rj must be GPR"); + _assert_msg_(IsGPR(rk), "DJKUa2pp1 instruction rk must be GPR"); + // cpu will perform as sa2 + 1 + return (u32)opcode | (u32)((sa2 - 1) & 0x3) << 15 | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDJKUa3pp1(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa3) { + _assert_msg_(IsGPR(rd), "DJKUa3pp1 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJKUa3pp1 instruction rj must be GPR"); + _assert_msg_(IsGPR(rk), "DJKUa3pp1 instruction rk must be GPR"); + // cpu will perform as sa3 + 1 + return (u32)opcode | (u32)((sa3 - 1) & 0x7) << 15 | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDSj20(Opcode32 opcode, LoongArch64Reg rd, s32 si20) { + _assert_msg_(IsGPR(rd), "DSj20 instruction rd must be GPR"); + return (u32)opcode | ((u32)(si20 & 0xFFFFF) << 5) | (u32)rd; +} + +static inline u32 EncodeDJUk5(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5) { + _assert_msg_(IsGPR(rd), "DJUk5 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJUk5 instruction rj must be GPR"); + return (u32)opcode | ((u32)(ui5 & 0x1F) << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDJUk6(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6) { + _assert_msg_(IsGPR(rd), "DJUk6 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJUk6 instruction rj must be GPR"); + return (u32)opcode | ((u32)(ui6 & 0x3F) << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDJ(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(IsGPR(rd), "DJ instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJ instruction rj must be GPR"); + return (u32)opcode | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeJK(Opcode32 opcode, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(IsGPR(rj), "JK instruction rj must be GPR"); + _assert_msg_(IsGPR(rk), "JK instruction rk must be GPR"); + return (u32)opcode | ((u32)rk << 5) | ((u32)rj << 5); +} + +static inline u32 EncodeDJKUa2(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) { + _assert_msg_(IsGPR(rd), "DJKUa2 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJKUa2 instruction rj must be GPR"); + _assert_msg_(IsGPR(rk), "DJKUa2 instruction rk must be GPR"); + return (u32)opcode | ((u32)(sa2 & 0x3) << 15) | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDJUk5Um5(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, u8 msbw, u8 lsbw) { + _assert_msg_(IsGPR(rd), "DJUk5Um5 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJUk5Um5 instruction rj must be GPR"); + return (u32)opcode | ((u32)(msbw & 0x1F) << 16) | ((u32)(lsbw & 0x1f) << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDJUk6Um6(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, u8 msbd, u8 lsbd) { + _assert_msg_(IsGPR(rd), "DJUk6Um6 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJUk6Um6 instruction rj must be GPR"); + return (u32)opcode | ((u32)(msbd & 0x3F) << 16) | ((u32)(lsbd & 0x3f) << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDJKUa3(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa3) { + _assert_msg_(IsGPR(rd), "DJKUa3 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJKUa3 instruction rj must be GPR"); + _assert_msg_(IsGPR(rk), "DJKUa3 instruction rk must be GPR"); + return (u32)opcode | (u32)(sa3 & 0x7) << 15 | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeJDSk16ps2(Opcode32 opcode, LoongArch64Reg rj, LoongArch64Reg rd, s32 offs16) { + _assert_msg_(IsGPR(rd), "JDSk16ps2 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "JDSk16ps2 instruction rj must be GPR"); + _assert_msg_((offs16 & 3) == 0, "offs16 immediate must be aligned to 4"); + u32 offs = (u32)(offs16 >> 2); + return (u32)opcode | ((offs & 0xFFFF) << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeDJSk16ps2(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, s32 offs16) { + _assert_msg_(IsGPR(rd), "DJSk16ps2 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJSk16ps2 instruction rj must be GPR"); + _assert_msg_((offs16 & 3) == 0, "offs16 immediate must be aligned to 4"); + u32 offs = (u32)(offs16 >> 2) & 0xFFFF; + return (u32)opcode | ((offs & 0xFFFF) << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeJSd5k16(Opcode32 opcode, LoongArch64Reg rj, s32 offs21) { + _assert_msg_(IsGPR(rj), "JSd5k16 instruction rj must be GPR"); + _assert_msg_((offs21 & 3) == 0, "offs21 immediate must be aligned to 4"); + u32 offs = (u32)(offs21 >> 2); + return (u32)opcode | ((offs & 0xFFFF) << 10) | ((u32)rj << 5) | ((offs >> 16) & 0x1F); +} + +static inline u32 EncodeSd10k16ps2(Opcode32 opcode, s32 offs26) { + _assert_msg_((offs26 & 3) == 0, "offs21 immediate must be aligned to 4"); + u32 offs = (u32)(offs26 >> 2); + return (u32)opcode | ((offs & 0xFFFF) << 10) | ((offs >> 16) & 0x3FF); +} + +static inline u32 EncodeDJSk14ps2(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rj, s16 si14) { + _assert_msg_(IsGPR(rd), "DJSk14ps2 instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DJSk14ps2 instruction rj must be GPR"); + _assert_msg_((si14 & 3) == 0, "offs21 immediate must be aligned to 4"); + u32 si = (u32)(si14 >> 2); + return (u32)opcode | (si & 0x3FFF) << 10 | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeUd5JSk12(Opcode32 opcode, u32 hint, LoongArch64Reg rj, s16 si12) { + _assert_msg_(IsGPR(rj), "Ud5JSk12 instruction rj must be GPR"); + _assert_msg_((si12 & 3) == 0, "offs21 immediate must be aligned to 4"); + return (u32)opcode | ((u32)(si12 & 0xFFF) << 10) | ((u32)rj << 5) | (u32)(hint & 0x1F); +} + +static inline u32 EncodeUd5JK(Opcode32 opcode, u32 hint, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(IsGPR(rj), "Ud5JK instruction rj must be GPR"); + _assert_msg_(IsGPR(rk), "Ud5JK instruction rk must be GPR"); + return (u32)opcode | ((u32)rk << 10) | ((u32)rj << 5) | (u32)(hint & 0x1F); +} + +static inline u32 EncodeDKJ(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(IsGPR(rd), "DKJ instruction rd must be GPR"); + _assert_msg_(IsGPR(rj), "DKJ instruction rj must be GPR"); + _assert_msg_(IsGPR(rk), "DKJ instruction rk must be GPR"); + return (u32)opcode | ((u32)rk << 10) | ((u32)rj << 5) | (u32)rd; +} + +static inline u32 EncodeUd15(Opcode32 opcode, u16 code) { + return (u32)opcode | (u32)(code & 0x7FFF); +} + +static inline u32 EncodeFdFjFk(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + _assert_msg_(IsFPR(fd), "FdFjFk instruction fd must be FPR"); + _assert_msg_(IsFPR(fj), "FdFjFk instruction fj must be FPR"); + _assert_msg_(IsFPR(fk), "FdFjFk instruction fk must be FPR"); + return (u32)opcode | ((u32)DecodeReg(fk) << 10) | ((u32)DecodeReg(fj) << 5) | (u32)DecodeReg(fd); +} + +static inline u32 EncodeFdFjFkFa(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) { + _assert_msg_(IsFPR(fd), "FdFjFkFa instruction fd must be FPR"); + _assert_msg_(IsFPR(fj), "FdFjFkFa instruction fj must be FPR"); + _assert_msg_(IsFPR(fk), "FdFjFkFa instruction fk must be FPR"); + _assert_msg_(IsFPR(fa), "FdFjFkFa instruction fk must be FPR"); + return (u32)opcode | ((u32)DecodeReg(fa) << 15) | ((u32)DecodeReg(fk) << 10) | ((u32)DecodeReg(fj) << 5) | (u32)DecodeReg(fd); +} + +static inline u32 EncodeFdFj(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg fj) { + _assert_msg_(IsFPR(fd), "FdFj instruction fd must be FPR"); + _assert_msg_(IsFPR(fj), "FdFj instruction fj must be FPR"); + return (u32)opcode | ((u32)DecodeReg(fj) << 5) | (u32)DecodeReg(fd); +} + +static inline u32 EncodeCdFjFkFcond(Opcode32 opcode, LoongArch64CFR cd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Fcond cond) { + _assert_msg_(IsCFR(cd), "CdFjFkFcond instruction cd must be CFR"); + _assert_msg_(IsFPR(fj), "CdFjFkFcond instruction fj must be FPR"); + _assert_msg_(IsFPR(fk), "CdFjFkFcond instruction fk must be FPR"); + return (u32)opcode | ((u32)cond << 15) | ((u32)DecodeReg(fk) << 10) | ((u32)DecodeReg(fj) << 5) | (u32)cd; +} + +static inline u32 EncodeFdFjFkCa(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64CFR ca) { + _assert_msg_(IsFPR(fd), "FdFjFkCa instruction fd must be FPR"); + _assert_msg_(IsFPR(fj), "FdFjFkCa instruction fj must be FPR"); + _assert_msg_(IsFPR(fk), "FdFjFkCa instruction fk must be FPR"); + _assert_msg_(IsCFR(ca), "FdFjFkCa instruction ca must be CFR"); + return (u32)opcode | ((u32)ca << 15) | ((u32)DecodeReg(fk) << 10) | ((u32)DecodeReg(fj) << 5) | (u32)DecodeReg(fd); +} + +static inline u32 EncodeFdJ(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg rj) { + _assert_msg_(IsFPR(fd), "FdJ instruction fd must be FPR"); + _assert_msg_(IsGPR(rj), "FdJ instruction rj must be GPR"); + return (u32)opcode | ((u32)rj << 5) | (u32)DecodeReg(fd); +} + +static inline u32 EncodeDFj(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg fj) { + _assert_msg_(IsGPR(rd), "DFj instruction rd must be GPR"); + _assert_msg_(IsFPR(fj), "DFj instruction fj must be FPR"); + return (u32)opcode | ((u32)fj << 5) | (u32)DecodeReg(rd); +} + +static inline u32 EncodeJUd5(Opcode32 opcode, LoongArch64FCSR fcsr, LoongArch64Reg rj) { + _assert_msg_(IsFCSR(fcsr), "JUd5 instruction fcsr must be FCSR"); + _assert_msg_(IsGPR(rj), "JUd5 instruction rj must be GPR"); + return (u32)opcode | ((u32)rj << 5) | (u32)fcsr; +} + +static inline u32 EncodeDUj5(Opcode32 opcode, LoongArch64Reg rd, LoongArch64FCSR fcsr) { + _assert_msg_(IsGPR(rd), "DUj5 instruction rd must be GPR"); + _assert_msg_(IsFCSR(fcsr), "DUj5 instruction fcsr must be FCSR"); + return (u32)opcode | ((u32)fcsr << 5) | (u32)rd; +} + +static inline u32 EncodeCdFj(Opcode32 opcode, LoongArch64CFR cd, LoongArch64Reg fj) { + _assert_msg_(IsCFR(cd), "CdFj instruction cd must be CFR"); + _assert_msg_(IsFPR(fj), "CdFj instruction fj must be FPR"); + return (u32)opcode | ((u32)DecodeReg(fj) << 5) | (u32)cd; +} + +static inline u32 EncodeFdCj(Opcode32 opcode, LoongArch64Reg fd, LoongArch64CFR cj) { + _assert_msg_(IsFPR(fd), "FdCj instruction fd must be FPR"); + _assert_msg_(IsCFR(cj), "FdCj instruction cj must be CFR"); + return (u32)opcode | ((u32)cj << 5) | (u32)DecodeReg(fd); +} + +static inline u32 EncodeCdJ(Opcode32 opcode, LoongArch64CFR cd, LoongArch64Reg rj) { + _assert_msg_(IsCFR(cd), "CdJ instruction cd must be CFR"); + _assert_msg_(IsGPR(rj), "CdJ instruction rj must be GPR"); + return (u32)opcode | ((u32)rj << 5) | (u32)cd; +} + +static inline u32 EncodeDCj(Opcode32 opcode, LoongArch64Reg rd, LoongArch64CFR cj) { + _assert_msg_(IsGPR(rd), "DCj instruction rd must be GPR"); + _assert_msg_(IsCFR(cj), "DCj instruction cj must be CFR"); + return (u32)opcode | ((u32)cj << 5) | (u32)rd; +} + +static inline u32 EncodeCjSd5k16ps2(Opcode32 opcode, LoongArch64CFR cj, s32 offs21) { + _assert_msg_(IsCFR(cj), "CjSd5k16ps2 instruction cj must be CFR"); + _assert_msg_((offs21 & 3) == 0, "offs21 immediate must be aligned to 4"); + u32 offs = (u32)(offs21 >> 2); + return (u32)opcode | ((offs & 0xFFFF) << 10) | ((u32)cj << 5) | ((offs >> 16) & 0x1F); +} + +static inline u32 EncodeFdJSk12(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(IsFPR(fd), "FdJSk12 instruction fd must be FPR"); + _assert_msg_(IsGPR(rj), "FdJSk12 instruction rj must be GPR"); + return (u32)opcode | ((u32)(si12 & 0xFFF) << 10) | ((u32)rj << 5) | (u32)DecodeReg(fd); +} + +static inline u32 EncodeFdJK(Opcode32 opcode, LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(IsFPR(fd), "FdJK instruction fd must be FPR"); + _assert_msg_(IsGPR(rj), "FdJK instruction rj must be GPR"); + _assert_msg_(IsGPR(rk), "FdJK instruction rk must be GPR"); + return (u32)opcode | ((u32)rk << 10) | ((u32)rj << 5) | (u32)DecodeReg(fd); +} + +static inline u32 EncodeVdVjVkVa(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) { + _assert_msg_(IsVPR(vd), "VdVjVkVa instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjVkVa instruction vj must be VPR"); + _assert_msg_(IsVPR(vk), "VdVjVkVa instruction vk must be VPR"); + _assert_msg_(IsVPR(va), "VdVjVkVa instruction vk must be VPR"); + return (u32)opcode | ((u32)DecodeReg(va) << 15) | ((u32)DecodeReg(vk) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVjVk(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + _assert_msg_(IsVPR(vd), "VdVjVk instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjVk instruction vj must be VPR"); + _assert_msg_(IsVPR(vk), "VdVjVk instruction vk must be VPR"); + return (u32)opcode | ((u32)DecodeReg(vk) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJSk12(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(IsVPR(vd), "VdJSk12 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJSk12 instruction rj must be GPR"); + return (u32)opcode | ((u32)(si12 & 0xFFF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJSk11(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si11) { + _assert_msg_(IsVPR(vd), "VdJSk11 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJSk11 instruction rj must be GPR"); + return (u32)opcode | ((u32)((si11 >> 1) & 0x7FF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJSk10(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si10) { + _assert_msg_(IsVPR(vd), "VdJSk10 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJSk10 instruction rj must be GPR"); + return (u32)opcode | ((u32)((si10 >> 2) & 0x3FF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJSk9(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si9) { + _assert_msg_(IsVPR(vd), "VdJSk9 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJSk9 instruction rj must be GPR"); + return (u32)opcode | ((u32)((si9 >> 3) & 0x1FF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJSk8Un1(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx1) { + _assert_msg_(IsVPR(vd), "VdJSk8Un1 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJSk8Un1 instruction rj must be GPR"); + return (u32)opcode | (u32)((idx1 & 0x1) << 18) | ((u32)((si8 >> 3) & 0xFF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJSk8Un2(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx2) { + _assert_msg_(IsVPR(vd), "VdJSk8Un2 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJSk8Un2 instruction rj must be GPR"); + return (u32)opcode | (u32)((idx2 & 0x3) << 18) | ((u32)((si8 >> 2) & 0xFF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJSk8Un3(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx3) { + _assert_msg_(IsVPR(vd), "VdJSk8Un3 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJSk8Un3 instruction rj must be GPR"); + return (u32)opcode | (u32)((idx3 & 0x7) << 18) | ((u32)((si8 >> 1) & 0xFF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJSk8Un4(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx4) { + _assert_msg_(IsVPR(vd), "VdJSk8Un4 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJSk8Un4 instruction rj must be GPR"); + return (u32)opcode | (u32)((idx4 & 0xF) << 18) | ((u32)(si8 & 0xFF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJK(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(IsVPR(vd), "VdJK instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJK instruction rj must be GPR"); + _assert_msg_(IsGPR(rk), "VdJK instruction rk must be GPR"); + return (u32)opcode | ((u32)DecodeReg(rk) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVjSk5(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + _assert_msg_(IsVPR(vd), "VdVjSk5 instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjSk5 instruction vj must be VPR"); + return (u32)opcode | ((u32)(si5 & 0x1F) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVjUk1(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui1) { + _assert_msg_(IsVPR(vd), "VdVjUk1 instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjUk1 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui1 & 0x1) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVjUk2(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui2) { + _assert_msg_(IsVPR(vd), "VdVjUk2 instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjUk2 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui2 & 0x3) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVjUk3(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + _assert_msg_(IsVPR(vd), "VdVjUk3 instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjUk3 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui3 & 0x7) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVjUk4(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + _assert_msg_(IsVPR(vd), "VdVjUk4 instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjUk4 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui4 & 0xF) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVjUk5(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + _assert_msg_(IsVPR(vd), "VdVjUk5 instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjUk5 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui5 & 0x1F) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVjUk6(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + _assert_msg_(IsVPR(vd), "VdVjUk6 instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjUk6 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui6 & 0x3F) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVjUk7(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + _assert_msg_(IsVPR(vd), "VdVjUk7 instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjUk7 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui7 & 0x7F) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVjUk8(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + _assert_msg_(IsVPR(vd), "VdVjUk8 instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjUk8 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui8 & 0xFF) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVj(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj) { + _assert_msg_(IsVPR(vd), "VdVj instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVj instruction vj must be VPR"); + return (u32)opcode | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdVjK(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk) { + _assert_msg_(IsVPR(vd), "VdVjK instruction vd must be VPR"); + _assert_msg_(IsVPR(vj), "VdVjK instruction vj must be VPR"); + _assert_msg_(IsGPR(rk), "VdVjK instruction rk must be GPR"); + return (u32)opcode | ((u32)DecodeReg(rk) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeCdVj(Opcode32 opcode, LoongArch64CFR cd, LoongArch64Reg vj) { + _assert_msg_(IsCFR(cd), "CdVj instruction cd must be CFR"); + _assert_msg_(IsVPR(vj), "CdVj instruction vj must be VPR"); + return (u32)opcode | ((u32)DecodeReg(vj) << 5) | (u32)(cd & 0x7); +} + +static inline u32 EncodeVdJ(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj) { + _assert_msg_(IsVPR(vd), "VdJ instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJ instruction rj must be GPR"); + return (u32)opcode | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJUk1(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, u8 ui1) { + _assert_msg_(IsVPR(vd), "VdJUk1 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJUk1 instruction rj must be GPR"); + return (u32)opcode | ((u32)(ui1 & 0x1) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJUk2(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, u8 ui2) { + _assert_msg_(IsVPR(vd), "VdJUk2 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJUk2 instruction rj must be GPR"); + return (u32)opcode | ((u32)(ui2 & 0x3) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJUk3(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, u8 ui3) { + _assert_msg_(IsVPR(vd), "VdJUk3 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJUk3 instruction rj must be GPR"); + return (u32)opcode | ((u32)(ui3 & 0x7) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeVdJUk4(Opcode32 opcode, LoongArch64Reg vd, LoongArch64Reg rj, u8 ui4) { + _assert_msg_(IsVPR(vd), "VdJUk4 instruction vd must be VPR"); + _assert_msg_(IsGPR(rj), "VdJUk4 instruction rj must be GPR"); + return (u32)opcode | ((u32)(ui4 & 0xF) << 10) | ((u32)DecodeReg(rj) << 5) | (u32)DecodeReg(vd); +} + +static inline u32 EncodeDVjUk1(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg vj, u8 ui1) { + _assert_msg_(IsGPR(rd), "DVjUk1 instruction rd must be GPR"); + _assert_msg_(IsVPR(vj), "DVjUk1 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui1 & 0x1) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(rd); +} + +static inline u32 EncodeDVjUk2(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg vj, u8 ui2) { + _assert_msg_(IsGPR(rd), "DVjUk2 instruction rd must be GPR"); + _assert_msg_(IsVPR(vj), "DVjUk2 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui2 & 0x3) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(rd); +} + +static inline u32 EncodeDVjUk3(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg vj, u8 ui3) { + _assert_msg_(IsGPR(rd), "DVjUk3 instruction rd must be GPR"); + _assert_msg_(IsVPR(vj), "DVjUk3 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui3 & 0x7) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(rd); +} + +static inline u32 EncodeDVjUk4(Opcode32 opcode, LoongArch64Reg rd, LoongArch64Reg vj, u8 ui4) { + _assert_msg_(IsGPR(rd), "DVjUk4 instruction rd must be GPR"); + _assert_msg_(IsVPR(vj), "DVjUk4 instruction vj must be VPR"); + return (u32)opcode | ((u32)(ui4 & 0xF) << 10) | ((u32)DecodeReg(vj) << 5) | (u32)DecodeReg(rd); +} + +static inline u32 EncodeVdSj13(Opcode32 opcode, LoongArch64Reg vd, s16 i13) { + _assert_msg_(IsVPR(vd), "VdJUk4 instruction vd must be VPR"); + return (u32)opcode | ((u32)(i13 & 0x1FFF) << 5) | (u32)DecodeReg(vd); +} + +void LoongArch64Emitter::ReserveCodeSpace(u32 bytes) +{ + for (u32 i = 0; i < bytes / 4; i++) + BREAK(0); +} + +const u8 *LoongArch64Emitter::AlignCode16() { + int c = int((u64)code_ & 15); + if (c) + ReserveCodeSpace(16 - c); + return code_; +} + +const u8 *LoongArch64Emitter::AlignCodePage() { + int page_size = GetMemoryProtectPageSize(); + int c = int((intptr_t)code_ & ((intptr_t)page_size - 1)); + if (c) + ReserveCodeSpace(page_size - c); + return code_; +} + +void LoongArch64Emitter::FlushIcache() { + FlushIcacheSection(lastCacheFlushEnd_, code_); + lastCacheFlushEnd_ = code_; +} + +void LoongArch64Emitter::FlushIcacheSection(const u8 *start, const u8 *end) { +#if PPSSPP_ARCH(LOONGARCH64) + __builtin___clear_cache((char *)start, (char *)end); +#endif +} + +FixupBranch::FixupBranch(FixupBranch &&other) { + ptr = other.ptr; + type = other.type; + other.ptr = nullptr; +} + +FixupBranch::~FixupBranch() { + _assert_msg_(ptr == nullptr, "FixupBranch never set (left infinite loop)"); +} + +FixupBranch &FixupBranch::operator =(FixupBranch &&other) { + ptr = other.ptr; + type = other.type; + other.ptr = nullptr; + return *this; +} + +void LoongArch64Emitter::SetJumpTarget(FixupBranch &branch) { + SetJumpTarget(branch, code_); +} + +void LoongArch64Emitter::SetJumpTarget(FixupBranch &branch, const void *dst) { + _assert_msg_(branch.ptr != nullptr, "Invalid FixupBranch (SetJumpTarget twice?)"); + + const intptr_t srcp = (intptr_t)branch.ptr; + const intptr_t dstp = (intptr_t)dst; + const ptrdiff_t writable_delta = writable_ - code_; + u32 *writableSrc = (u32 *)(branch.ptr + writable_delta); + + u32 fixup; + + _assert_msg_((dstp & 3) == 0, "Destination should be aligned (no compressed)"); + + ptrdiff_t distance = dstp - srcp; + _assert_msg_((distance & 3) == 0, "Distance should be aligned (no compressed)"); + + switch (branch.type) { + case FixupBranchType::B: + _assert_msg_(BranchInRange(branch.ptr, dst), "B destination is too far away (%p -> %p)", branch.ptr, dst); + memcpy(&fixup, writableSrc, sizeof(u32)); + fixup = (fixup & 0xFC0003FF) | EncodeJDSk16ps2(Opcode32::ZERO, R_ZERO, R_ZERO, (s32)distance); + memcpy(writableSrc, &fixup, sizeof(u32)); + break; + + case FixupBranchType::J: + _assert_msg_(JumpInRange(branch.ptr, dst), "J destination is too far away (%p -> %p)", branch.ptr, dst); + memcpy(&fixup, writableSrc, sizeof(u32)); + fixup = (fixup & 0xFC000000) | EncodeSd10k16ps2(Opcode32::ZERO, (s32)distance); + memcpy(writableSrc, &fixup, sizeof(u32)); + break; + + case FixupBranchType::BZ: + _assert_msg_(BranchInRange(branch.ptr, dst), "B destination is too far away (%p -> %p)", branch.ptr, dst); + memcpy(&fixup, writableSrc, sizeof(u32)); + fixup = (fixup & 0xFC0003E0) | EncodeJSd5k16(Opcode32::ZERO, R_ZERO, (s32)distance); + memcpy(writableSrc, &fixup, sizeof(u32)); + break; + } + + branch.ptr = nullptr; +} + +bool LoongArch64Emitter::BranchInRange(const void *func) const { + return BranchInRange(code_, func); +} + +bool LoongArch64Emitter::BranchZeroInRange(const void *func) const { + return BranchZeroInRange(code_, func); +} + +bool LoongArch64Emitter::JumpInRange(const void *func) const { + return JumpInRange(code_, func); +} + +static inline bool BJInRange(const void *src, const void *dst, int bits) { + ptrdiff_t distance = (intptr_t)dst - (intptr_t)src; + // Get rid of bits and sign extend to validate range. + s32 encodable = SignReduce32((s32)distance, bits); + return distance == encodable; +} + +bool LoongArch64Emitter::BranchInRange(const void *src, const void *dst) const { + return BJInRange(src, dst, 18); +} + +bool LoongArch64Emitter::BranchZeroInRange(const void *src, const void *dst) const { + return BJInRange(src, dst, 23); +} + +bool LoongArch64Emitter::JumpInRange(const void *src, const void *dst) const { + return BJInRange(src, dst, 28); +} + +void LoongArch64Emitter::QuickJump(LoongArch64Reg scratchreg, LoongArch64Reg rd, const u8 *dst) { + if (!JumpInRange(GetCodePointer(), dst)) { + int32_t lower = (int32_t)SignReduce64((int64_t)dst, 18); + static_assert(sizeof(intptr_t) <= sizeof(int64_t)); + LI(scratchreg, dst - lower); + JIRL(rd, scratchreg, lower); + } else if (rd != R_ZERO) { + BL(dst); + } else { + B(dst); + } +} + +void LoongArch64Emitter::SetRegToImmediate(LoongArch64Reg rd, uint64_t value) { + int64_t svalue = (int64_t)value; + _assert_msg_(IsGPR(rd), "SetRegToImmediate only supports GPRs"); + + if (SignReduce64(svalue, 12) == svalue) { + // Nice and simple, small immediate fits in a single ADDI against zero. + ADDI_D(rd, R_ZERO, (s32)svalue); + return; + } + + if (svalue <= 0x7fffffffl && svalue >= -0x80000000l) { + // Use lu12i.w/ori to load 32-bits immediate. + LU12I_W(rd, (s32)((svalue & 0xffffffff) >> 12)); + ORI(rd, rd, (s16)(svalue & 0xFFF)); + return; + } else if (svalue <= 0x7ffffffffffffl && svalue >= -0x8000000000000l) { + // Use lu12i.w/ori/lu32i.d to load 52-bits immediate. + LU12I_W(rd, (s32)((svalue & 0xffffffff) >> 12)); + ORI(rd, rd, (s16)(svalue & 0xFFF)); + LU32I_D(rd, (s32)((svalue >> 32) & 0xfffff)); + return; + } + // Use lu12i.w/ori/lu32i.d/lu52i.d to load 64-bits immediate. + LU12I_W(rd, (s32)((svalue & 0xffffffff) >> 12)); + ORI(rd, rd, (s16)(svalue & 0xFFF)); + LU32I_D(rd, (s32)((svalue >> 32) & 0xfffff)); + return LU52I_D(rd, rd, (s16)(svalue >> 52)); +} + +void LoongArch64Emitter::ADD_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::ADD_W, rd, rj, rk)); +} + +void LoongArch64Emitter::ADD_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::ADD_D, rd, rj, rk)); +} + +void LoongArch64Emitter::SUB_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::SUB_W, rd, rj, rk)); +} + +void LoongArch64Emitter::SUB_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::SUB_D, rd, rj, rk)); +} + +void LoongArch64Emitter::ADDI_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO || (rj == R0 && si12 == 0), "%s write to zero is a HINT", __func__); // work as NOP + Write32(EncodeDJSk12(Opcode32::ADDI_W, rd, rj, si12)); +} + +void LoongArch64Emitter::ADDI_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO || (rj == R0 && si12 == 0), "%s write to zero is a HINT", __func__); // work as NOP + Write32(EncodeDJSk12(Opcode32::ADDI_D, rd, rj, si12)); +} + +void LoongArch64Emitter::ADDU16I_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si16) { + _assert_msg_(rd != R_ZERO || (rj == R0 && si16 == 0), "%s write to zero is a HINT", __func__); // work as NOP + Write32(EncodeDJSk16(Opcode32::ADDU16I_D, rd, rj, si16)); +} + +void LoongArch64Emitter::ALSL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + _assert_msg_( sa2 >= 1 && sa2 <= 4, "%s shift out of range", __func__); + Write32(EncodeDJKUa2pp1(Opcode32::ALSL_W, rd, rj, rk, sa2)); +} + +void LoongArch64Emitter::ALSL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + _assert_msg_( sa2 >= 1 && sa2 <= 4, "%s shift out of range", __func__); + Write32(EncodeDJKUa2pp1(Opcode32::ALSL_D, rd, rj, rk, sa2)); +} + +void LoongArch64Emitter::ALSL_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + _assert_msg_( sa2 >= 1 && sa2 <= 4, "%s shift out of range", __func__); + Write32(EncodeDJKUa2pp1(Opcode32::ALSL_WU, rd, rj, rk, sa2)); +} + +void LoongArch64Emitter::LU12I_W(LoongArch64Reg rd, s32 si20) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDSj20(Opcode32::LU12I_W, rd, si20)); +} + +void LoongArch64Emitter::LU32I_D(LoongArch64Reg rd, s32 si20) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDSj20(Opcode32::LU32I_D, rd, si20)); +} + +void LoongArch64Emitter::LU52I_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk12(Opcode32::LU52I_D, rd, rj, si12)); +} + +void LoongArch64Emitter::SLT(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::SLT, rd, rj, rk)); +} + +void LoongArch64Emitter::SLTU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::SLTU, rd, rj, rk)); +} + +void LoongArch64Emitter::SLTI(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk12(Opcode32::SLTI, rd, rj, si12)); +} + +void LoongArch64Emitter::SLTUI(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk12(Opcode32::SLTUI, rd, rj, si12)); +} + +void LoongArch64Emitter::PCADDI(LoongArch64Reg rd, s32 si20) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDSj20(Opcode32::PCADDI, rd, si20)); +} + +void LoongArch64Emitter::PCADDU12I(LoongArch64Reg rd, s32 si20) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDSj20(Opcode32::PCADDU12I, rd, si20)); +} + +void LoongArch64Emitter::PCADDU18I(LoongArch64Reg rd, s32 si20) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDSj20(Opcode32::PCADDU18I, rd, si20)); +} + +void LoongArch64Emitter::PCALAU12I(LoongArch64Reg rd, s32 si20) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDSj20(Opcode32::PCALAU12I, rd, si20)); +} + +void LoongArch64Emitter::AND(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::AND, rd, rj, rk)); +} + +void LoongArch64Emitter::OR(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::OR, rd, rj, rk)); +} + +void LoongArch64Emitter::NOR(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::NOR, rd, rj, rk)); +} + +void LoongArch64Emitter::XOR(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::XOR, rd, rj, rk)); +} + +void LoongArch64Emitter::ANDN(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::ANDN, rd, rj, rk)); +} + +void LoongArch64Emitter::ORN(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::ORN, rd, rj, rk)); +} + +void LoongArch64Emitter::ANDI(LoongArch64Reg rd, LoongArch64Reg rj, u16 ui12) { + _assert_msg_(rd != R_ZERO || (rj == R0 && ui12 == 0), "%s write to zero is a HINT", __func__); // work as NOP + Write32(EncodeDJUk12(Opcode32::ANDI, rd, rj, ui12)); +} + +void LoongArch64Emitter::ORI(LoongArch64Reg rd, LoongArch64Reg rj, u16 ui12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk12(Opcode32::ORI, rd, rj, ui12)); +} + +void LoongArch64Emitter::XORI(LoongArch64Reg rd, LoongArch64Reg rj, u16 ui12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk12(Opcode32::XORI, rd, rj, ui12)); +} + +void LoongArch64Emitter::MUL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MUL_W, rd, rj, rk)); +} + +void LoongArch64Emitter::MULH_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MULH_W, rd, rj, rk)); +} + +void LoongArch64Emitter::MULH_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MULH_WU, rd, rj, rk)); +} + +void LoongArch64Emitter::MUL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MUL_D, rd, rj, rk)); +} + +void LoongArch64Emitter::MULH_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MULH_D, rd, rj, rk)); +} + +void LoongArch64Emitter::MULH_DU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MULH_DU, rd, rj, rk)); +} + +void LoongArch64Emitter::MULW_D_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MULW_D_W, rd, rj, rk)); +} + +void LoongArch64Emitter::MULW_D_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MULW_D_WU, rd, rj, rk)); +} + +void LoongArch64Emitter::DIV_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::DIV_W, rd, rj, rk)); +} + +void LoongArch64Emitter::MOD_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MOD_W, rd, rj, rk)); +} + +void LoongArch64Emitter::DIV_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::DIV_WU, rd, rj, rk)); +} + +void LoongArch64Emitter::MOD_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MOD_WU, rd, rj, rk)); +} + +void LoongArch64Emitter::DIV_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::DIV_D, rd, rj, rk)); +} + +void LoongArch64Emitter::MOD_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MOD_D, rd, rj, rk)); +} + +void LoongArch64Emitter::DIV_DU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::DIV_DU, rd, rj, rk)); +} + +void LoongArch64Emitter::MOD_DU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MOD_DU, rd, rj, rk)); +} + +void LoongArch64Emitter::SLL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::SLL_W, rd, rj, rk)); +} + +void LoongArch64Emitter::SRL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::SRL_W, rd, rj, rk)); +} + +void LoongArch64Emitter::SRA_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::SRA_W, rd, rj, rk)); +} + +void LoongArch64Emitter::ROTR_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::ROTR_W, rd, rj, rk)); +} + +void LoongArch64Emitter::SLLI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk5(Opcode32::SLLI_W, rd, rj, ui5)); +} + +void LoongArch64Emitter::SRLI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk5(Opcode32::SRLI_W, rd, rj, ui5)); +} + +void LoongArch64Emitter::SRAI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk5(Opcode32::SRAI_W, rd, rj, ui5)); +} + +void LoongArch64Emitter::ROTRI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk5(Opcode32::ROTRI_W, rd, rj, ui5)); +} + +void LoongArch64Emitter::SLL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::SLL_D, rd, rj, rk)); +} + +void LoongArch64Emitter::SRL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::SRL_D, rd, rj, rk)); +} + +void LoongArch64Emitter::SRA_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::SRA_D, rd, rj, rk)); +} + +void LoongArch64Emitter::ROTR_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::ROTR_D, rd, rj, rk)); +} + +void LoongArch64Emitter::SLLI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk6(Opcode32::SLLI_D, rd, rj, ui6)); +} + +void LoongArch64Emitter::SRLI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk6(Opcode32::SRLI_D, rd, rj, ui6)); +} + +void LoongArch64Emitter::SRAI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk6(Opcode32::SRAI_D, rd, rj, ui6)); +} + +void LoongArch64Emitter::ROTRI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk6(Opcode32::ROTRI_D, rd, rj, ui6)); +} + +void LoongArch64Emitter::EXT_W_B(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::EXT_W_B, rd, rj)); +} + +void LoongArch64Emitter::EXT_W_H(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::EXT_W_H, rd, rj)); +} + +void LoongArch64Emitter::CLO_W(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::CLO_W, rd, rj)); +} + +void LoongArch64Emitter::CLO_D(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::CLO_D, rd, rj)); +} + +void LoongArch64Emitter::CLZ_W(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::CLZ_W, rd, rj)); +} + +void LoongArch64Emitter::CLZ_D(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::CLZ_D, rd, rj)); +} + +void LoongArch64Emitter::CTO_W(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::CTO_W, rd, rj)); +} + +void LoongArch64Emitter::CTO_D(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::CTO_D, rd, rj)); +} + +void LoongArch64Emitter::CTZ_W(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::CTZ_W, rd, rj)); +} + +void LoongArch64Emitter::CTZ_D(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::CTZ_D, rd, rj)); +} + +void LoongArch64Emitter::BYTEPICK_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJKUa2(Opcode32::BYTEPICK_W, rd, rj, rk, sa2)); +} + +void LoongArch64Emitter::BYTEPICK_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa3) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJKUa2(Opcode32::BYTEPICK_D, rd, rj, rk, sa3)); +} + +void LoongArch64Emitter::REVB_2H(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::REVB_2H, rd, rj)); +} + +void LoongArch64Emitter::REVB_4H(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::REVB_4H, rd, rj)); +} + +void LoongArch64Emitter::REVB_2W(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::REVB_2W, rd, rj)); +} + +void LoongArch64Emitter::REVB_D(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::REVB_D, rd, rj)); +} + +void LoongArch64Emitter::BITREV_4B(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::BITREV_4B, rd, rj)); +} + +void LoongArch64Emitter::BITREV_8B(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::BITREV_8B, rd, rj)); +} + +void LoongArch64Emitter::BITREV_W(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::BITREV_W, rd, rj)); +} + +void LoongArch64Emitter::BITREV_D(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::BITREV_D, rd, rj)); +} + +void LoongArch64Emitter::BSTRINS_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 msbw, u8 lsbw) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk5Um5(Opcode32::BSTRINS_W, rd, rj, msbw, lsbw)); +} + +void LoongArch64Emitter::BSTRINS_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 msbd, u8 lsbd) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk6Um6(Opcode32::BSTRINS_D, rd, rj, msbd, lsbd)); +} + +void LoongArch64Emitter::BSTRPICK_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 msbw, u8 lsbw) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk5Um5(Opcode32::BSTRPICK_W, rd, rj, msbw, lsbw)); +} + +void LoongArch64Emitter::BSTRPICK_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 msbd, u8 lsbd) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJUk6Um6(Opcode32::BSTRPICK_D, rd, rj, msbd, lsbd)); +} + +void LoongArch64Emitter::MASKEQZ(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MASKEQZ, rd, rj, rk)); +} + +void LoongArch64Emitter::MASKNEZ(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::MASKNEZ, rd, rj, rk)); +} + +void LoongArch64Emitter::BEQ(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) { + _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst); + _assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__); + ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer(); + Write32(EncodeJDSk16ps2(Opcode32::BEQ, rj, rd, (s32)distance)); +} + +void LoongArch64Emitter::BNE(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) { + _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst); + _assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__); + ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer(); + Write32(EncodeJDSk16ps2(Opcode32::BNE, rj, rd, (s32)distance)); +} + +void LoongArch64Emitter::BLT(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) { + _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst); + _assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__); + ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer(); + Write32(EncodeJDSk16ps2(Opcode32::BLT, rj, rd, (s32)distance)); +} + +void LoongArch64Emitter::BGE(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) { + _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst); + _assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__); + ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer(); + Write32(EncodeJDSk16ps2(Opcode32::BGE, rj, rd, (s32)distance)); +} + +void LoongArch64Emitter::BLTU(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) { + _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst); + _assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__); + ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer(); + Write32(EncodeJDSk16ps2(Opcode32::BLTU, rj, rd, (s32)distance)); +} + +void LoongArch64Emitter::BGEU(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst) { + _assert_msg_(BranchInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst); + _assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__); + ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer(); + Write32(EncodeJDSk16ps2(Opcode32::BGEU, rj, rd, (s32)distance)); +} + +FixupBranch LoongArch64Emitter::BEQ(LoongArch64Reg rj, LoongArch64Reg rd) { + FixupBranch fixup{ GetCodePointer(), FixupBranchType::B }; + Write32(EncodeJDSk16ps2(Opcode32::BEQ, rj, rd, 0)); + return fixup; +} + +FixupBranch LoongArch64Emitter::BNE(LoongArch64Reg rj, LoongArch64Reg rd) { + FixupBranch fixup{ GetCodePointer(), FixupBranchType::B }; + Write32(EncodeJDSk16ps2(Opcode32::BNE, rj, rd, 0)); + return fixup; +} + +FixupBranch LoongArch64Emitter::BLT(LoongArch64Reg rj, LoongArch64Reg rd) { + FixupBranch fixup{ GetCodePointer(), FixupBranchType::B }; + Write32(EncodeJDSk16ps2(Opcode32::BLT, rj, rd, 0)); + return fixup; +} + +FixupBranch LoongArch64Emitter::BGE(LoongArch64Reg rj, LoongArch64Reg rd) { + FixupBranch fixup{ GetCodePointer(), FixupBranchType::B }; + Write32(EncodeJDSk16ps2(Opcode32::BGE, rj, rd, 0)); + return fixup; +} + +FixupBranch LoongArch64Emitter::BLTU(LoongArch64Reg rj, LoongArch64Reg rd) { + FixupBranch fixup{ GetCodePointer(), FixupBranchType::B }; + Write32(EncodeJDSk16ps2(Opcode32::BLTU, rj, rd, 0)); + return fixup; +} + +FixupBranch LoongArch64Emitter::BGEU(LoongArch64Reg rj, LoongArch64Reg rd) { + FixupBranch fixup{ GetCodePointer(), FixupBranchType::B }; + Write32(EncodeJDSk16ps2(Opcode32::BGEU, rj, rd, 0)); + return fixup; +} + +void LoongArch64Emitter::BEQZ(LoongArch64Reg rj, const void *dst) { + _assert_msg_(BranchZeroInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst); + _assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__); + ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer(); + Write32(EncodeJSd5k16(Opcode32::BEQZ, rj, (s32)distance)); +} + +void LoongArch64Emitter::BNEZ(LoongArch64Reg rj, const void *dst) { + _assert_msg_(BranchZeroInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst); + _assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__); + ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer(); + Write32(EncodeJSd5k16(Opcode32::BNEZ, rj, (s32)distance)); +} + +FixupBranch LoongArch64Emitter::BEQZ(LoongArch64Reg rj) { + FixupBranch fixup{ GetCodePointer(), FixupBranchType::BZ }; + Write32(EncodeJSd5k16(Opcode32::BEQZ, rj, 0)); + return fixup; +} + +FixupBranch LoongArch64Emitter::BNEZ(LoongArch64Reg rj) { + FixupBranch fixup{ GetCodePointer(), FixupBranchType::BZ }; + Write32(EncodeJSd5k16(Opcode32::BNEZ, rj, 0)); + return fixup; +} + +void LoongArch64Emitter::B(const void *dst) { + _assert_msg_(JumpInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst); + _assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__); + ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer(); + Write32(EncodeSd10k16ps2(Opcode32::B, (s32)distance)); +} + +void LoongArch64Emitter::BL(const void *dst) { + _assert_msg_(JumpInRange(GetCodePointer(), dst), "%s destination is too far away (%p -> %p)", __func__, GetCodePointer(), dst); + _assert_msg_(((intptr_t)dst & 3) == 0, "%s destination should be aligned to 4", __func__); + ptrdiff_t distance = (intptr_t)dst - (intptr_t)GetCodePointer(); + Write32(EncodeSd10k16ps2(Opcode32::BL, (s32)distance)); +} + +FixupBranch LoongArch64Emitter::B() { + FixupBranch fixup{ GetCodePointer(), FixupBranchType::J }; + Write32(EncodeSd10k16ps2(Opcode32::B, 0)); + return fixup; +} + +FixupBranch LoongArch64Emitter::BL() { + FixupBranch fixup{ GetCodePointer(), FixupBranchType::J }; + Write32(EncodeSd10k16ps2(Opcode32::BL, 0)); + return fixup; +} + +void LoongArch64Emitter::JIRL(LoongArch64Reg rd, LoongArch64Reg rj, s32 offs16) { + Write32(EncodeDJSk16ps2(Opcode32::JIRL, rd, rj, offs16)); +} + +void LoongArch64Emitter::LD_B(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk12(Opcode32::LD_B, rd, rj, si12)); +} + +void LoongArch64Emitter::LD_H(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk12(Opcode32::LD_H, rd, rj, si12)); +} + +void LoongArch64Emitter::LD_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk12(Opcode32::LD_W, rd, rj, si12)); +} + +void LoongArch64Emitter::LD_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk12(Opcode32::LD_D, rd, rj, si12)); +} + +void LoongArch64Emitter::LD_BU(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk12(Opcode32::LD_BU, rd, rj, si12)); +} + +void LoongArch64Emitter::LD_HU(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk12(Opcode32::LD_HU, rd, rj, si12)); +} + +void LoongArch64Emitter::LD_WU(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk12(Opcode32::LD_WU, rd, rj, si12)); +} + +void LoongArch64Emitter::ST_B(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + Write32(EncodeDJSk12(Opcode32::ST_B, rd, rj, si12)); +} + +void LoongArch64Emitter::ST_H(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + Write32(EncodeDJSk12(Opcode32::ST_H, rd, rj, si12)); +} + +void LoongArch64Emitter::ST_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + Write32(EncodeDJSk12(Opcode32::ST_W, rd, rj, si12)); +} + +void LoongArch64Emitter::ST_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12) { + Write32(EncodeDJSk12(Opcode32::ST_D, rd, rj, si12)); +} + +void LoongArch64Emitter::LDX_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDX_B, rd, rj, rk)); +} + +void LoongArch64Emitter::LDX_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDX_H, rd, rj, rk)); +} + +void LoongArch64Emitter::LDX_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDX_W, rd, rj, rk)); +} + +void LoongArch64Emitter::LDX_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDX_D, rd, rj, rk)); +} + +void LoongArch64Emitter::LDX_BU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDX_BU, rd, rj, rk)); +} + +void LoongArch64Emitter::LDX_HU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDX_HU, rd, rj, rk)); +} + +void LoongArch64Emitter::LDX_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDX_WU, rd, rj, rk)); +} + +void LoongArch64Emitter::STX_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STX_B, rd, rj, rk)); +} + +void LoongArch64Emitter::STX_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STX_H, rd, rj, rk)); +} + +void LoongArch64Emitter::STX_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STX_W, rd, rj, rk)); +} + +void LoongArch64Emitter::STX_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STX_D, rd, rj, rk)); +} + +void LoongArch64Emitter::LDPTR_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk14ps2(Opcode32::LDPTR_W, rd, rj, si14)); +} + +void LoongArch64Emitter::LDPTR_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk14ps2(Opcode32::LDPTR_W, rd, rj, si14)); +} + +void LoongArch64Emitter::STPTR_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk14ps2(Opcode32::LDPTR_W, rd, rj, si14)); +} + +void LoongArch64Emitter::STPTR_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJSk14ps2(Opcode32::LDPTR_W, rd, rj, si14)); +} + +void LoongArch64Emitter::PRELD(u32 hint, LoongArch64Reg rj, s16 si12) { + _assert_msg_(rj != R_ZERO, "%s load from zero is a HINT", __func__); + _assert_msg_(hint == 0 || hint == 8, "%s hint represents a NOP", __func__); + Write32(EncodeUd5JSk12(Opcode32::PRELD, hint, rj, si12)); +} + +void LoongArch64Emitter::PRELDX(u32 hint, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rj != R_ZERO, "%s load from zero is a HINT", __func__); + _assert_msg_(hint == 0 || hint == 8, "%s hint represents a NOP", __func__); + Write32(EncodeUd5JK(Opcode32::PRELDX, hint, rj, rk)); +} + +void LoongArch64Emitter::LDGT_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDGT_B, rd, rj, rk)); +} + +void LoongArch64Emitter::LDGT_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDGT_H, rd, rj, rk)); +} + +void LoongArch64Emitter::LDGT_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDGT_W, rd, rj, rk)); +} + +void LoongArch64Emitter::LDGT_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDGT_D, rd, rj, rk)); +} + +void LoongArch64Emitter::LDLE_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDLE_B, rd, rj, rk)); +} + +void LoongArch64Emitter::LDLE_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDLE_H, rd, rj, rk)); +} + +void LoongArch64Emitter::LDLE_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDLE_W, rd, rj, rk)); +} + +void LoongArch64Emitter::LDLE_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::LDLE_D, rd, rj, rk)); +} + +void LoongArch64Emitter::STGT_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STGT_B, rd, rj, rk)); +} + +void LoongArch64Emitter::STGT_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STGT_H, rd, rj, rk)); +} + +void LoongArch64Emitter::STGT_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STGT_W, rd, rj, rk)); +} + +void LoongArch64Emitter::STGT_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STGT_D, rd, rj, rk)); +} + +void LoongArch64Emitter::STLE_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STLE_B, rd, rj, rk)); +} + +void LoongArch64Emitter::STLE_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STLE_H, rd, rj, rk)); +} + +void LoongArch64Emitter::STLE_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STLE_W, rd, rj, rk)); +} + +void LoongArch64Emitter::STLE_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJK(Opcode32::STLE_D, rd, rj, rk)); +} + +void LoongArch64Emitter::AMSWAP_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMSWAP_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMSWAP_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMSWAP_DB_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMSWAP_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMSWAP_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMSWAP_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMSWAP_DB_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMADD_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMADD_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMADD_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMADD_DB_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMADD_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMADD_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMADD_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMADD_DB_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMAND_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMAND_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMAND_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMAND_DB_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMAND_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMAND_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMAND_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMAND_DB_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMOR_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMOR_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMOR_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMOR_DB_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMOR_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMOR_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMOR_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMOR_DB_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMXOR_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMXOR_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMXOR_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMXOR_DB_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMXOR_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMXOR_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMXOR_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMXOR_DB_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMAX_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMAX_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMAX_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMAX_DB_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMAX_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMAX_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMAX_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMAX_DB_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMIN_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMIN_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMIN_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMIN_DB_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMIN_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMIN_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMIN_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMIN_DB_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMAX_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMAX_WU, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMAX_DB_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMAX_DB_WU, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMAX_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMAX_DU, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMAX_DB_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMAX_DB_DU, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMIN_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMIN_WU, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMIN_DB_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMIN_DB_WU, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMIN_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMIN_DU, rd, rk, rj)); +} + +void LoongArch64Emitter::AMMIN_DB_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMMIN_DB_DU, rd, rk, rj)); +} + +void LoongArch64Emitter::AMSWAP_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMSWAP_B, rd, rk, rj)); +} + +void LoongArch64Emitter::AMSWAP_DB_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMSWAP_DB_B, rd, rk, rj)); +} + +void LoongArch64Emitter::AMSWAP_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMSWAP_H, rd, rk, rj)); +} + +void LoongArch64Emitter::AMSWAP_DB_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMSWAP_DB_H, rd, rk, rj)); +} + +void LoongArch64Emitter::AMADD_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMADD_B, rd, rk, rj)); +} + +void LoongArch64Emitter::AMADD_DB_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMADD_DB_B, rd, rk, rj)); +} + +void LoongArch64Emitter::AMADD_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMADD_H, rd, rk, rj)); +} + +void LoongArch64Emitter::AMADD_DB_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMADD_DB_H, rd, rk, rj)); +} + +void LoongArch64Emitter::AMCAS_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMCAS_B, rd, rk, rj)); +} + +void LoongArch64Emitter::AMCAS_DB_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMCAS_DB_B, rd, rk, rj)); +} + +void LoongArch64Emitter::AMCAS_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMCAS_H, rd, rk, rj)); +} + +void LoongArch64Emitter::AMCAS_DB_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMCAS_DB_H, rd, rk, rj)); +} + +void LoongArch64Emitter::AMCAS_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMCAS_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMCAS_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMCAS_DB_W, rd, rk, rj)); +} + +void LoongArch64Emitter::AMCAS_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMCAS_D, rd, rk, rj)); +} + +void LoongArch64Emitter::AMCAS_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::AMCAS_DB_D, rd, rk, rj)); +} + +void LoongArch64Emitter::CRC_W_B_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::CRC_W_B_W, rd, rk, rj)); +} + +void LoongArch64Emitter::CRC_W_H_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::CRC_W_H_W, rd, rk, rj)); +} + +void LoongArch64Emitter::CRC_W_W_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::CRC_W_W_W, rd, rk, rj)); +} + +void LoongArch64Emitter::CRC_W_D_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::CRC_W_D_W, rd, rk, rj)); +} + +void LoongArch64Emitter::CRCC_W_B_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::CRCC_W_B_W, rd, rk, rj)); +} + +void LoongArch64Emitter::CRCC_W_H_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::CRCC_W_H_W, rd, rk, rj)); +} + +void LoongArch64Emitter::CRCC_W_W_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::CRCC_W_W_W, rd, rk, rj)); +} + +void LoongArch64Emitter::CRCC_W_D_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDKJ(Opcode32::CRCC_W_D_W, rd, rk, rj)); +} + +void LoongArch64Emitter::SYSCALL(u16 code) { + Write32(EncodeUd15(Opcode32::SYSCALL, code)); +} + +void LoongArch64Emitter::BREAK(u16 code) { + Write32(EncodeUd15(Opcode32::BREAK, code)); +} + +void LoongArch64Emitter::ASRTLE_D(LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeJK(Opcode32::ASRTLE_D, rj, rk)); +} + +void LoongArch64Emitter::ASRTGT_D(LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeJK(Opcode32::ASRTGT_D, rj, rk)); +} + +void LoongArch64Emitter::RDTIMEL_W(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::RDTIMEL_W, rd, rj)); +} + +void LoongArch64Emitter::RDTIMEH_W(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::RDTIMEH_W, rd, rj)); +} + +void LoongArch64Emitter::RDTIME_D(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::RDTIME_D, rd, rj)); +} + +void LoongArch64Emitter::CPUCFG(LoongArch64Reg rd, LoongArch64Reg rj) { + _assert_msg_(rd != R_ZERO, "%s write to zero is a HINT", __func__); + Write32(EncodeDJ(Opcode32::CPUCFG, rd, rj)); +} + +void LoongArch64Emitter::FADD_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FADD_S, fd, fj, fk)); +} + +void LoongArch64Emitter::FADD_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FADD_D, fd, fj, fk)); +} + +void LoongArch64Emitter::FSUB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FSUB_S, fd, fj, fk)); +} + +void LoongArch64Emitter::FSUB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FSUB_D, fd, fj, fk)); +} + +void LoongArch64Emitter::FMUL_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FMUL_S, fd, fj, fk)); +} + +void LoongArch64Emitter::FMUL_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FMUL_D, fd, fj, fk)); +} + +void LoongArch64Emitter::FDIV_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FDIV_S, fd, fj, fk)); +} + +void LoongArch64Emitter::FDIV_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FDIV_D, fd, fj, fk)); +} + +void LoongArch64Emitter::FMADD_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) { + Write32(EncodeFdFjFkFa(Opcode32::FMADD_S, fd, fj, fk, fa)); +} + +void LoongArch64Emitter::FMADD_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) { + Write32(EncodeFdFjFkFa(Opcode32::FMADD_D, fd, fj, fk, fa)); +} + +void LoongArch64Emitter::FMSUB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) { + Write32(EncodeFdFjFkFa(Opcode32::FMSUB_S, fd, fj, fk, fa)); +} + +void LoongArch64Emitter::FMSUB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) { + Write32(EncodeFdFjFkFa(Opcode32::FMSUB_D, fd, fj, fk, fa)); +} + +void LoongArch64Emitter::FNMADD_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) { + Write32(EncodeFdFjFkFa(Opcode32::FNMADD_S, fd, fj, fk, fa)); +} + +void LoongArch64Emitter::FNMADD_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) { + Write32(EncodeFdFjFkFa(Opcode32::FNMADD_D, fd, fj, fk, fa)); +} + +void LoongArch64Emitter::FNMSUB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) { + Write32(EncodeFdFjFkFa(Opcode32::FNMSUB_S, fd, fj, fk, fa)); +} + +void LoongArch64Emitter::FNMSUB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa) { + Write32(EncodeFdFjFkFa(Opcode32::FNMSUB_D, fd, fj, fk, fa)); +} + +void LoongArch64Emitter::FMAX_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FMAX_S, fd, fj, fk)); +} + +void LoongArch64Emitter::FMAX_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FMAX_D, fd, fj, fk)); +} + +void LoongArch64Emitter::FMIN_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FMIN_S, fd, fj, fk)); +} + +void LoongArch64Emitter::FMIN_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FMIN_D, fd, fj, fk)); +} + +void LoongArch64Emitter::FMAXA_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FMAXA_S, fd, fj, fk)); +} + +void LoongArch64Emitter::FMAXA_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FMAXA_D, fd, fj, fk)); +} + +void LoongArch64Emitter::FMINA_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FMINA_S, fd, fj, fk)); +} + +void LoongArch64Emitter::FMINA_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FMINA_D, fd, fj, fk)); +} + +void LoongArch64Emitter::FABS_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FABS_S, fd, fj)); +} + +void LoongArch64Emitter::FABS_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FABS_D, fd, fj)); +} + +void LoongArch64Emitter::FNEG_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FNEG_S, fd, fj)); +} + +void LoongArch64Emitter::FNEG_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FNEG_D, fd, fj)); +} + +void LoongArch64Emitter::FSQRT_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FSQRT_S, fd, fj)); +} + +void LoongArch64Emitter::FSQRT_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FSQRT_D, fd, fj)); +} + +void LoongArch64Emitter::FRECIP_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FRECIP_S, fd, fj)); +} + +void LoongArch64Emitter::FRECIP_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FRECIP_D, fd, fj)); +} + +void LoongArch64Emitter::FRSQRT_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FRSQRT_S, fd, fj)); +} + +void LoongArch64Emitter::FRSQRT_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FRSQRT_D, fd, fj)); +} + +void LoongArch64Emitter::FSCALEB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FSCALEB_S, fd, fj, fk)); +} + +void LoongArch64Emitter::FSCALEB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FSCALEB_D, fd, fj, fk)); +} + +void LoongArch64Emitter::FLOGB_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FLOGB_S, fd, fj)); +} + +void LoongArch64Emitter::FLOGB_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FLOGB_D, fd, fj)); +} + +void LoongArch64Emitter::FCOPYSIGN_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FCOPYSIGN_S, fd, fj, fk)); +} + +void LoongArch64Emitter::FCOPYSIGN_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk) { + Write32(EncodeFdFjFk(Opcode32::FCOPYSIGN_D, fd, fj, fk)); +} + +void LoongArch64Emitter::FCLASS_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FCLASS_S, fd, fj)); +} + +void LoongArch64Emitter::FCLASS_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FCLASS_D, fd, fj)); +} + +void LoongArch64Emitter::FRECIPE_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FRECIPE_S, fd, fj)); +} + +void LoongArch64Emitter::FRECIPE_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FRECIPE_D, fd, fj)); +} + +void LoongArch64Emitter::FRSQRTE_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FRSQRTE_S, fd, fj)); +} + +void LoongArch64Emitter::FRSQRTE_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FRSQRTE_D, fd, fj)); +} + +void LoongArch64Emitter::FCMP_COND_S(LoongArch64CFR cd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Fcond cond) { + Write32(EncodeCdFjFkFcond(Opcode32::FCMP_COND_S, cd, fj, fk, cond)); +} + +void LoongArch64Emitter::FCMP_COND_D(LoongArch64CFR cd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Fcond cond) { + Write32(EncodeCdFjFkFcond(Opcode32::FCMP_COND_D, cd, fj, fk, cond)); +} + +void LoongArch64Emitter::FCVT_S_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FCVT_S_D, fd, fj)); +} + +void LoongArch64Emitter::FCVT_D_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FCVT_D_S, fd, fj)); +} + +void LoongArch64Emitter::FFINT_S_W(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FFINT_S_W, fd, fj)); +} + +void LoongArch64Emitter::FFINT_S_L(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FFINT_S_L, fd, fj)); +} + +void LoongArch64Emitter::FFINT_D_W(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FFINT_D_W, fd, fj)); +} + +void LoongArch64Emitter::FFINT_D_L(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FFINT_D_L, fd, fj)); +} + +void LoongArch64Emitter::FTINT_W_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINT_W_S, fd, fj)); +} + +void LoongArch64Emitter::FTINT_W_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINT_W_D, fd, fj)); +} + +void LoongArch64Emitter::FTINT_L_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINT_L_S, fd, fj)); +} + +void LoongArch64Emitter::FTINT_L_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINT_L_D, fd, fj)); +} + +void LoongArch64Emitter::FTINTRM_W_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRM_W_S, fd, fj)); +} + +void LoongArch64Emitter::FTINTRM_W_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRM_W_D, fd, fj)); +} + +void LoongArch64Emitter::FTINTRM_L_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRM_L_S, fd, fj)); +} + +void LoongArch64Emitter::FTINTRM_L_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRM_L_D, fd, fj)); +} + +void LoongArch64Emitter::FTINTRP_W_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRP_W_S, fd, fj)); +} + +void LoongArch64Emitter::FTINTRP_W_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRP_W_D, fd, fj)); +} + +void LoongArch64Emitter::FTINTRP_L_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRP_L_S, fd, fj)); +} + +void LoongArch64Emitter::FTINTRP_L_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRP_L_D, fd, fj)); +} + +void LoongArch64Emitter::FTINTRZ_W_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRZ_W_S, fd, fj)); +} + +void LoongArch64Emitter::FTINTRZ_W_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRZ_W_D, fd, fj)); +} + +void LoongArch64Emitter::FTINTRZ_L_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRZ_L_S, fd, fj)); +} + +void LoongArch64Emitter::FTINTRZ_L_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRZ_L_D, fd, fj)); +} + +void LoongArch64Emitter::FTINTRNE_W_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRNE_W_S, fd, fj)); +} + +void LoongArch64Emitter::FTINTRNE_W_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRNE_W_D, fd, fj)); +} + +void LoongArch64Emitter::FTINTRNE_L_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRNE_L_S, fd, fj)); +} + +void LoongArch64Emitter::FTINTRNE_L_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FTINTRNE_L_D, fd, fj)); +} + +void LoongArch64Emitter::FRINT_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FRINT_S, fd, fj)); +} + +void LoongArch64Emitter::FRINT_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FRINT_D, fd, fj)); +} + +void LoongArch64Emitter::FMOV_S(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FMOV_S, fd, fj)); +} + +void LoongArch64Emitter::FMOV_D(LoongArch64Reg fd, LoongArch64Reg fj) { + Write32(EncodeFdFj(Opcode32::FMOV_D, fd, fj)); +} + +void LoongArch64Emitter::FSEL(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64CFR ca) { + Write32(EncodeFdFjFkCa(Opcode32::FSEL, fd, fj, fk, ca)); +} + +void LoongArch64Emitter::MOVGR2FR_W(LoongArch64Reg fd, LoongArch64Reg rj) { + Write32(EncodeFdJ(Opcode32::MOVGR2FR_W, fd, rj)); +} + +void LoongArch64Emitter::MOVGR2FR_D(LoongArch64Reg fd, LoongArch64Reg rj) { + Write32(EncodeFdJ(Opcode32::MOVGR2FR_D, fd, rj)); +} + +void LoongArch64Emitter::MOVGR2FRH_W(LoongArch64Reg fd, LoongArch64Reg rj) { + Write32(EncodeFdJ(Opcode32::MOVGR2FRH_W, fd, rj)); +} + +void LoongArch64Emitter::MOVFR2GR_S(LoongArch64Reg rd, LoongArch64Reg fj) { + Write32(EncodeDFj(Opcode32::MOVFR2GR_S, rd, fj)); +} + +void LoongArch64Emitter::MOVFR2GR_D(LoongArch64Reg rd, LoongArch64Reg fj) { + Write32(EncodeDFj(Opcode32::MOVFR2GR_D, rd, fj)); +} + +void LoongArch64Emitter::MOVFRH2GR_S(LoongArch64Reg rd, LoongArch64Reg fj) { + Write32(EncodeDFj(Opcode32::MOVFRH2GR_S, rd, fj)); +} + +void LoongArch64Emitter::MOVGR2FCSR(LoongArch64FCSR fcsr, LoongArch64Reg rj) { + Write32(EncodeJUd5(Opcode32::MOVGR2FCSR, fcsr, rj)); +} + +void LoongArch64Emitter::MOVFCSR2GR(LoongArch64Reg rd, LoongArch64FCSR fcsr) { + Write32(EncodeDUj5(Opcode32::MOVFCSR2GR, rd, fcsr)); +} + +void LoongArch64Emitter::MOVFR2CF(LoongArch64CFR cd, LoongArch64Reg fj) { + Write32(EncodeCdFj(Opcode32::MOVFR2CF, cd, fj)); +} + +void LoongArch64Emitter::MOVCF2FR(LoongArch64Reg fd, LoongArch64CFR cj) { + Write32(EncodeFdCj(Opcode32::MOVCF2FR, fd, cj)); +} + +void LoongArch64Emitter::MOVGR2CF(LoongArch64CFR cd, LoongArch64Reg rj) { + Write32(EncodeCdJ(Opcode32::MOVGR2CF, cd, rj)); +} + +void LoongArch64Emitter::MOVCF2GR(LoongArch64Reg rd, LoongArch64CFR cj) { + Write32(EncodeDCj(Opcode32::MOVCF2GR, rd, cj)); +} + +void LoongArch64Emitter::BCEQZ(LoongArch64CFR cj, s32 offs21) { + Write32(EncodeCjSd5k16ps2(Opcode32::BCEQZ, cj, offs21)); +} + +void LoongArch64Emitter::BCNEZ(LoongArch64CFR cj, s32 offs21) { + Write32(EncodeCjSd5k16ps2(Opcode32::BCNEZ, cj, offs21)); +} + +void LoongArch64Emitter::FLD_S(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12) { + Write32(EncodeFdJSk12(Opcode32::FLD_S, fd, rj, si12)); +} + +void LoongArch64Emitter::FLD_D(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12) { + Write32(EncodeFdJSk12(Opcode32::FLD_D, fd, rj, si12)); +} + +void LoongArch64Emitter::FST_S(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12) { + Write32(EncodeFdJSk12(Opcode32::FST_S, fd, rj, si12)); +} + +void LoongArch64Emitter::FST_D(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12) { + Write32(EncodeFdJSk12(Opcode32::FST_D, fd, rj, si12)); +} + +void LoongArch64Emitter::FLDX_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FLDX_S, fd, rj, rk)); +} + +void LoongArch64Emitter::FLDX_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FLDX_D, fd, rj, rk)); +} + +void LoongArch64Emitter::FSTX_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FSTX_S, fd, rj, rk)); +} + +void LoongArch64Emitter::FSTX_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FSTX_D, fd, rj, rk)); +} + +void LoongArch64Emitter::FLDGT_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FLDGT_S, fd, rj, rk)); +} + +void LoongArch64Emitter::FLDGT_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FLDGT_D, fd, rj, rk)); +} + +void LoongArch64Emitter::FLDLE_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FLDLE_S, fd, rj, rk)); +} + +void LoongArch64Emitter::FLDLE_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FLDLE_D, fd, rj, rk)); +} + +void LoongArch64Emitter::FSTGT_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FSTGT_S, fd, rj, rk)); +} + +void LoongArch64Emitter::FSTGT_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FSTGT_D, fd, rj, rk)); +} + +void LoongArch64Emitter::FSTLE_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FSTLE_S, fd, rj, rk)); +} + +void LoongArch64Emitter::FSTLE_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeFdJK(Opcode32::FSTLE_D, fd, rj, rk)); +} + +void LoongArch64Emitter::QuickFLI(int bits, LoongArch64Reg fd, double v, LoongArch64Reg scratchReg) { + if (bits == 64) { + LI(scratchReg, v); + MOVGR2FR_D(fd, scratchReg); + } else if (bits <= 32) { + QuickFLI(32, fd, (float)v, scratchReg); + } else { + _assert_msg_(false, "Unsupported QuickFLI bits"); + } +} + +void LoongArch64Emitter::QuickFLI(int bits, LoongArch64Reg fd, uint32_t pattern, LoongArch64Reg scratchReg) { + if (bits == 32) { + LI(scratchReg, (int32_t)pattern); + MOVGR2FR_W(fd, scratchReg); + } else { + _assert_msg_(false, "Unsupported QuickFLI bits"); + } +} + +void LoongArch64Emitter::QuickFLI(int bits, LoongArch64Reg fd, float v, LoongArch64Reg scratchReg) { + if (bits == 64) { + QuickFLI(32, fd, (double)v, scratchReg); + } else if (bits == 32) { + LI(scratchReg, v); + MOVGR2FR_W(fd, scratchReg); + } else { + _assert_msg_(false, "Unsupported QuickFLI bits"); + } +} + +void LoongArch64Emitter::VFMADD_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) { + Write32(EncodeVdVjVkVa(Opcode32::VFMADD_S, vd, vj, vk, va)); +} + +void LoongArch64Emitter::VFMADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) { + Write32(EncodeVdVjVkVa(Opcode32::VFMADD_D, vd, vj, vk, va)); +} + +void LoongArch64Emitter::VFMSUB_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) { + Write32(EncodeVdVjVkVa(Opcode32::VFMSUB_S, vd, vj, vk, va)); +} + +void LoongArch64Emitter::VFMSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) { + Write32(EncodeVdVjVkVa(Opcode32::VFMSUB_D, vd, vj, vk, va)); +} + +void LoongArch64Emitter::VFNMADD_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) { + Write32(EncodeVdVjVkVa(Opcode32::VFNMADD_S, vd, vj, vk, va)); +} + +void LoongArch64Emitter::VFNMADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) { + Write32(EncodeVdVjVkVa(Opcode32::VFNMADD_D, vd, vj, vk, va)); +} + +void LoongArch64Emitter::VFNMSUB_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) { + Write32(EncodeVdVjVkVa(Opcode32::VFNMSUB_S, vd, vj, vk, va)); +} + +void LoongArch64Emitter::VFNMSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) { + Write32(EncodeVdVjVkVa(Opcode32::VFNMSUB_D, vd, vj, vk, va)); +} + +void LoongArch64Emitter::VFCMP_CAF_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CAF_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SAF_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SAF_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CLT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CLT_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SLT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SLT_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CEQ_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SEQ_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CLE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CLE_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SLE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SLE_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CUN_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CUN_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SUN_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SUN_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CULT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CULT_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SULT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SULT_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CUEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CUEQ_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SUEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SUEQ_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CULE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CULE_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SULE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SULE_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CNE_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SNE_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_COR_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_COR_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SOR_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SOR_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CUNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CUNE_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SUNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SUNE_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CAF_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CAF_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SAF_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SAF_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CLT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CLT_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SLT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SLT_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CEQ_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SEQ_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CLE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CLE_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SLE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SLE_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CUN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CUN_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SUN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SUN_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CULT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CULT_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SULT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SULT_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CUEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CUEQ_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SUEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SUEQ_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CULE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CULE_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SULE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SULE_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CNE_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SNE_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_COR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_COR_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SOR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SOR_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_CUNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_CUNE_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCMP_SUNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCMP_SUNE_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITSEL_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) { + Write32(EncodeVdVjVkVa(Opcode32::VBITSEL_V, vd, vj, vk, va)); +} + +void LoongArch64Emitter::VSHUF_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va) { + Write32(EncodeVdVjVkVa(Opcode32::VSHUF_B, vd, vj, vk, va)); +} + +void LoongArch64Emitter::VLD(LoongArch64Reg vd, LoongArch64Reg rj, s16 si12) { + Write32(EncodeVdJSk12(Opcode32::VLD, vd, rj, si12)); +} + +void LoongArch64Emitter::VST(LoongArch64Reg vd, LoongArch64Reg rj, s16 si12) { + Write32(EncodeVdJSk12(Opcode32::VST, vd, rj, si12)); +} + +void LoongArch64Emitter::VLDREPL_D(LoongArch64Reg vd, LoongArch64Reg rj, s16 si9) { + Write32(EncodeVdJSk9(Opcode32::VLDREPL_D, vd, rj, si9)); +} + +void LoongArch64Emitter::VLDREPL_W(LoongArch64Reg vd, LoongArch64Reg rj, s16 si10) { + Write32(EncodeVdJSk10(Opcode32::VLDREPL_W, vd, rj, si10)); +} + +void LoongArch64Emitter::VLDREPL_H(LoongArch64Reg vd, LoongArch64Reg rj, s16 si11) { + Write32(EncodeVdJSk11(Opcode32::VLDREPL_H, vd, rj, si11)); +} + +void LoongArch64Emitter::VLDREPL_B(LoongArch64Reg vd, LoongArch64Reg rj, s16 si12) { + Write32(EncodeVdJSk12(Opcode32::VLDREPL_B, vd, rj, si12)); +} + +void LoongArch64Emitter::VSTELM_D(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx1) { + Write32(EncodeVdJSk8Un1(Opcode32::VSTELM_D, vd, rj, si8, idx1)); +} + +void LoongArch64Emitter::VSTELM_W(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx2) { + Write32(EncodeVdJSk8Un2(Opcode32::VSTELM_W, vd, rj, si8, idx2)); +} + +void LoongArch64Emitter::VSTELM_H(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx3) { + Write32(EncodeVdJSk8Un3(Opcode32::VSTELM_H, vd, rj, si8, idx3)); +} + +void LoongArch64Emitter::VSTELM_B(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx4) { + Write32(EncodeVdJSk8Un4(Opcode32::VSTELM_B, vd, rj, si8, idx4)); +} + +void LoongArch64Emitter::VLDX(LoongArch64Reg vd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeVdJK(Opcode32::VLDX, vd, rj, rk)); +} + +void LoongArch64Emitter::VSTX(LoongArch64Reg vd, LoongArch64Reg rj, LoongArch64Reg rk) { + Write32(EncodeVdJK(Opcode32::VSTX, vd, rj, rk)); +} + +void LoongArch64Emitter::VSEQ_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSEQ_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSEQ_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSEQ_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSEQ_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSEQ_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSEQ_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLE_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLE_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLE_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLE_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLE_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLE_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLE_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLE_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLE_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLE_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLE_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLE_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLE_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLE_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLE_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLT_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLT_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLT_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLT_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLT_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLT_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLT_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLT_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLT_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLT_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLT_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLT_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLT_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLT_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLT_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VADD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADD_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VADD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADD_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VADD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADD_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADD_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUB_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUB_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUB_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUB_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUB_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUB_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUB_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_H_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_W_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_D_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_Q_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWEV_H_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWEV_W_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWEV_D_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWEV_Q_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_H_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_W_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_D_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_Q_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWOD_H_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWOD_W_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWOD_D_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWOD_Q_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_H_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_W_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_D_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_Q_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWEV_H_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWEV_W_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWEV_D_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWEV_Q_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_H_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_W_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_D_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_Q_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWOD_H_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWOD_W_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWOD_D_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUBWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUBWOD_Q_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_H_BU_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_W_HU_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_D_WU_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWEV_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWEV_Q_DU_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_H_BU_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_W_HU_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_D_WU_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDWOD_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDWOD_Q_DU_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSADD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSADD_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSADD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSADD_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSADD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSADD_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSADD_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSUB_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSUB_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSUB_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSUB_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSUB_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSUB_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSUB_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSADD_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSADD_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSADD_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSADD_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSADD_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSADD_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSADD_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSADD_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSUB_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSUB_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSUB_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSUB_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSUB_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSUB_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSUB_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSUB_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VHADDW_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHADDW_H_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VHADDW_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHADDW_W_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VHADDW_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHADDW_D_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VHADDW_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHADDW_Q_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VHSUBW_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHSUBW_H_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VHSUBW_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHSUBW_W_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VHSUBW_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHSUBW_D_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VHSUBW_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHSUBW_Q_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VHADDW_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHADDW_HU_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VHADDW_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHADDW_WU_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VHADDW_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHADDW_DU_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VHADDW_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHADDW_QU_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VHSUBW_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHSUBW_HU_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VHSUBW_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHSUBW_WU_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VHSUBW_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHSUBW_DU_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VHSUBW_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VHSUBW_QU_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDA_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDA_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDA_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDA_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDA_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDA_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VADDA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADDA_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VABSD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VABSD_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VABSD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VABSD_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VABSD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VABSD_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VABSD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VABSD_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VABSD_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VABSD_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VABSD_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VABSD_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VABSD_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VABSD_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VABSD_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VABSD_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVG_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVG_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVG_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVG_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVG_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVG_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVG_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVG_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVG_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVG_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVG_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVG_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVG_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVG_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVG_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVG_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVGR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVGR_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVGR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVGR_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVGR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVGR_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVGR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVGR_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVGR_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVGR_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVGR_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVGR_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVGR_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVGR_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VAVGR_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAVGR_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMAX_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMAX_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMAX_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMAX_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMAX_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMAX_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMAX_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMAX_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMIN_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMIN_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMIN_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMIN_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMIN_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMIN_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMIN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMIN_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMAX_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMAX_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMAX_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMAX_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMAX_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMAX_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMAX_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMAX_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMIN_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMIN_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMIN_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMIN_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMIN_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMIN_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMIN_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMIN_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUL_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUL_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUL_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUL_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUH_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUH_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUH_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUH_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUH_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUH_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUH_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUH_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUH_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUH_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUH_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUH_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUH_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUH_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMUH_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMUH_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_H_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_W_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_D_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_Q_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_H_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_W_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_D_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_Q_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_H_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_W_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_D_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_Q_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_H_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_W_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_D_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_Q_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_H_BU_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_W_HU_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_D_WU_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWEV_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWEV_Q_DU_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_H_BU_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_W_HU_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_D_WU_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMULWOD_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMULWOD_Q_DU_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADD_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADD_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADD_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADD_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMSUB_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMSUB_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMSUB_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMSUB_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMSUB_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMSUB_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMSUB_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_H_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_W_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_D_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_Q_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_H_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_W_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_D_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_Q_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_H_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_W_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_D_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_Q_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_H_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_W_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_D_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_Q_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_H_BU_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_W_HU_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_D_WU_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWEV_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWEV_Q_DU_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_H_BU_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_W_HU_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_D_WU_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMADDWOD_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMADDWOD_Q_DU_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VDIV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VDIV_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VDIV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VDIV_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VDIV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VDIV_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VDIV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VDIV_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VMOD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMOD_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VMOD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMOD_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VMOD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMOD_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VMOD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMOD_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VDIV_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VDIV_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VDIV_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VDIV_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VDIV_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VDIV_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VDIV_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VDIV_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMOD_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMOD_BU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMOD_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMOD_HU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMOD_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMOD_WU, vd, vj, vk)); +} + +void LoongArch64Emitter::VMOD_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VMOD_DU, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLL_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLL_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLL_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSLL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSLL_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRL_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRL_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRL_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRL_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRA_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRA_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRA_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRA_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRA_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRA_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRA_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VROTR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VROTR_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VROTR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VROTR_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VROTR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VROTR_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VROTR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VROTR_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRLR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRLR_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRLR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRLR_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRLR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRLR_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRLR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRLR_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRAR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRAR_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRAR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRAR_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRAR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRAR_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRAR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRAR_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRLN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRLN_B_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRLN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRLN_H_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRLN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRLN_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRAN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRAN_B_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRAN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRAN_H_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRAN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRAN_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRLRN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRLRN_B_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRLRN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRLRN_H_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRLRN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRLRN_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRARN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRARN_B_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRARN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRARN_H_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSRARN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSRARN_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLN_B_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLN_H_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLN_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRAN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRAN_B_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRAN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRAN_H_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRAN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRAN_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLRN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLRN_B_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLRN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLRN_H_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLRN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLRN_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRARN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRARN_B_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRARN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRARN_H_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRARN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRARN_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLN_BU_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLN_HU_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLN_WU_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRAN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRAN_BU_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRAN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRAN_HU_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRAN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRAN_WU_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLRN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLRN_BU_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLRN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLRN_HU_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRLRN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRLRN_WU_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRARN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRARN_BU_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRARN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRARN_HU_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSSRARN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSSRARN_WU_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITCLR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITCLR_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITCLR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITCLR_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITCLR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITCLR_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITCLR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITCLR_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITSET_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITSET_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITSET_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITSET_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITSET_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITSET_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITSET_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITSET_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITREV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITREV_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITREV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITREV_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITREV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITREV_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VBITREV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VBITREV_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VPACKEV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPACKEV_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VPACKEV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPACKEV_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VPACKEV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPACKEV_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VPACKEV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPACKEV_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VPACKOD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPACKOD_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VPACKOD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPACKOD_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VPACKOD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPACKOD_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VPACKOD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPACKOD_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VILVL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VILVL_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VILVL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VILVL_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VILVL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VILVL_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VILVL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VILVL_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VILVH_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VILVH_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VILVH_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VILVH_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VILVH_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VILVH_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VILVH_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VILVH_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VPICKEV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPICKEV_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VPICKEV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPICKEV_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VPICKEV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPICKEV_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VPICKEV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPICKEV_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VPICKOD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPICKOD_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VPICKOD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPICKOD_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VPICKOD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPICKOD_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VPICKOD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VPICKOD_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VREPLVE_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk) { + Write32(EncodeVdVjK(Opcode32::VREPLVE_B, vd, vj, rk)); +} + +void LoongArch64Emitter::VREPLVE_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk) { + Write32(EncodeVdVjK(Opcode32::VREPLVE_H, vd, vj, rk)); +} + +void LoongArch64Emitter::VREPLVE_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk) { + Write32(EncodeVdVjK(Opcode32::VREPLVE_W, vd, vj, rk)); +} + +void LoongArch64Emitter::VREPLVE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk) { + Write32(EncodeVdVjK(Opcode32::VREPLVE_D, vd, vj, rk)); +} + +void LoongArch64Emitter::VAND_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VAND_V, vd, vj, vk)); +} + +void LoongArch64Emitter::VOR_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VOR_V, vd, vj, vk)); +} + +void LoongArch64Emitter::VXOR_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VXOR_V, vd, vj, vk)); +} + +void LoongArch64Emitter::VNOR_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VNOR_V, vd, vj, vk)); +} + +void LoongArch64Emitter::VANDN_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VANDN_V, vd, vj, vk)); +} + +void LoongArch64Emitter::VORN_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VORN_V, vd, vj, vk)); +} + +void LoongArch64Emitter::VFRSTP_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFRSTP_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VFRSTP_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFRSTP_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VADD_Q(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VADD_Q, vd, vj, vk)); +} + +void LoongArch64Emitter::VSUB_Q(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSUB_Q, vd, vj, vk)); +} + +void LoongArch64Emitter::VSIGNCOV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSIGNCOV_B, vd, vj, vk)); +} + +void LoongArch64Emitter::VSIGNCOV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSIGNCOV_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSIGNCOV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSIGNCOV_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSIGNCOV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSIGNCOV_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFADD_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFADD_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFADD_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFSUB_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFSUB_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFSUB_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFMUL_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFMUL_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFMUL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFMUL_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFDIV_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFDIV_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFDIV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFDIV_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFMAX_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFMAX_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFMAX_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFMAX_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFMIN_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFMIN_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFMIN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFMIN_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFMAXA_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFMAXA_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFMAXA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFMAXA_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFMINA_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFMINA_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFMINA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFMINA_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCVT_H_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCVT_H_S, vd, vj, vk)); +} + +void LoongArch64Emitter::VFCVT_S_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFCVT_S_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFFINT_S_L(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFFINT_S_L, vd, vj, vk)); +} + +void LoongArch64Emitter::VFTINT_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFTINT_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFTINTRM_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFTINTRM_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFTINTRP_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFTINTRP_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFTINTRZ_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFTINTRZ_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VFTINTRNE_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VFTINTRNE_W_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSHUF_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSHUF_H, vd, vj, vk)); +} + +void LoongArch64Emitter::VSHUF_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSHUF_W, vd, vj, vk)); +} + +void LoongArch64Emitter::VSHUF_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk) { + Write32(EncodeVdVjVk(Opcode32::VSHUF_D, vd, vj, vk)); +} + +void LoongArch64Emitter::VSEQI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSEQI_B, vd, vj, si5)); +} + +void LoongArch64Emitter::VSEQI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSEQI_H, vd, vj, si5)); +} + +void LoongArch64Emitter::VSEQI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSEQI_W, vd, vj, si5)); +} + +void LoongArch64Emitter::VSEQI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSEQI_D, vd, vj, si5)); +} + +void LoongArch64Emitter::VSLEI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSLEI_B, vd, vj, si5)); +} + +void LoongArch64Emitter::VSLEI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSLEI_H, vd, vj, si5)); +} + +void LoongArch64Emitter::VSLEI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSLEI_W, vd, vj, si5)); +} + +void LoongArch64Emitter::VSLEI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSLEI_D, vd, vj, si5)); +} + +void LoongArch64Emitter::VSLEI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSLEI_BU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSLEI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSLEI_HU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSLEI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSLEI_WU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSLEI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSLEI_DU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSLTI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSLTI_B, vd, vj, si5)); +} + +void LoongArch64Emitter::VSLTI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSLTI_H, vd, vj, si5)); +} + +void LoongArch64Emitter::VSLTI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSLTI_W, vd, vj, si5)); +} + +void LoongArch64Emitter::VSLTI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VSLTI_D, vd, vj, si5)); +} + +void LoongArch64Emitter::VSLTI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSLTI_BU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSLTI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSLTI_HU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSLTI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSLTI_WU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSLTI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSLTI_DU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VADDI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VADDI_BU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VADDI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VADDI_HU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VADDI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VADDI_WU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VADDI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VADDI_DU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSUBI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSUBI_BU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSUBI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSUBI_HU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSUBI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSUBI_WU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSUBI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSUBI_DU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VBSLL_V(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VBSLL_V, vd, vj, ui5)); +} + +void LoongArch64Emitter::VBSRL_V(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VBSRL_V, vd, vj, ui5)); +} + +void LoongArch64Emitter::VMAXI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VMAXI_B, vd, vj, si5)); +} + +void LoongArch64Emitter::VMAXI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VMAXI_H, vd, vj, si5)); +} + +void LoongArch64Emitter::VMAXI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VMAXI_W, vd, vj, si5)); +} + +void LoongArch64Emitter::VMAXI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VMAXI_D, vd, vj, si5)); +} + +void LoongArch64Emitter::VMINI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VMINI_B, vd, vj, si5)); +} + +void LoongArch64Emitter::VMINI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VMINI_H, vd, vj, si5)); +} + +void LoongArch64Emitter::VMINI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VMINI_W, vd, vj, si5)); +} + +void LoongArch64Emitter::VMINI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5) { + Write32(EncodeVdVjSk5(Opcode32::VMINI_D, vd, vj, si5)); +} + +void LoongArch64Emitter::VMAXI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VMAXI_BU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VMAXI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VMAXI_HU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VMAXI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VMAXI_WU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VMAXI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VMAXI_DU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VMINI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VMINI_BU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VMINI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VMINI_HU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VMINI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VMINI_WU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VMINI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VMINI_DU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VFRSTPI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VFRSTPI_B, vd, vj, ui5)); +} + +void LoongArch64Emitter::VFRSTPI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VFRSTPI_H, vd, vj, ui5)); +} + +void LoongArch64Emitter::VCLO_B(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VCLO_B, vd, vj)); +} + +void LoongArch64Emitter::VCLO_H(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VCLO_H, vd, vj)); +} + +void LoongArch64Emitter::VCLO_W(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VCLO_W, vd, vj)); +} + +void LoongArch64Emitter::VCLO_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VCLO_D, vd, vj)); +} + +void LoongArch64Emitter::VCLZ_B(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VCLZ_B, vd, vj)); +} + +void LoongArch64Emitter::VCLZ_H(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VCLZ_H, vd, vj)); +} + +void LoongArch64Emitter::VCLZ_W(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VCLZ_W, vd, vj)); +} + +void LoongArch64Emitter::VCLZ_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VCLZ_D, vd, vj)); +} + +void LoongArch64Emitter::VPCNT_B(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VPCNT_B, vd, vj)); +} + +void LoongArch64Emitter::VPCNT_H(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VPCNT_H, vd, vj)); +} + +void LoongArch64Emitter::VPCNT_W(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VPCNT_W, vd, vj)); +} + +void LoongArch64Emitter::VPCNT_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VPCNT_D, vd, vj)); +} + +void LoongArch64Emitter::VNEG_B(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VNEG_B, vd, vj)); +} + +void LoongArch64Emitter::VNEG_H(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VNEG_H, vd, vj)); +} + +void LoongArch64Emitter::VNEG_W(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VNEG_W, vd, vj)); +} + +void LoongArch64Emitter::VNEG_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VNEG_D, vd, vj)); +} + +void LoongArch64Emitter::VMSKLTZ_B(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VMSKLTZ_B, vd, vj)); +} + +void LoongArch64Emitter::VMSKLTZ_H(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VMSKLTZ_H, vd, vj)); +} + +void LoongArch64Emitter::VMSKLTZ_W(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VMSKLTZ_W, vd, vj)); +} + +void LoongArch64Emitter::VMSKLTZ_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VMSKLTZ_D, vd, vj)); +} + +void LoongArch64Emitter::VMSKGEZ_B(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VMSKGEZ_B, vd, vj)); +} + +void LoongArch64Emitter::VMSKNZ_B(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VMSKNZ_B, vd, vj)); +} + +void LoongArch64Emitter::VSETEQZ_V(LoongArch64CFR cd, LoongArch64Reg vj) { + Write32(EncodeCdVj(Opcode32::VSETEQZ_V, cd, vj)); +} + +void LoongArch64Emitter::VSETNEZ_V(LoongArch64CFR cd, LoongArch64Reg vj) { + Write32(EncodeCdVj(Opcode32::VSETNEZ_V, cd, vj)); +} + +void LoongArch64Emitter::VSETANYEQZ_B(LoongArch64CFR cd, LoongArch64Reg vj) { + Write32(EncodeCdVj(Opcode32::VSETANYEQZ_B, cd, vj)); +} + +void LoongArch64Emitter::VSETANYEQZ_H(LoongArch64CFR cd, LoongArch64Reg vj) { + Write32(EncodeCdVj(Opcode32::VSETANYEQZ_H, cd, vj)); +} + +void LoongArch64Emitter::VSETANYEQZ_W(LoongArch64CFR cd, LoongArch64Reg vj) { + Write32(EncodeCdVj(Opcode32::VSETANYEQZ_W, cd, vj)); +} + +void LoongArch64Emitter::VSETANYEQZ_D(LoongArch64CFR cd, LoongArch64Reg vj) { + Write32(EncodeCdVj(Opcode32::VSETANYEQZ_D, cd, vj)); +} + +void LoongArch64Emitter::VSETALLNEZ_B(LoongArch64CFR cd, LoongArch64Reg vj) { + Write32(EncodeCdVj(Opcode32::VSETALLNEZ_B, cd, vj)); +} + +void LoongArch64Emitter::VSETALLNEZ_H(LoongArch64CFR cd, LoongArch64Reg vj) { + Write32(EncodeCdVj(Opcode32::VSETALLNEZ_H, cd, vj)); +} + +void LoongArch64Emitter::VSETALLNEZ_W(LoongArch64CFR cd, LoongArch64Reg vj) { + Write32(EncodeCdVj(Opcode32::VSETALLNEZ_W, cd, vj)); +} + +void LoongArch64Emitter::VSETALLNEZ_D(LoongArch64CFR cd, LoongArch64Reg vj) { + Write32(EncodeCdVj(Opcode32::VSETALLNEZ_D, cd, vj)); +} + +void LoongArch64Emitter::VFLOGB_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFLOGB_S, vd, vj)); +} + +void LoongArch64Emitter::VFLOGB_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFLOGB_D, vd, vj)); +} + +void LoongArch64Emitter::VFCLASS_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFCLASS_S, vd, vj)); +} + +void LoongArch64Emitter::VFCLASS_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFCLASS_D, vd, vj)); +} + +void LoongArch64Emitter::VFSQRT_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFSQRT_S, vd, vj)); +} + +void LoongArch64Emitter::VFSQRT_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFSQRT_D, vd, vj)); +} + +void LoongArch64Emitter::VFRECIP_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRECIP_S, vd, vj)); +} + +void LoongArch64Emitter::VFRECIP_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRECIP_D, vd, vj)); +} + +void LoongArch64Emitter::VFRSQRT_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRSQRT_S, vd, vj)); +} + +void LoongArch64Emitter::VFRSQRT_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRSQRT_D, vd, vj)); +} + +void LoongArch64Emitter::VFRECIPE_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRECIPE_S, vd, vj)); +} + +void LoongArch64Emitter::VFRECIPE_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRECIPE_D, vd, vj)); +} + +void LoongArch64Emitter::VFRSQRTE_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRSQRTE_S, vd, vj)); +} + +void LoongArch64Emitter::VFRSQRTE_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRSQRTE_D, vd, vj)); +} + +void LoongArch64Emitter::VFRINT_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRINT_S, vd, vj)); +} + +void LoongArch64Emitter::VFRINT_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRINT_D, vd, vj)); +} + +void LoongArch64Emitter::VFRINTRM_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRINTRM_S, vd, vj)); +} + +void LoongArch64Emitter::VFRINTRM_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRINTRM_D, vd, vj)); +} + +void LoongArch64Emitter::VFRINTRP_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRINTRP_S, vd, vj)); +} + +void LoongArch64Emitter::VFRINTRP_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRINTRP_D, vd, vj)); +} + +void LoongArch64Emitter::VFRINTRZ_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRINTRZ_S, vd, vj)); +} + +void LoongArch64Emitter::VFRINTRZ_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRINTRZ_D, vd, vj)); +} + +void LoongArch64Emitter::VFRINTRNE_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRINTRNE_S, vd, vj)); +} + +void LoongArch64Emitter::VFRINTRNE_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFRINTRNE_D, vd, vj)); +} + +void LoongArch64Emitter::VFCVTL_S_H(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFCVTL_S_H, vd, vj)); +} + +void LoongArch64Emitter::VFCVTH_S_H(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFCVTH_S_H, vd, vj)); +} + +void LoongArch64Emitter::VFCVTL_D_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFCVTL_D_S, vd, vj)); +} + +void LoongArch64Emitter::VFCVTH_D_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFCVTH_D_S, vd, vj)); +} + +void LoongArch64Emitter::VFFINT_S_W(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFFINT_S_W, vd, vj)); +} + +void LoongArch64Emitter::VFFINT_S_WU(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFFINT_S_WU, vd, vj)); +} + +void LoongArch64Emitter::VFFINT_D_L(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFFINT_D_L, vd, vj)); +} + +void LoongArch64Emitter::VFFINT_D_LU(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFFINT_D_LU, vd, vj)); +} + +void LoongArch64Emitter::VFFINTL_D_W(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFFINTL_D_W, vd, vj)); +} + +void LoongArch64Emitter::VFFINTH_D_W(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFFINTH_D_W, vd, vj)); +} + +void LoongArch64Emitter::VFTINT_W_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINT_W_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINT_L_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINT_L_D, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRM_W_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRM_W_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRM_L_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRM_L_D, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRP_W_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRP_W_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRP_L_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRP_L_D, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRZ_W_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRZ_W_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRZ_L_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRZ_L_D, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRNE_W_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRNE_W_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRNE_L_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRNE_L_D, vd, vj)); +} + +void LoongArch64Emitter::VFTINT_WU_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINT_WU_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINT_LU_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINT_LU_D, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRZ_WU_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRZ_WU_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRZ_LU_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRZ_LU_D, vd, vj)); +} + +void LoongArch64Emitter::VFTINTL_L_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTL_L_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTH_L_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTH_L_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRML_L_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRML_L_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRMH_L_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRMH_L_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRPL_L_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRPL_L_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRPH_L_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRPH_L_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRZL_L_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRZL_L_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRZH_L_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRZH_L_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRNEL_L_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRNEL_L_S, vd, vj)); +} + +void LoongArch64Emitter::VFTINTRNEH_L_S(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VFTINTRNEH_L_S, vd, vj)); +} + +void LoongArch64Emitter::VEXTH_H_B(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VEXTH_H_B, vd, vj)); +} + +void LoongArch64Emitter::VEXTH_W_H(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VEXTH_W_H, vd, vj)); +} + +void LoongArch64Emitter::VEXTH_D_W(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VEXTH_D_W, vd, vj)); +} + +void LoongArch64Emitter::VEXTH_Q_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VEXTH_Q_D, vd, vj)); +} + +void LoongArch64Emitter::VEXTH_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VEXTH_HU_BU, vd, vj)); +} + +void LoongArch64Emitter::VEXTH_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VEXTH_WU_HU, vd, vj)); +} + +void LoongArch64Emitter::VEXTH_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VEXTH_DU_WU, vd, vj)); +} + +void LoongArch64Emitter::VEXTH_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VEXTH_QU_DU, vd, vj)); +} + +void LoongArch64Emitter::VREPLGR2VR_B(LoongArch64Reg vd, LoongArch64Reg rj) { + Write32(EncodeVdJ(Opcode32::VREPLGR2VR_B, vd, rj)); +} + +void LoongArch64Emitter::VREPLGR2VR_H(LoongArch64Reg vd, LoongArch64Reg rj) { + Write32(EncodeVdJ(Opcode32::VREPLGR2VR_H, vd, rj)); +} + +void LoongArch64Emitter::VREPLGR2VR_W(LoongArch64Reg vd, LoongArch64Reg rj) { + Write32(EncodeVdJ(Opcode32::VREPLGR2VR_W, vd, rj)); +} + +void LoongArch64Emitter::VREPLGR2VR_D(LoongArch64Reg vd, LoongArch64Reg rj) { + Write32(EncodeVdJ(Opcode32::VREPLGR2VR_D, vd, rj)); +} + +void LoongArch64Emitter::VROTRI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VROTRI_B, vd, vj, ui3)); +} + +void LoongArch64Emitter::VROTRI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VROTRI_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VROTRI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VROTRI_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VROTRI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VROTRI_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSRLRI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VSRLRI_B, vd, vj, ui3)); +} + +void LoongArch64Emitter::VSRLRI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSRLRI_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSRLRI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSRLRI_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSRLRI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSRLRI_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSRARI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VSRARI_B, vd, vj, ui3)); +} + +void LoongArch64Emitter::VSRARI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSRARI_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSRARI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSRARI_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSRARI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSRARI_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VINSGR2VR_B(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui4) { + Write32(EncodeVdJUk4(Opcode32::VINSGR2VR_B, vd, rj, ui4)); +} + +void LoongArch64Emitter::VINSGR2VR_H(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui3) { + Write32(EncodeVdJUk3(Opcode32::VINSGR2VR_H, vd, rj, ui3)); +} + +void LoongArch64Emitter::VINSGR2VR_W(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui2) { + Write32(EncodeVdJUk2(Opcode32::VINSGR2VR_W, vd, rj, ui2)); +} + +void LoongArch64Emitter::VINSGR2VR_D(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui1) { + Write32(EncodeVdJUk1(Opcode32::VINSGR2VR_D, vd, rj, ui1)); +} + +void LoongArch64Emitter::VPICKVE2GR_B(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeDVjUk4(Opcode32::VPICKVE2GR_B, rd, vj, ui4)); +} + +void LoongArch64Emitter::VPICKVE2GR_H(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeDVjUk3(Opcode32::VPICKVE2GR_H, rd, vj, ui3)); +} + +void LoongArch64Emitter::VPICKVE2GR_W(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui2) { + Write32(EncodeDVjUk2(Opcode32::VPICKVE2GR_W, rd, vj, ui2)); +} + +void LoongArch64Emitter::VPICKVE2GR_D(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui1) { + Write32(EncodeDVjUk1(Opcode32::VPICKVE2GR_D, rd, vj, ui1)); +} + +void LoongArch64Emitter::VPICKVE2GR_BU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeDVjUk4(Opcode32::VPICKVE2GR_BU, rd, vj, ui4)); +} + +void LoongArch64Emitter::VPICKVE2GR_HU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeDVjUk3(Opcode32::VPICKVE2GR_HU, rd, vj, ui3)); +} + +void LoongArch64Emitter::VPICKVE2GR_WU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui2) { + Write32(EncodeDVjUk2(Opcode32::VPICKVE2GR_WU, rd, vj, ui2)); +} + +void LoongArch64Emitter::VPICKVE2GR_DU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui1) { + Write32(EncodeDVjUk1(Opcode32::VPICKVE2GR_DU, rd, vj, ui1)); +} + +void LoongArch64Emitter::VREPLVEI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VREPLVEI_B, vd, vj, ui4)); +} + +void LoongArch64Emitter::VREPLVEI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VREPLVEI_H, vd, vj, ui3)); +} + +void LoongArch64Emitter::VREPLVEI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui2) { + Write32(EncodeVdVjUk2(Opcode32::VREPLVEI_W, vd, vj, ui2)); +} + +void LoongArch64Emitter::VREPLVEI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui1) { + Write32(EncodeVdVjUk1(Opcode32::VREPLVEI_D, vd, vj, ui1)); +} + +void LoongArch64Emitter::VSLLWIL_H_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VSLLWIL_H_B, vd, vj, ui3)); +} + +void LoongArch64Emitter::VSLLWIL_W_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSLLWIL_W_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSLLWIL_D_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSLLWIL_D_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VEXTL_Q_D(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VEXTL_Q_D, vd, vj)); +} + +void LoongArch64Emitter::VSLLWIL_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VSLLWIL_HU_BU, vd, vj, ui3)); +} + +void LoongArch64Emitter::VSLLWIL_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSLLWIL_WU_HU, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSLLWIL_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSLLWIL_DU_WU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VEXTL_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj) { + Write32(EncodeVdVj(Opcode32::VEXTL_QU_DU, vd, vj)); +} + +void LoongArch64Emitter::VBITCLRI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VBITCLRI_B, vd, vj, ui3)); +} + +void LoongArch64Emitter::VBITCLRI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VBITCLRI_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VBITCLRI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VBITCLRI_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VBITCLRI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VBITCLRI_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VBITSETI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VBITSETI_B, vd, vj, ui3)); +} + +void LoongArch64Emitter::VBITSETI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VBITSETI_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VBITSETI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VBITSETI_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VBITSETI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VBITSETI_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VBITREVI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VBITREVI_B, vd, vj, ui3)); +} + +void LoongArch64Emitter::VBITREVI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VBITREVI_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VBITREVI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VBITREVI_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VBITREVI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VBITREVI_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSAT_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VSAT_B, vd, vj, ui3)); +} + +void LoongArch64Emitter::VSAT_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSAT_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSAT_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSAT_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSAT_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSAT_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSAT_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VSAT_BU, vd, vj, ui3)); +} + +void LoongArch64Emitter::VSAT_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSAT_HU, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSAT_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSAT_WU, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSAT_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSAT_DU, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSLLI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VSLLI_B, vd, vj, ui3)); +} + +void LoongArch64Emitter::VSLLI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSLLI_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSLLI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSLLI_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSLLI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSLLI_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSRLI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VSRLI_B, vd, vj, ui3)); +} + +void LoongArch64Emitter::VSRLI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSRLI_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSRLI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSRLI_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSRLI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSRLI_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSRAI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3) { + Write32(EncodeVdVjUk3(Opcode32::VSRAI_B, vd, vj, ui3)); +} + +void LoongArch64Emitter::VSRAI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSRAI_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSRAI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSRAI_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSRAI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSRAI_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSRLNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSRLNI_B_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSRLNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSRLNI_H_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSRLNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSRLNI_W_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSRLNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSRLNI_D_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VSRLRNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSRLRNI_B_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSRLRNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSRLRNI_H_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSRLRNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSRLRNI_W_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSRLRNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSRLRNI_D_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VSSRLNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSSRLNI_B_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSSRLNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSSRLNI_H_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSSRLNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSSRLNI_W_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSSRLNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSSRLNI_D_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VSSRLNI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSSRLNI_BU_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSSRLNI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSSRLNI_HU_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSSRLNI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSSRLNI_WU_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSSRLNI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSSRLNI_DU_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VSSRLRNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSSRLRNI_B_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSSRLRNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSSRLRNI_H_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSSRLRNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSSRLRNI_W_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSSRLRNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSSRLRNI_D_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VSSRLRNI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSSRLRNI_BU_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSSRLRNI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSSRLRNI_HU_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSSRLRNI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSSRLRNI_WU_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSSRLRNI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSSRLRNI_DU_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VSRANI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSRANI_B_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSRANI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSRANI_H_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSRANI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSRANI_W_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSRANI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSRANI_D_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VSRARNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSRARNI_B_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSRARNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSRARNI_H_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSRARNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSRARNI_W_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSRARNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSRARNI_D_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VSSRANI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSSRANI_B_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSSRANI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSSRANI_H_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSSRANI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSSRANI_W_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSSRANI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSSRANI_D_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VSSRANI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSSRANI_BU_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSSRANI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSSRANI_HU_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSSRANI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSSRANI_WU_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSSRANI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSSRANI_DU_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VSSRARNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSSRARNI_B_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSSRARNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSSRARNI_H_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSSRARNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSSRARNI_W_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSSRARNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSSRARNI_D_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VSSRARNI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4) { + Write32(EncodeVdVjUk4(Opcode32::VSSRARNI_BU_H, vd, vj, ui4)); +} + +void LoongArch64Emitter::VSSRARNI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5) { + Write32(EncodeVdVjUk5(Opcode32::VSSRARNI_HU_W, vd, vj, ui5)); +} + +void LoongArch64Emitter::VSSRARNI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6) { + Write32(EncodeVdVjUk6(Opcode32::VSSRARNI_WU_D, vd, vj, ui6)); +} + +void LoongArch64Emitter::VSSRARNI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7) { + Write32(EncodeVdVjUk7(Opcode32::VSSRARNI_DU_Q, vd, vj, ui7)); +} + +void LoongArch64Emitter::VEXTRINS_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VEXTRINS_D, vd, vj, ui8)); +} + +void LoongArch64Emitter::VEXTRINS_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VEXTRINS_W, vd, vj, ui8)); +} + +void LoongArch64Emitter::VEXTRINS_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VEXTRINS_H, vd, vj, ui8)); +} + +void LoongArch64Emitter::VEXTRINS_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VEXTRINS_B, vd, vj, ui8)); +} + +void LoongArch64Emitter::VSHUF4I_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VSHUF4I_B, vd, vj, ui8)); +} + +void LoongArch64Emitter::VSHUF4I_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VSHUF4I_H, vd, vj, ui8)); +} + +void LoongArch64Emitter::VSHUF4I_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VSHUF4I_W, vd, vj, ui8)); +} + +void LoongArch64Emitter::VSHUF4I_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VSHUF4I_D, vd, vj, ui8)); +} + +void LoongArch64Emitter::VBITSELI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VBITSELI_B, vd, vj, ui8)); +} + +void LoongArch64Emitter::VANDI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VANDI_B, vd, vj, ui8)); +} + +void LoongArch64Emitter::VORI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VORI_B, vd, vj, ui8)); +} + +void LoongArch64Emitter::VXORI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VXORI_B, vd, vj, ui8)); +} + +void LoongArch64Emitter::VNORI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VNORI_B, vd, vj, ui8)); +} + +void LoongArch64Emitter::VLDI(LoongArch64Reg vd, s16 i13) { + Write32(EncodeVdSj13(Opcode32::VLDI, vd, i13)); +} + +void LoongArch64Emitter::VPERMI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8) { + Write32(EncodeVdVjUk8(Opcode32::VPERMI_W, vd, vj, ui8)); +} + +void LoongArch64CodeBlock::PoisonMemory(int offset) { + // So we can adjust region to writable space. Might be zero. + ptrdiff_t writable = writable_ - code_; + + u32 *ptr = (u32 *)(region + offset + writable); + u32 *maxptr = (u32 *)(region + region_size - offset + writable); + // If our memory isn't a multiple of u32 then this won't write the last remaining bytes with anything + // Less than optimal, but there would be nothing we could do but throw a runtime warning anyway. + // LoongArch64: 0x002a0000 = BREAK 0 + while (ptr < maxptr) + *ptr++ = 0x002a0000; +} + +}; \ No newline at end of file diff --git a/Common/LoongArch64Emitter.h b/Common/LoongArch64Emitter.h new file mode 100644 index 0000000000..9464ea9e59 --- /dev/null +++ b/Common/LoongArch64Emitter.h @@ -0,0 +1,1398 @@ +// Copyright (c) 2025- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#pragma once + +#include +#include +#include +#include "Common/CodeBlock.h" +#include "Common/Common.h" + +namespace LoongArch64Gen { + +enum LoongArch64Reg { + // General-purpose Registers (64-bit) + // https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_general_purpose_registers + R0 = 0, R1, R2, R3, R4, R5, R6, R7, + R8, R9, R10, R11, R12, R13, R14, R15, + R16, R17, R18, R19, R20, R21, R22, R23, + R24, R25, R26, R27, R28, R29, R30, R31, + + R_ZERO = 0, + R_RA = 1, + R_SP = 3, + + // Floating-point Registers (64-bit) + // https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#floating-point-registers + F0 = 0x20, F1, F2, F3, F4, F5, F6, F7, + F8, F9, F10, F11, F12, F13, F14, F15, + F16, F17, F18, F19, F20, F21, F22, F23, + F24, F25, F26, F27, F28, F29, F30, F31, + + // FP register f0 and LSX register v0 and LASX register x0 share the lowest 64 bits + // LSX register v0 and LASX register x0 share the lowest 128 bits + // https://jia.je/unofficial-loongarch-intrinsics-guide/ + + // LSX Registers (128-bit) + V0 = 0x40, V1, V2, V3, V4, V5, V6, V7, + V8, V9, V10, V11, V12, V13, V14, V15, + V16, V17, V18, V19, V20, V21, V22, V23, + V24, V25, V26, V27, V28, V29, V30, V31, + + // LASX Registers + X0 = 0x60, X1, X2, X3, X4, X5, X6, X7, + X8, X9, X10, X11, X12, X13, X14, X15, + X16, X17, X18, X19, X20, X21, X22, X23, + X24, X25, X26, X27, X28, X29, X30, X31, + + INVALID_REG = 0xFFFFFFFF, +}; + +enum LoongArch64CFR { + // Condition Flag Register + // The length of CFR is 1 bit. + FCC0 = 0, FCC1, FCC2, FCC3, FCC4, FCC5, FCC6, FCC7, +}; + +enum LoongArch64FCSR { + // Floating-point Control and Status Register + // The length of FCSR0 is 29 bits. + // FCSR1-FCSR3 are aliases of some fields in fcsr0. + FCSR0 = 0, FCSR1, FCSR2, FCSR3, +}; + +enum class FixupBranchType { + B, + J, + BZ, +}; + +enum class LoongArch64Fcond { + // Conditions used in FCMP instruction + CAF = 0x0, + CUN = 0x8, + CEQ = 0x4, + CUEQ = 0xC, + CLT = 0x2, + CULT = 0xA, + CLE = 0x6, + CULE = 0xE, + CNE = 0x10, + COR = 0x14, + CUNE = 0x18, + SAF = 0x1, + SUN = 0x9, + SEQ = 0x5, + SUEQ = 0xD, + SLT = 0x3, + SULT = 0xB, + SLE = 0x7, + SULE = 0xF, + SNE = 0x11, + SOR = 0x15, + SUNE = 0x19, +}; + +static inline LoongArch64Reg DecodeReg(LoongArch64Reg reg) { return (LoongArch64Reg)(reg & 0x1F); } +static inline bool IsGPR(LoongArch64Reg reg) { return (reg & ~0x1F) == 0; } +static inline bool IsFPR(LoongArch64Reg reg) { return (reg & ~0x1F) == 0x20; } +static inline bool IsVPR(LoongArch64Reg reg) { return (reg & ~0x1F) == 0x40; } +static inline bool IsXPR(LoongArch64Reg reg) { return (reg & ~0x1F) == 0x60; } +static inline bool IsCFR(LoongArch64CFR cfr) { return (cfr < 8); } +static inline bool IsFCSR(LoongArch64FCSR fcsr) { return (fcsr < 4); } +inline LoongArch64Reg EncodeRegToV(LoongArch64Reg reg) { return (LoongArch64Reg)(DecodeReg(reg) + V0); } + +struct FixupBranch { + FixupBranch() {} + FixupBranch(const u8 *p, FixupBranchType t) : ptr(p), type(t) {} + FixupBranch(FixupBranch &&other); + FixupBranch(const FixupBranch &) = delete; + ~FixupBranch(); + + FixupBranch &operator =(FixupBranch &&other); + FixupBranch &operator =(const FixupBranch &other) = delete; + + // Pointer to executable code address. + const u8 *ptr = nullptr; + FixupBranchType type = FixupBranchType::B; +}; + +class LoongArch64Emitter { +public: + LoongArch64Emitter() {} + LoongArch64Emitter(const u8 *codePtr, u8 *writablePtr); + virtual ~LoongArch64Emitter() {} + + void SetCodePointer(const u8 *ptr, u8 *writePtr); + const u8 *GetCodePointer() const; + u8 *GetWritableCodePtr(); + + void ReserveCodeSpace(u32 bytes); + const u8 *AlignCode16(); + const u8 *AlignCodePage(); + void FlushIcache(); + void FlushIcacheSection(const u8 *start, const u8 *end); + + void SetJumpTarget(FixupBranch &branch); + bool BranchInRange(const void *func) const; + bool JumpInRange(const void *func) const; + bool BranchZeroInRange(const void *func) const; + + void QuickJump(LoongArch64Reg scratchreg, LoongArch64Reg rd, const u8 *dst); + void QuickJ(LoongArch64Reg scratchreg, const u8 *dst) { + QuickJump(scratchreg, R_ZERO, dst); + } + void QuickCallFunction(const u8 *func, LoongArch64Reg scratchreg = R_RA) { + QuickJump(scratchreg, R_RA, func); + } + template + void QuickCallFunction(T *func, LoongArch64Reg scratchreg = R_RA) { + static_assert(std::is_function::value, "QuickCallFunction without function"); + QuickCallFunction((const u8 *)func, scratchreg); + } + + // https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html + // https://github.com/loongson-community/loongarch-opcodes/ + + // Basic Integer Instructions + + // Arithmetic Operation Instructions + void ADD_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void ADD_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void SUB_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void SUB_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + + void ADDI_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void ADDI_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void ADDU16I_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si16); // DJSk16 + + void ALSL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2); // DJKUa2pp1 + void ALSL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2); // DJKUa2pp1 + void ALSL_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2); // DJKUa2pp1 + + void LU12I_W(LoongArch64Reg rd, s32 si20); // DSj20 + void LU32I_D(LoongArch64Reg rd, s32 si20); // DSj20 + void LU52I_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + + void SLT(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void SLTU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + + void SLTI(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void SLTUI(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + + void PCADDI(LoongArch64Reg rd, s32 si20); // DSj20 + void PCADDU12I(LoongArch64Reg rd, s32 si20); // DSj20 + void PCADDU18I(LoongArch64Reg rd, s32 si20); // DSj20 + void PCALAU12I(LoongArch64Reg rd, s32 si20); // DSj20 + + void AND(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void OR(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void NOR(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void XOR(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void ANDN(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void ORN(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + + void ANDI(LoongArch64Reg rd, LoongArch64Reg rj, u16 ui12); // DJUk12 + void ORI(LoongArch64Reg rd, LoongArch64Reg rj, u16 ui12); // DJUk12 + void XORI(LoongArch64Reg rd, LoongArch64Reg rj, u16 ui12); // DJUk12 + + void NOP() { + ANDI(R_ZERO, R_ZERO, 0); + } + void MOVE(LoongArch64Reg rd, LoongArch64Reg rj) { + OR(rd, rj, R_ZERO); + } + + template + void LI(LoongArch64Reg rd, const T &v) { + _assert_msg_(rd != R_ZERO, "LI to X0"); + _assert_msg_(rd < F0, "LI to non-GPR"); + + uint64_t value = AsImmediate::value>(v); + SetRegToImmediate(rd, value); + } + + void MUL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void MULH_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void MULH_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void MUL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void MULH_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void MULH_DU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + + void MULW_D_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void MULW_D_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + + void DIV_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void MOD_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void DIV_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void MOD_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void DIV_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void MOD_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void DIV_DU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void MOD_DU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + + // Bit-shift Instructions + void SLL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void SRL_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void SRA_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void ROTR_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + + void SLLI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5); // DJUk5 + void SRLI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5); // DJUk5 + void SRAI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5); // DJUk5 + void ROTRI_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui5); // DJUk5 + + void SLL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void SRL_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void SRA_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void ROTR_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + + void SLLI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6); // DJUk6 + void SRLI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6); // DJUk6 + void SRAI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6); // DJUk6 + void ROTRI_D(LoongArch64Reg rd, LoongArch64Reg rj, u8 ui6); // DJUk6 + + // Bit-manipulation Instructions + void EXT_W_B(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void EXT_W_H(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + + void CLO_W(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void CLO_D(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void CLZ_W(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void CLZ_D(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void CTO_W(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void CTO_D(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void CTZ_W(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void CTZ_D(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + + void BYTEPICK_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa2); // DJKUa2 + void BYTEPICK_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk, u8 sa3); // DJKUa3 + + void REVB_2H(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void REVB_4H(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void REVB_2W(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void REVB_D(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + + void BITREV_4B(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void BITREV_8B(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + + void BITREV_W(LoongArch64Reg rd, LoongArch64Reg rj); //DJ + void BITREV_D(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + + void BSTRINS_W(LoongArch64Reg rd, LoongArch64Reg rj, u8 msbw, u8 lsbw); // DJUk5Um5 + void BSTRINS_D(LoongArch64Reg RD, LoongArch64Reg RJ, u8 msbd, u8 lsbd); // DJUk6Um6 + + void BSTRPICK_W(LoongArch64Reg RD, LoongArch64Reg RJ, u8 msbd, u8 lsbd); // DJUk5Um5 + void BSTRPICK_D(LoongArch64Reg RD, LoongArch64Reg RJ, u8 msbd, u8 lsbd); // DJUk6Um6 + + void MASKEQZ(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void MASKNEZ(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + + // Branch Instructions + void BEQ(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst); // JDSk16ps2 + void BNE(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst); // JDSk16ps2 + void BLT(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst); // JDSk16ps2 + void BGE(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst); // JDSk16ps2 + void BLTU(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst); // JDSk16ps2 + void BGEU(LoongArch64Reg rj, LoongArch64Reg rd, const void *dst); // JDSk16ps2 + FixupBranch BEQ(LoongArch64Reg rj, LoongArch64Reg rd); + FixupBranch BNE(LoongArch64Reg rj, LoongArch64Reg rd); + FixupBranch BLT(LoongArch64Reg rj, LoongArch64Reg rd); + FixupBranch BGE(LoongArch64Reg rj, LoongArch64Reg rd); + FixupBranch BLTU(LoongArch64Reg rj, LoongArch64Reg rd); + FixupBranch BGEU(LoongArch64Reg rj, LoongArch64Reg rd); + + void BEQZ(LoongArch64Reg rj, const void *dst); // JSd5k16ps2 + void BNEZ(LoongArch64Reg rj, const void *dst); // JSd5k16ps2 + FixupBranch BEQZ(LoongArch64Reg rj); + FixupBranch BNEZ(LoongArch64Reg rj); + + void B(const void *dst); // Sd10k16ps2 + void BL(const void *dst); // Sd10k16ps2 + FixupBranch B(); + FixupBranch BL(); + + void JIRL(LoongArch64Reg rd, LoongArch64Reg rj, s32 offs16); // DJSk16ps2 + + void JR(LoongArch64Reg rj) { + JIRL(R_ZERO, rj, 0); + } + void RET() { + JIRL(R_ZERO, R_RA, 0); + } + + // Common Memory Access Instructions + void LD_B(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void LD_H(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void LD_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void LD_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void LD_BU(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void LD_HU(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void LD_WU(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void ST_B(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void ST_H(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void ST_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + void ST_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si12); // DJSk12 + + void LDX_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDX_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDX_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDX_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDX_BU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDX_HU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDX_WU(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STX_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STX_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STX_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STX_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + + void LDPTR_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14); // DJSk14ps2 + void LDPTR_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14); // DJSk14ps2 + void STPTR_W(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14); // DJSk14ps2 + void STPTR_D(LoongArch64Reg rd, LoongArch64Reg rj, s16 si14); // DJSk14ps2 + + void PRELD(u32 hint, LoongArch64Reg rj, s16 si12); // Ud5JSk12 + void PRELDX(u32 hint, LoongArch64Reg rj, LoongArch64Reg rk); // Ud5JK + + // Bound Check Memory Access Instructions + void LDGT_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDGT_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDGT_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDGT_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDLE_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDLE_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDLE_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void LDLE_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STGT_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STGT_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STGT_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STGT_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STLE_B(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STLE_H(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STLE_W(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + void STLE_D(LoongArch64Reg rd, LoongArch64Reg rj, LoongArch64Reg rk); // DJK + + // Atomic Memory Access Instructions + void AMSWAP_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMSWAP_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMSWAP_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMSWAP_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + void AMADD_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMADD_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMADD_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMADD_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + void AMAND_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMAND_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMAND_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMAND_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + void AMOR_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMOR_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMOR_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMOR_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + void AMXOR_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMXOR_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMXOR_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMXOR_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + void AMMAX_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMAX_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMAX_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMAX_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + void AMMIN_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMIN_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMIN_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMIN_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + void AMMAX_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMAX_DB_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMAX_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMAX_DB_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + void AMMIN_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMIN_DB_WU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMIN_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMMIN_DB_DU(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + void AMSWAP_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMSWAP_DB_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMSWAP_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMSWAP_DB_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + void AMADD_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMADD_DB_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMADD_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMADD_DB_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + void AMCAS_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMCAS_DB_B(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMCAS_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMCAS_DB_H(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMCAS_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMCAS_DB_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMCAS_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void AMCAS_DB_D(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + // CRC Check Instructions + void CRC_W_B_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void CRC_W_H_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void CRC_W_W_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void CRC_W_D_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void CRCC_W_B_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void CRCC_W_H_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void CRCC_W_W_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + void CRCC_W_D_W(LoongArch64Reg rd, LoongArch64Reg rk, LoongArch64Reg rj); // DKJ + + // Other Miscellaneous Instructions + void SYSCALL(u16 code); // Ud15 + void BREAK(u16 code); // Ud15 + + void ASRTLE_D(LoongArch64Reg rj, LoongArch64Reg rk); // JK + void ASRTGT_D(LoongArch64Reg rj, LoongArch64Reg rk); // JK + + void RDTIMEL_W(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void RDTIMEH_W(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + void RDTIME_D(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + + void CPUCFG(LoongArch64Reg rd, LoongArch64Reg rj); // DJ + + // Basic Floating-Point Instructions + // Floating-Point Arithmetic Operation Instructions + void FADD_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FADD_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FSUB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FSUB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FMUL_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FMUL_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FDIV_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FDIV_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + + void FMADD_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa); // FdFjFkFa + void FMADD_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa); // FdFjFkFa + void FMSUB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa); // FdFjFkFa + void FMSUB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa); // FdFjFkFa + void FNMADD_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa); // FdFjFkFa + void FNMADD_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa); // FdFjFkFa + void FNMSUB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa); // FdFjFkFa + void FNMSUB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Reg fa); // FdFjFkFa + + void FMAX_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FMAX_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FMIN_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FMIN_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + + void FMAXA_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FMAXA_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FMINA_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FMINA_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + + void FABS_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FABS_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FNEG_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FNEG_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + + void FSQRT_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FSQRT_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FRECIP_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FRECIP_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FRSQRT_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FRSQRT_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + + void FSCALEB_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FSCALEB_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FLOGB_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FLOGB_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FCOPYSIGN_S(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + void FCOPYSIGN_D(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk); // FdFjFk + + void FCLASS_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FCLASS_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + + void FRECIPE_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FRECIPE_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FRSQRTE_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FRSQRTE_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + + void FCMP_COND_S(LoongArch64CFR cd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Fcond cond); // CdFjFkFcond + void FCMP_COND_D(LoongArch64CFR cd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64Fcond cond); // CdFjFkFcond + + // Floating-Point Conversion Instructions + void FCVT_S_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FCVT_D_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + + void FFINT_S_W(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FFINT_S_L(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FFINT_D_W(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FFINT_D_L(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINT_W_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINT_W_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINT_L_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINT_L_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + + void FTINTRM_W_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRM_W_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRM_L_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRM_L_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRP_W_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRP_W_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRP_L_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRP_L_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRZ_W_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRZ_W_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRZ_L_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRZ_L_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRNE_W_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRNE_W_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRNE_L_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FTINTRNE_L_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + + void FRINT_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FRINT_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + + // Floating-Point Move Instructions + void FMOV_S(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + void FMOV_D(LoongArch64Reg fd, LoongArch64Reg fj); // FdFj + + void FSEL(LoongArch64Reg fd, LoongArch64Reg fj, LoongArch64Reg fk, LoongArch64CFR ca); // FdFjFkCa + + void MOVGR2FR_W(LoongArch64Reg fd, LoongArch64Reg rj); // FdJ + void MOVGR2FR_D(LoongArch64Reg fd, LoongArch64Reg rj); // FdJ + void MOVGR2FRH_W(LoongArch64Reg fd, LoongArch64Reg rj); // FdJ + + void MOVFR2GR_S(LoongArch64Reg fd, LoongArch64Reg rj); // DFj + void MOVFR2GR_D(LoongArch64Reg fd, LoongArch64Reg rj); // DFj + void MOVFRH2GR_S(LoongArch64Reg fd, LoongArch64Reg rj); // DFj + + void MOVGR2FCSR(LoongArch64FCSR fcsr, LoongArch64Reg rj); // JUd5 + void MOVFCSR2GR(LoongArch64Reg rd, LoongArch64FCSR fcsr); // DUj5 + + void MOVFR2CF(LoongArch64CFR cd, LoongArch64Reg fj); // CdFj + void MOVCF2FR(LoongArch64Reg fd, LoongArch64CFR cj); // FdCj + + void MOVGR2CF(LoongArch64CFR cd, LoongArch64Reg rj); // CdJ + void MOVCF2GR(LoongArch64Reg rd, LoongArch64CFR cj); // DCj + + // Floating-Point Branch Instructions + void BCEQZ(LoongArch64CFR cj, s32 offs21); // CjSd5k16ps2 + void BCNEZ(LoongArch64CFR cj, s32 offs21); // CjSd5k16ps2 + + // Floating-Point Common Memory Access Instructions + void FLD_S(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12); // FdJSk12 + void FLD_D(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12); // FdJSk12 + void FST_S(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12); // FdJSk12 + void FST_D(LoongArch64Reg fd, LoongArch64Reg rj, s16 si12); // FdJSk12 + + void FLDX_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + void FLDX_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + void FSTX_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + void FSTX_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + + // Floating-Point Bound Check Memory Access Instructions + void FLDGT_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + void FLDGT_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + void FLDLE_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + void FLDLE_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + void FSTGT_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + void FSTGT_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + void FSTLE_S(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + void FSTLE_D(LoongArch64Reg fd, LoongArch64Reg rj, LoongArch64Reg rk); // FdJK + + void QuickFLI(int bits, LoongArch64Reg fd, double v, LoongArch64Reg scratchReg); + void QuickFLI(int bits, LoongArch64Reg fd, uint32_t pattern, LoongArch64Reg scratchReg); + void QuickFLI(int bits, LoongArch64Reg fd, float v, LoongArch64Reg scratchReg); + + // LoongArch SX 128-bit SIMD instructions + void VFMADD_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va); // VdVjVkVa + void VFMADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va); // VdVjVkVa + void VFMSUB_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va); // VdVjVkVa + void VFMSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va); // VdVjVkVa + void VFNMADD_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va); // VdVjVkVa + void VFNMADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va); // VdVjVkVa + void VFNMSUB_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va); // VdVjVkVa + void VFNMSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va); // VdVjVkVa + void VFCMP_CAF_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SAF_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CLT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SLT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CLE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SLE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CUN_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SUN_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CULT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SULT_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CUEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SUEQ_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CULE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SULE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_COR_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SOR_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CUNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SUNE_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CAF_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SAF_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CLT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SLT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CLE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SLE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CUN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SUN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CULT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SULT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CUEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SUEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CULE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SULE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_COR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SOR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_CUNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCMP_SUNE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITSEL_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va); // VdVjVkVa + void VSHUF_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk, LoongArch64Reg va); // VdVjVkVa + void VLD(LoongArch64Reg vd, LoongArch64Reg rj, s16 si12); // VdJSk12 + void VST(LoongArch64Reg vd, LoongArch64Reg rj, s16 si12); // VdJSk12 + void VLDREPL_D(LoongArch64Reg vd, LoongArch64Reg rj, s16 si9); // VdJSk9 + void VLDREPL_W(LoongArch64Reg vd, LoongArch64Reg rj, s16 si10); // VdJSk10 + void VLDREPL_H(LoongArch64Reg vd, LoongArch64Reg rj, s16 si11); // VdJSk11 + void VLDREPL_B(LoongArch64Reg vd, LoongArch64Reg rj, s16 si12); // VdJSk12 + void VSTELM_D(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx1); // VdJSk8Un1 + void VSTELM_W(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx2); // VdJSk8Un2 + void VSTELM_H(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx3); // VdJSk8Un3 + void VSTELM_B(LoongArch64Reg vd, LoongArch64Reg rj, s16 si8, u8 idx4); // VdJSk8Un4 + void VLDX(LoongArch64Reg vd, LoongArch64Reg rj, LoongArch64Reg rk); // VdJK + void VSTX(LoongArch64Reg vd, LoongArch64Reg rj, LoongArch64Reg rk); // VdJK + void VSEQ_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSEQ_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSEQ_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSEQ_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLE_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLE_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLE_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLE_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLE_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLE_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLE_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLT_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLT_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLT_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLT_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLT_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLT_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLT_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLT_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUB_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUB_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUB_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUBWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWEV_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDWOD_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSADD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSADD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSADD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSUB_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSUB_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSUB_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSADD_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSADD_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSADD_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSADD_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSUB_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSUB_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSUB_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSUB_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHADDW_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHADDW_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHADDW_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHADDW_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHSUBW_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHSUBW_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHSUBW_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHSUBW_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHADDW_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHADDW_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHADDW_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHADDW_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHSUBW_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHSUBW_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHSUBW_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VHSUBW_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDA_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDA_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDA_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADDA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VABSD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VABSD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VABSD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VABSD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VABSD_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VABSD_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VABSD_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VABSD_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVG_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVG_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVG_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVG_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVG_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVG_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVG_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVG_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVGR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVGR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVGR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVGR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVGR_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVGR_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVGR_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VAVGR_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMAX_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMAX_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMAX_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMAX_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMIN_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMIN_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMIN_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMIN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMAX_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMAX_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMAX_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMAX_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMIN_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMIN_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMIN_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMIN_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUH_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUH_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUH_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUH_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUH_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUH_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUH_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMUH_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWEV_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMULWOD_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMSUB_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMSUB_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMSUB_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_H_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_W_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_D_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_Q_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_H_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_W_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_D_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_Q_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWEV_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_H_BU_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_W_HU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_D_WU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMADDWOD_Q_DU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VDIV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VDIV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VDIV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VDIV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMOD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMOD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMOD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMOD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VDIV_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VDIV_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VDIV_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VDIV_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMOD_BU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMOD_HU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMOD_WU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VMOD_DU(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSLL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRA_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRA_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRA_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VROTR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VROTR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VROTR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VROTR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRLR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRLR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRLR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRLR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRAR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRAR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRAR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRAR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRLN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRLN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRLN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRAN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRAN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRAN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRLRN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRLRN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRLRN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRARN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRARN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSRARN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRAN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRAN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRAN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLRN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLRN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLRN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRARN_B_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRARN_H_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRARN_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRAN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRAN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRAN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLRN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLRN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRLRN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRARN_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRARN_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSSRARN_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITCLR_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITCLR_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITCLR_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITCLR_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITSET_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITSET_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITSET_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITSET_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITREV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITREV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITREV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VBITREV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPACKEV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPACKEV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPACKEV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPACKEV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPACKOD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPACKOD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPACKOD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPACKOD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VILVL_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VILVL_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VILVL_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VILVL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VILVH_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VILVH_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VILVH_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VILVH_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPICKEV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPICKEV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPICKEV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPICKEV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPICKOD_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPICKOD_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPICKOD_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VPICKOD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VREPLVE_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk); // VdVjK + void VREPLVE_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk); // VdVjK + void VREPLVE_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk); // VdVjK + void VREPLVE_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg rk); // VdVjK + void VAND_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VOR_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VXOR_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VNOR_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VANDN_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VORN_V(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFRSTP_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFRSTP_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VADD_Q(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSUB_Q(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSIGNCOV_B(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSIGNCOV_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSIGNCOV_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSIGNCOV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFADD_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFADD_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFSUB_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFSUB_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFMUL_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFMUL_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFDIV_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFDIV_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFMAX_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFMAX_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFMIN_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFMIN_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFMAXA_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFMAXA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFMINA_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFMINA_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCVT_H_S(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFCVT_S_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFFINT_S_L(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFTINT_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFTINTRM_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFTINTRP_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFTINTRZ_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VFTINTRNE_W_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSHUF_H(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSHUF_W(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSHUF_D(LoongArch64Reg vd, LoongArch64Reg vj, LoongArch64Reg vk); // VdVjVk + void VSEQI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSEQI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSEQI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSEQI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSLEI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSLEI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSLEI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSLEI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSLEI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSLEI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSLEI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSLEI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSLTI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSLTI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSLTI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSLTI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VSLTI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSLTI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSLTI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSLTI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VADDI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VADDI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VADDI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VADDI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSUBI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSUBI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSUBI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSUBI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VBSLL_V(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VBSRL_V(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VMAXI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VMAXI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VMAXI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VMAXI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VMINI_B(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VMINI_H(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VMINI_W(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VMINI_D(LoongArch64Reg vd, LoongArch64Reg vj, s8 si5); // VdVjSk5 + void VMAXI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VMAXI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VMAXI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VMAXI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VMINI_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VMINI_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VMINI_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VMINI_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VFRSTPI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VFRSTPI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VCLO_B(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VCLO_H(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VCLO_W(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VCLO_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VCLZ_B(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VCLZ_H(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VCLZ_W(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VCLZ_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VPCNT_B(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VPCNT_H(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VPCNT_W(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VPCNT_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VNEG_B(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VNEG_H(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VNEG_W(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VNEG_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VMSKLTZ_B(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VMSKLTZ_H(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VMSKLTZ_W(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VMSKLTZ_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VMSKGEZ_B(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VMSKNZ_B(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VSETEQZ_V(LoongArch64CFR cd, LoongArch64Reg vj); // CdVj + void VSETNEZ_V(LoongArch64CFR cd, LoongArch64Reg vj); // CdVj + void VSETANYEQZ_B(LoongArch64CFR cd, LoongArch64Reg vj); // CdVj + void VSETANYEQZ_H(LoongArch64CFR cd, LoongArch64Reg vj); // CdVj + void VSETANYEQZ_W(LoongArch64CFR cd, LoongArch64Reg vj); // CdVj + void VSETANYEQZ_D(LoongArch64CFR cd, LoongArch64Reg vj); // CdVj + void VSETALLNEZ_B(LoongArch64CFR cd, LoongArch64Reg vj); // CdVj + void VSETALLNEZ_H(LoongArch64CFR cd, LoongArch64Reg vj); // CdVj + void VSETALLNEZ_W(LoongArch64CFR cd, LoongArch64Reg vj); // CdVj + void VSETALLNEZ_D(LoongArch64CFR cd, LoongArch64Reg vj); // CdVj + void VFLOGB_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFLOGB_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFCLASS_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFCLASS_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFSQRT_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFSQRT_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRECIP_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRECIP_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRSQRT_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRSQRT_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRECIPE_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRECIPE_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRSQRTE_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRSQRTE_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRINT_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRINT_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRINTRM_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRINTRM_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRINTRP_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRINTRP_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRINTRZ_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRINTRZ_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRINTRNE_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFRINTRNE_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFCVTL_S_H(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFCVTH_S_H(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFCVTL_D_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFCVTH_D_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFFINT_S_W(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFFINT_S_WU(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFFINT_D_L(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFFINT_D_LU(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFFINTL_D_W(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFFINTH_D_W(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINT_W_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINT_L_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRM_W_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRM_L_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRP_W_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRP_L_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRZ_W_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRZ_L_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRNE_W_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRNE_L_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINT_WU_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINT_LU_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRZ_WU_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRZ_LU_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTL_L_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTH_L_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRML_L_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRMH_L_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRPL_L_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRPH_L_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRZL_L_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRZH_L_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRNEL_L_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VFTINTRNEH_L_S(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VEXTH_H_B(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VEXTH_W_H(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VEXTH_D_W(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VEXTH_Q_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VEXTH_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VEXTH_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VEXTH_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VEXTH_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VREPLGR2VR_B(LoongArch64Reg vd, LoongArch64Reg rj); // VdJ + void VREPLGR2VR_H(LoongArch64Reg vd, LoongArch64Reg rj); // VdJ + void VREPLGR2VR_W(LoongArch64Reg vd, LoongArch64Reg rj); // VdJ + void VREPLGR2VR_D(LoongArch64Reg vd, LoongArch64Reg rj); // VdJ + void VROTRI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VROTRI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VROTRI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VROTRI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSRLRI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VSRLRI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSRLRI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSRLRI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSRARI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VSRARI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSRARI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSRARI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VINSGR2VR_B(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui4); // VdJUk4 + void VINSGR2VR_H(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui3); // VdJUk3 + void VINSGR2VR_W(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui2); // VdJUk2 + void VINSGR2VR_D(LoongArch64Reg vd, LoongArch64Reg rj, u8 ui1); // VdJUk1 + void VPICKVE2GR_B(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui4); // DVjUk4 + void VPICKVE2GR_H(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui3); // DVjUk3 + void VPICKVE2GR_W(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui2); // DVjUk2 + void VPICKVE2GR_D(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui1); // DVjUk1 + void VPICKVE2GR_BU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui4); // DVjUk4 + void VPICKVE2GR_HU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui3); // DVjUk3 + void VPICKVE2GR_WU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui2); // DVjUk2 + void VPICKVE2GR_DU(LoongArch64Reg rd, LoongArch64Reg vj, u8 ui1); // DVjUk1 + void VREPLVEI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VREPLVEI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VREPLVEI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui2); // VdVjUk2 + void VREPLVEI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui1); // VdVjUk1 + void VSLLWIL_H_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VSLLWIL_W_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSLLWIL_D_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VEXTL_Q_D(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VSLLWIL_HU_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VSLLWIL_WU_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSLLWIL_DU_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VEXTL_QU_DU(LoongArch64Reg vd, LoongArch64Reg vj); // VdVj + void VBITCLRI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VBITCLRI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VBITCLRI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VBITCLRI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VBITSETI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VBITSETI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VBITSETI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VBITSETI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VBITREVI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VBITREVI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VBITREVI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VBITREVI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSAT_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VSAT_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSAT_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSAT_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSAT_BU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VSAT_HU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSAT_WU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSAT_DU(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSLLI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VSLLI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSLLI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSLLI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSRLI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VSRLI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSRLI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSRLI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSRAI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui3); // VdVjUk3 + void VSRAI_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSRAI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSRAI_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSRLNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSRLNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSRLNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSRLNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VSRLRNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSRLRNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSRLRNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSRLRNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VSSRLNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSSRLNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSSRLNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSSRLNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VSSRLNI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSSRLNI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSSRLNI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSSRLNI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VSSRLRNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSSRLRNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSSRLRNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSSRLRNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VSSRLRNI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSSRLRNI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSSRLRNI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSSRLRNI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VSRANI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSRANI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSRANI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSRANI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VSRARNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSRARNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSRARNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSRARNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VSSRANI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSSRANI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSSRANI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSSRANI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VSSRANI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSSRANI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSSRANI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSSRANI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VSSRARNI_B_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSSRARNI_H_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSSRARNI_W_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSSRARNI_D_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VSSRARNI_BU_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui4); // VdVjUk4 + void VSSRARNI_HU_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui5); // VdVjUk5 + void VSSRARNI_WU_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui6); // VdVjUk6 + void VSSRARNI_DU_Q(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui7); // VdVjUk7 + void VEXTRINS_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VEXTRINS_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VEXTRINS_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VEXTRINS_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VSHUF4I_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VSHUF4I_H(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VSHUF4I_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VSHUF4I_D(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VBITSELI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VANDI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VORI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VXORI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VNORI_B(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + void VLDI(LoongArch64Reg vd, s16 i13); // VdSj13 + void VPERMI_W(LoongArch64Reg vd, LoongArch64Reg vj, u8 ui8); // VdVjUk8 + +private: + void SetJumpTarget(FixupBranch &branch, const void *dst); + bool BranchInRange(const void *src, const void *dst) const; + bool JumpInRange(const void *src, const void *dst) const; + bool BranchZeroInRange(const void *src, const void *dst) const; + + void SetRegToImmediate(LoongArch64Reg rd, uint64_t value); + + template + uint64_t AsImmediate(const T &v) { + static_assert(std::is_trivial::value, "Immediate argument must be a simple type"); + static_assert(sizeof(T) <= 8, "Immediate argument size should be 8, 16, 32, or 64 bits"); + + // Copy the type to allow floats and avoid endian issues. + if (sizeof(T) == 8) { + uint64_t value; + memcpy(&value, &v, sizeof(value)); + return value; + } else if (sizeof(T) == 4) { + uint32_t value; + memcpy(&value, &v, sizeof(value)); + if (extend) + return (int64_t)(int32_t)value; + return value; + } else if (sizeof(T) == 2) { + uint16_t value; + memcpy(&value, &v, sizeof(value)); + if (extend) + return (int64_t)(int16_t)value; + return value; + } else if (sizeof(T) == 1) { + uint8_t value; + memcpy(&value, &v, sizeof(value)); + if (extend) + return (int64_t)(int8_t)value; + return value; + } + return (uint64_t)v; + } + + inline void Write32(u32 value) { + *(u32 *)writable_ = value; + code_ += 4; + writable_ += 4; + } + +protected: + const u8 *code_ = nullptr; + u8 *writable_ = nullptr; + const u8 *lastCacheFlushEnd_ = nullptr; +}; + +class LoongArch64CodeBlock : public CodeBlock { +private: + void PoisonMemory(int offset) override; +}; + +}; \ No newline at end of file diff --git a/Core/Config.cpp b/Core/Config.cpp index ad76481c46..573bf7ae1f 100644 --- a/Core/Config.cpp +++ b/Core/Config.cpp @@ -172,7 +172,7 @@ std::string CreateRandMAC() { } static int DefaultCpuCore() { -#if PPSSPP_ARCH(ARM) || PPSSPP_ARCH(ARM64) || PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64) || PPSSPP_ARCH(RISCV64) +#if PPSSPP_ARCH(ARM) || PPSSPP_ARCH(ARM64) || PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64) || PPSSPP_ARCH(RISCV64) || PPSSPP_ARCH(LOONGARCH64) if (System_GetPropertyBool(SYSPROP_CAN_JIT)) return (int)CPUCore::JIT; return (int)CPUCore::IR_INTERPRETER; @@ -182,7 +182,7 @@ static int DefaultCpuCore() { } static bool DefaultCodeGen() { -#if PPSSPP_ARCH(ARM) || PPSSPP_ARCH(ARM64) || PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64) || PPSSPP_ARCH(RISCV64) +#if PPSSPP_ARCH(ARM) || PPSSPP_ARCH(ARM64) || PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64) || PPSSPP_ARCH(RISCV64) || PPSSPP_ARCH(LOONGARCH64) return true; #else return false; diff --git a/Core/Core.vcxproj b/Core/Core.vcxproj index 95afc14886..d60fa89adf 100644 --- a/Core/Core.vcxproj +++ b/Core/Core.vcxproj @@ -428,6 +428,7 @@ + @@ -518,6 +519,15 @@ + + + + + + + + + @@ -967,6 +977,7 @@ + @@ -1053,6 +1064,8 @@ + + diff --git a/Core/Core.vcxproj.filters b/Core/Core.vcxproj.filters index e9d8adab35..0708880166 100644 --- a/Core/Core.vcxproj.filters +++ b/Core/Core.vcxproj.filters @@ -94,6 +94,9 @@ {067e3128-3aaf-4ed1-b19e-bab11606abe7} + + {1ef9e44d-2e76-4984-a6e5-5f6f143acfc8} + @@ -1354,6 +1357,36 @@ FileLoaders + + MIPS\LoongArch64 + + + MIPS\LoongArch64 + + + MIPS\LoongArch64 + + + MIPS\LoongArch64 + + + MIPS\LoongArch64 + + + MIPS\LoongArch64 + + + MIPS\LoongArch64 + + + MIPS\LoongArch64 + + + MIPS\LoongArch64 + + + Ext + @@ -2193,6 +2226,15 @@ HLE\Libraries + + MIPS\LoongArch64 + + + MIPS\LoongArch64 + + + Ext + diff --git a/Core/MIPS/IR/IRNativeCommon.cpp b/Core/MIPS/IR/IRNativeCommon.cpp index 0bed8b1794..60d4472734 100644 --- a/Core/MIPS/IR/IRNativeCommon.cpp +++ b/Core/MIPS/IR/IRNativeCommon.cpp @@ -762,6 +762,8 @@ JitBlockDebugInfo IRNativeBlockCacheDebugInterface::GetBlockDebugInfo(int blockN debugInfo.targetDisasm = DisassembleX86(blockStart, codeSize); #elif PPSSPP_ARCH(RISCV64) debugInfo.targetDisasm = DisassembleRV64(blockStart, codeSize); +#elif PPSSPP_ARCH(LOONGARCH64) + debugInfo.targetDisasm = DisassembleLA64(blockStart, codeSize); #endif return debugInfo; } diff --git a/Core/MIPS/JitCommon/JitBlockCache.cpp b/Core/MIPS/JitCommon/JitBlockCache.cpp index 1eb7020d66..e3861c83e6 100644 --- a/Core/MIPS/JitCommon/JitBlockCache.cpp +++ b/Core/MIPS/JitCommon/JitBlockCache.cpp @@ -662,6 +662,9 @@ int JitBlockCache::GetBlockExitSize() { #elif PPSSPP_ARCH(RISCV64) // Will depend on the sequence found to encode the destination address. return 0; +#elif PPSSPP_ARCH(LOONGARCH64) + // Will depend on the sequence found to encode the destination address. + return 0; #else #warning GetBlockExitSize unimplemented return 0; @@ -715,6 +718,8 @@ JitBlockDebugInfo JitBlockCache::GetBlockDebugInfo(int blockNum) const { debugInfo.targetDisasm = DisassembleX86(block->normalEntry, block->codeSize); #elif PPSSPP_ARCH(RISCV64) debugInfo.targetDisasm = DisassembleRV64(block->normalEntry, block->codeSize); +#elif PPSSPP_ARCH(LOONGARCH64) + debugInfo.targetDisasm = DisassembleLA64(block->normalEntry, block->codeSize); #endif return debugInfo; } diff --git a/Core/MIPS/JitCommon/JitCommon.cpp b/Core/MIPS/JitCommon/JitCommon.cpp index 1708bf1ea6..104ef69d3e 100644 --- a/Core/MIPS/JitCommon/JitCommon.cpp +++ b/Core/MIPS/JitCommon/JitCommon.cpp @@ -22,6 +22,7 @@ #include "ext/disarm.h" #include "ext/riscv-disas.h" #include "ext/udis86/udis86.h" +#include "ext/loongarch-disasm.h" #include "Common/LogReporting.h" #include "Common/StringUtils.h" @@ -49,6 +50,8 @@ #include "../MIPS/MipsJit.h" #elif PPSSPP_ARCH(RISCV64) #include "../RiscV/RiscVJit.h" +#elif PPSSPP_ARCH(LOONGARCH64) +#include "../LoongArch64/LoongArch64Jit.h" #else #include "../fake/FakeJit.h" #endif @@ -118,6 +121,8 @@ namespace MIPSComp { return new MIPSComp::MipsJit(mipsState); #elif PPSSPP_ARCH(RISCV64) return new MIPSComp::RiscVJit(mipsState); +#elif PPSSPP_ARCH(LOONGARCH64) + return new MIPSComp::LoongArch64Jit(mipsState); #else return new MIPSComp::FakeJit(mipsState); #endif @@ -358,3 +363,30 @@ std::vector DisassembleRV64(const u8 *data, int size) { return lines; } #endif + +#if PPSSPP_ARCH(LOONGARCH64) || defined(DISASM_ALL) +std::vector DisassembleLA64(const u8 *data, int size) { + std::vector lines; + + int invalid_count = 0; + auto invalid_flush = [&]() { + if (invalid_count != 0) { + lines.push_back(StringFromFormat("(%d invalid bytes)", invalid_count)); + invalid_count = 0; + } + }; + + char temp[512]; + Ins ins; + for (int i = 0; i < size; i += 4) { + const u32 *codePtr = (const u32 *)(data + i); + invalid_flush(); + la_disasm(*codePtr, &ins); + sprint_ins(&ins, temp); + lines.push_back(ReplaceAll(temp, "\t", " ")); + } + + invalid_flush(); + return lines; +} +#endif diff --git a/Core/MIPS/JitCommon/JitCommon.h b/Core/MIPS/JitCommon/JitCommon.h index 7de9ddb2e1..46ebe6dea8 100644 --- a/Core/MIPS/JitCommon/JitCommon.h +++ b/Core/MIPS/JitCommon/JitCommon.h @@ -29,6 +29,7 @@ std::vector DisassembleArm2(const u8 *data, int size); std::vector DisassembleArm64(const u8 *data, int size); std::vector DisassembleX86(const u8 *data, int size); std::vector DisassembleRV64(const u8 *data, int size); +std::vector DisassembleLA64(const u8 *data, int size); struct JitBlock; class JitBlockCache; diff --git a/Core/MIPS/JitCommon/JitState.cpp b/Core/MIPS/JitCommon/JitState.cpp index 9144513cca..6e6a397501 100644 --- a/Core/MIPS/JitCommon/JitState.cpp +++ b/Core/MIPS/JitCommon/JitState.cpp @@ -60,7 +60,7 @@ namespace MIPSComp { useStaticAlloc = false; enablePointerify = false; -#if PPSSPP_ARCH(ARM64) || PPSSPP_ARCH(RISCV64) +#if PPSSPP_ARCH(ARM64) || PPSSPP_ARCH(RISCV64) || PPSSPP_ARCH(LOONGARCH64) useStaticAlloc = !Disabled(JitDisable::STATIC_ALLOC); // iOS/etc. may disable at runtime if Memory::base is not nicely aligned. enablePointerify = !Disabled(JitDisable::POINTERIFY); diff --git a/Core/MIPS/LoongArch64/LoongArch64Asm.cpp b/Core/MIPS/LoongArch64/LoongArch64Asm.cpp new file mode 100644 index 0000000000..5dc3e91688 --- /dev/null +++ b/Core/MIPS/LoongArch64/LoongArch64Asm.cpp @@ -0,0 +1,242 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "Common/Log.h" +#include "Core/CoreTiming.h" +#include "Core/MemMap.h" +#include "Core/MIPS/LoongArch64/LoongArch64Jit.h" +#include "Core/MIPS/LoongArch64/LoongArch64RegCache.h" +#include "Core/MIPS/JitCommon/JitCommon.h" +#include "Core/MIPS/JitCommon/JitState.h" +#include "Core/Core.h" + +namespace MIPSComp { + +using namespace LoongArch64Gen; +using namespace LoongArch64JitConstants; + +static const bool enableDebug = false; +static const bool enableDisasm = false; + +static void ShowPC(u32 downcount, void *membase, void *jitbase) { + static int count = 0; + if (currentMIPS) { + ERROR_LOG(Log::JIT, "[%08x] ShowPC Downcount : %08x %d %p %p", currentMIPS->pc, downcount, count, membase, jitbase); + } else { + ERROR_LOG(Log::JIT, "Universe corrupt?"); + } + count++; +} + +void LoongArch64JitBackend::GenerateFixedCode(MIPSState *mipsState) { + // This will be used as a writable scratch area, always 32-bit accessible. + const u8 *start = AlignCodePage(); + if (DebugProfilerEnabled()) { + ProtectMemoryPages(start, GetMemoryProtectPageSize(), MEM_PROT_READ | MEM_PROT_WRITE); + hooks_.profilerPC = (uint32_t *)GetWritableCodePtr(); + *hooks_.profilerPC = 0; + hooks_.profilerStatus = (IRProfilerStatus *)GetWritableCodePtr() + 1; + *hooks_.profilerStatus = IRProfilerStatus::NOT_RUNNING; + SetCodePointer(GetCodePtr() + sizeof(uint32_t) * 2, GetWritableCodePtr() + sizeof(uint32_t) * 2); + } + + const u8 *disasmStart = AlignCodePage(); + BeginWrite(GetMemoryProtectPageSize()); + if (jo.useStaticAlloc) { + saveStaticRegisters_ = AlignCode16(); + ST_W(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount)); + regs_.EmitSaveStaticRegisters(); + RET(); + + loadStaticRegisters_ = AlignCode16(); + regs_.EmitLoadStaticRegisters(); + LD_W(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount)); + RET(); + } else { + saveStaticRegisters_ = nullptr; + loadStaticRegisters_ = nullptr; + } + + applyRoundingMode_ = AlignCode16(); + { + // LoongArch64 does not have any flush to zero capability, so leaving it off + LD_WU(SCRATCH2, CTXREG, offsetof(MIPSState, fcr31)); + + // We can skip if the rounding mode is nearest (0) and flush is not set. + // (as restoreRoundingMode cleared it out anyway) + FixupBranch skip = BEQZ(SCRATCH2); + + // MIPS Rounding Mode: LoongArch64 + // 0: Round nearest 0 RNE + // 1: Round to zero 1 RZ + // 2: Round up (ceil) 2 RP + // 3: Round down (floor) 3 RM + MOVGR2FCSR(FCSR3, SCRATCH2); + + SetJumpTarget(skip); + RET(); + } + + hooks_.enterDispatcher = (IRNativeFuncNoArg)AlignCode16(); + + // Start by saving some regs on the stack. There are 11 GPs and 8 FPs we want. + // Note: we leave R_SP as, well, SP, so it doesn't need to be saved. + static constexpr LoongArch64Reg regs_to_save[]{ R_RA, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31 }; + // TODO: Maybe we shouldn't regalloc all of these? Is it worth it? + static constexpr LoongArch64Reg regs_to_save_fp[]{ F24, F25, F26, F27, F28, F29, F30, F31 }; + int saveSize = (64 / 8) * (int)(ARRAY_SIZE(regs_to_save) + ARRAY_SIZE(regs_to_save_fp)); + if (saveSize & 0xF) + saveSize += 8; + _assert_msg_((saveSize & 0xF) == 0, "Stack must be kept aligned"); + int saveOffset = 0; + ADDI_D(R_SP, R_SP, -saveSize); + for (LoongArch64Reg r : regs_to_save) { + ST_D(r, R_SP, saveOffset); + saveOffset += 64 / 8; + } + for (LoongArch64Reg r : regs_to_save_fp) { + FST_D(r, R_SP, saveOffset); + saveOffset += 64 / 8; + } + _assert_(saveOffset <= saveSize); + + // Fixed registers, these are always kept when in Jit context. + LI(MEMBASEREG, Memory::base); + LI(CTXREG, mipsState); + LI(JITBASEREG, GetBasePtr() - MIPS_EMUHACK_OPCODE); + + LoadStaticRegisters(); + WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT); + MovFromPC(SCRATCH1); + WriteDebugPC(SCRATCH1); + outerLoopPCInSCRATCH1_ = GetCodePtr(); + MovToPC(SCRATCH1); + outerLoop_ = GetCodePtr(); + // Advance can change the downcount (or thread), so must save/restore around it. + SaveStaticRegisters(); + RestoreRoundingMode(true); + WriteDebugProfilerStatus(IRProfilerStatus::TIMER_ADVANCE); + QuickCallFunction(&CoreTiming::Advance, R20); + WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT); + ApplyRoundingMode(true); + LoadStaticRegisters(); + + dispatcherCheckCoreState_ = GetCodePtr(); + LI(SCRATCH1, &coreState); + LD_W(SCRATCH1, SCRATCH1, 0); + FixupBranch badCoreState = BNEZ(SCRATCH1); + + // We just checked coreState, so go to advance if downcount is negative. + BLT(DOWNCOUNTREG, R_ZERO, outerLoop_); + FixupBranch skipToRealDispatch = B(); + + dispatcherPCInSCRATCH1_ = GetCodePtr(); + MovToPC(SCRATCH1); + + hooks_.dispatcher = GetCodePtr(); + FixupBranch bail = BLT(DOWNCOUNTREG, R_ZERO); + SetJumpTarget(skipToRealDispatch); + + dispatcherNoCheck_ = GetCodePtr(); + + // Debug + if (enableDebug) { + MOVE(R4, DOWNCOUNTREG); + MOVE(R5, MEMBASEREG); + MOVE(R6, JITBASEREG); + QuickCallFunction(&ShowPC, R20); + } + + LD_WU(SCRATCH1, CTXREG, offsetof(MIPSState, pc)); + WriteDebugPC(SCRATCH1); +#ifdef MASKED_PSP_MEMORY + LI(SCRATCH2, 0x3FFFFFFF); + AND(SCRATCH1, SCRATCH1, SCRATCH2); +#endif + ADD_D(SCRATCH1, SCRATCH1, MEMBASEREG); + hooks_.dispatchFetch = GetCodePtr(); + LD_WU(SCRATCH1, SCRATCH1, 0); + SRLI_D(SCRATCH2, SCRATCH1, 24); + // We're in other words comparing to the top 8 bits of MIPS_EMUHACK_OPCODE by subtracting. + ADDI_D(SCRATCH2, SCRATCH2, -(MIPS_EMUHACK_OPCODE >> 24)); + FixupBranch needsCompile = BNEZ(SCRATCH2); + // No need to mask, JITBASEREG has already accounted for the upper bits. + ADD_D(SCRATCH1, JITBASEREG, SCRATCH1); + JR(SCRATCH1); + SetJumpTarget(needsCompile); + + // No block found, let's jit. We don't need to save static regs, they're all callee saved. + RestoreRoundingMode(true); + WriteDebugProfilerStatus(IRProfilerStatus::COMPILING); + QuickCallFunction(&MIPSComp::JitAt, R20); + WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT); + ApplyRoundingMode(true); + + // Try again, the block index should be set now. + B(dispatcherNoCheck_); + + SetJumpTarget(bail); + + LI(SCRATCH1, &coreState); + LD_W(SCRATCH1, SCRATCH1, 0); + BEQZ(SCRATCH1, outerLoop_); + + const uint8_t *quitLoop = GetCodePtr(); + SetJumpTarget(badCoreState); + + WriteDebugProfilerStatus(IRProfilerStatus::NOT_RUNNING); + SaveStaticRegisters(); + RestoreRoundingMode(true); + + saveOffset = 0; + for (LoongArch64Reg r : regs_to_save) { + LD_D(r, R_SP, saveOffset); + saveOffset += 64 / 8; + } + for (LoongArch64Reg r : regs_to_save_fp) { + FLD_D(r, R_SP, saveOffset); + saveOffset += 64 / 8; + } + ADDI_D(R_SP, R_SP, saveSize); + + RET(); + + hooks_.crashHandler = GetCodePtr(); + LI(SCRATCH1, &coreState); + LI(SCRATCH2, CORE_RUNTIME_ERROR); + ST_W(SCRATCH2, SCRATCH1, 0); + B(quitLoop); + + // Leave this at the end, add more stuff above. + if (enableDisasm) { +#if PPSSPP_ARCH(LOONGARCH64) + std::vector lines = DisassembleLA64(start, GetCodePtr() - start); + for (auto s : lines) { + INFO_LOG(Log::JIT, "%s", s.c_str()); + } +#endif + } + + // Let's spare the pre-generated code from unprotect-reprotect. + AlignCodePage(); + jitStartOffset_ = (int)(GetCodePtr() - start); + // Don't forget to zap the instruction cache! This must stay at the end of this function. + FlushIcache(); + EndWrite(); +} + +} // namespace MIPSComp diff --git a/Core/MIPS/LoongArch64/LoongArch64CompALU.cpp b/Core/MIPS/LoongArch64/LoongArch64CompALU.cpp new file mode 100644 index 0000000000..4ce4fc2ddf --- /dev/null +++ b/Core/MIPS/LoongArch64/LoongArch64CompALU.cpp @@ -0,0 +1,658 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "Common/CPUDetect.h" +#include "Core/MemMap.h" +#include "Core/MIPS/LoongArch64/LoongArch64Jit.h" +#include "Core/MIPS/LoongArch64/LoongArch64RegCache.h" + +// This file contains compilation for integer / arithmetic / logic related instructions. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace LoongArch64Gen; +using namespace LoongArch64JitConstants; + +void LoongArch64JitBackend::CompIR_Arith(IRInst inst) { + CONDITIONAL_DISABLE; + + bool allowPtrMath = true; +#ifdef MASKED_PSP_MEMORY + // Since we modify it, we can't safely. + allowPtrMath = false; +#endif + + // LoongArch64 only adds signed immediates, so rewrite a small enough subtract to an add. + // We use -2047 and 2048 here because the range swaps. + if (inst.op == IROp::SubConst && (int32_t)inst.constant >= -2047 && (int32_t)inst.constant <= 2048) { + inst.op = IROp::AddConst; + inst.constant = (uint32_t)-(int32_t)inst.constant; + } + + switch (inst.op) { + case IROp::Add: + regs_.Map(inst); + ADD_W(regs_.R(inst.dest), regs_.R(inst.src1), regs_.R(inst.src2)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::Sub: + regs_.Map(inst); + SUB_W(regs_.R(inst.dest), regs_.R(inst.src1), regs_.R(inst.src2)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::AddConst: + if ((int32_t)inst.constant >= -2048 && (int32_t)inst.constant <= 2047) { + // Typical of stack pointer updates. + if (regs_.IsGPRMappedAsPointer(inst.dest) && inst.dest == inst.src1 && allowPtrMath) { + regs_.MarkGPRAsPointerDirty(inst.dest); + ADDI_D(regs_.RPtr(inst.dest), regs_.RPtr(inst.dest), inst.constant); + } else { + regs_.Map(inst); + ADDI_W(regs_.R(inst.dest), regs_.R(inst.src1), inst.constant); + regs_.MarkGPRDirty(inst.dest, true); + } + } else { + regs_.Map(inst); + LI(SCRATCH1, (int32_t)inst.constant); + ADD_W(regs_.R(inst.dest), regs_.R(inst.src1), SCRATCH1); + regs_.MarkGPRDirty(inst.dest, true); + } + break; + + case IROp::SubConst: + regs_.Map(inst); + LI(SCRATCH1, (int32_t)inst.constant); + SUB_W(regs_.R(inst.dest), regs_.R(inst.src1), SCRATCH1); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::Neg: + regs_.Map(inst); + SUB_W(regs_.R(inst.dest), R_ZERO, regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_Logic(IRInst inst) { + CONDITIONAL_DISABLE; + + bool resultNormalized = false; + switch (inst.op) { + case IROp::And: + if (inst.src1 != inst.src2) { + regs_.Map(inst); + AND(regs_.R(inst.dest), regs_.R(inst.src1), regs_.R(inst.src2)); + } else if (inst.src1 != inst.dest) { + regs_.Map(inst); + MOVE(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(inst.src1)); + } + break; + + case IROp::Or: + if (inst.src1 != inst.src2) { + // If both were normalized before, the result is normalized. + resultNormalized = regs_.IsNormalized32(inst.src1) && regs_.IsNormalized32(inst.src2); + regs_.Map(inst); + OR(regs_.R(inst.dest), regs_.R(inst.src1), regs_.R(inst.src2)); + regs_.MarkGPRDirty(inst.dest, resultNormalized); + } else if (inst.src1 != inst.dest) { + regs_.Map(inst); + MOVE(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(inst.src1)); + } + break; + + case IROp::Xor: + if (inst.src1 == inst.src2) { + regs_.SetGPRImm(inst.dest, 0); + } else { + regs_.Map(inst); + XOR(regs_.R(inst.dest), regs_.R(inst.src1), regs_.R(inst.src2)); + } + break; + + case IROp::AndConst: + resultNormalized = regs_.IsNormalized32(inst.src1); + regs_.Map(inst); + // LoongArch64's ANDI use unsigned 12-bit immediate + if ((int32_t)inst.constant >= 0 && (int32_t)inst.constant < 4096) { + ANDI(regs_.R(inst.dest), regs_.R(inst.src1), inst.constant); + } else { + LI(SCRATCH1, (int32_t)inst.constant); + AND(regs_.R(inst.dest), regs_.R(inst.src1), SCRATCH1); + } + // If the sign bits aren't cleared, and it was normalized before - it still is. + if ((inst.constant & 0x80000000) != 0 && resultNormalized) + regs_.MarkGPRDirty(inst.dest, true); + // Otherwise, if we cleared the sign bits, it's naturally normalized. + else if ((inst.constant & 0x80000000) == 0) + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::OrConst: + resultNormalized = regs_.IsNormalized32(inst.src1); + regs_.Map(inst); + if ((int32_t)inst.constant >= 0 && (int32_t)inst.constant < 4096) { + ORI(regs_.R(inst.dest), regs_.R(inst.src1), inst.constant); + } else { + LI(SCRATCH1, (int32_t)inst.constant); + OR(regs_.R(inst.dest), regs_.R(inst.src1), SCRATCH1); + } + // Since our constant is normalized, oring its bits in won't hurt normalization. + regs_.MarkGPRDirty(inst.dest, resultNormalized); + break; + + case IROp::XorConst: + regs_.Map(inst); + if ((int32_t)inst.constant >= 0 && (int32_t)inst.constant < 4096) { + XORI(regs_.R(inst.dest), regs_.R(inst.src1), inst.constant); + } else { + LI(SCRATCH1, (int32_t)inst.constant); + XOR(regs_.R(inst.dest), regs_.R(inst.src1), SCRATCH1); + } + break; + + case IROp::Not: + regs_.Map(inst); + ORN(regs_.R(inst.dest), R_ZERO, regs_.R(inst.src1)); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_Assign(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Mov: + if (inst.dest != inst.src1) { + regs_.Map(inst); + MOVE(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(inst.src1)); + } + break; + + case IROp::Ext8to32: + regs_.Map(inst); + EXT_W_B(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::Ext16to32: + regs_.Map(inst); + EXT_W_H(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_Bits(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::ReverseBits: + regs_.Map(inst); + BITREV_W(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::BSwap16: + regs_.Map(inst); + REVB_2H(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::BSwap32: + regs_.Map(inst); + REVB_2W(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::Clz: + regs_.Map(inst); + CLZ_W(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_Shift(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Shl: + regs_.Map(inst); + SLL_W(regs_.R(inst.dest), regs_.R(inst.src1), regs_.R(inst.src2)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::Shr: + regs_.Map(inst); + SRL_W(regs_.R(inst.dest), regs_.R(inst.src1), regs_.R(inst.src2)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::Sar: + regs_.Map(inst); + SRA_W(regs_.R(inst.dest), regs_.R(inst.src1), regs_.R(inst.src2)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::Ror: + regs_.Map(inst); + ROTR_W(regs_.R(inst.dest), regs_.R(inst.src1), regs_.R(inst.src2)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::ShlImm: + // Shouldn't happen, but let's be safe of any passes that modify the ops. + if (inst.src2 >= 32) { + regs_.SetGPRImm(inst.dest, 0); + } else if (inst.src2 == 0) { + if (inst.dest != inst.src1) { + regs_.Map(inst); + MOVE(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(inst.src1)); + } + } else { + regs_.Map(inst); + SLLI_W(regs_.R(inst.dest), regs_.R(inst.src1), inst.src2); + regs_.MarkGPRDirty(inst.dest, true); + } + break; + + case IROp::ShrImm: + // Shouldn't happen, but let's be safe of any passes that modify the ops. + if (inst.src2 >= 32) { + regs_.SetGPRImm(inst.dest, 0); + } else if (inst.src2 == 0) { + if (inst.dest != inst.src1) { + regs_.Map(inst); + MOVE(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(inst.src1)); + } + } else { + regs_.Map(inst); + SRLI_W(regs_.R(inst.dest), regs_.R(inst.src1), inst.src2); + regs_.MarkGPRDirty(inst.dest, true); + } + break; + + case IROp::SarImm: + // Shouldn't happen, but let's be safe of any passes that modify the ops. + if (inst.src2 >= 32) { + regs_.Map(inst); + SRAI_W(regs_.R(inst.dest), regs_.R(inst.src1), 31); + regs_.MarkGPRDirty(inst.dest, true); + } else if (inst.src2 == 0) { + if (inst.dest != inst.src1) { + regs_.Map(inst); + MOVE(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(inst.src1)); + } + } else { + regs_.Map(inst); + SRAI_W(regs_.R(inst.dest), regs_.R(inst.src1), inst.src2); + regs_.MarkGPRDirty(inst.dest, true); + } + break; + + case IROp::RorImm: + if (inst.src2 == 0) { + if (inst.dest != inst.src1) { + regs_.Map(inst); + MOVE(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(inst.src1)); + } + } else { + regs_.Map(inst); + ROTRI_W(regs_.R(inst.dest), regs_.R(inst.src1), inst.src2 & 31); + regs_.MarkGPRDirty(inst.dest, true); + } + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_Compare(IRInst inst) { + CONDITIONAL_DISABLE; + + LoongArch64Reg lhs = INVALID_REG; + LoongArch64Reg rhs = INVALID_REG; + switch (inst.op) { + case IROp::Slt: + regs_.Map(inst); + NormalizeSrc12(inst, &lhs, &rhs, SCRATCH1, SCRATCH2, true); + + SLT(regs_.R(inst.dest), lhs, rhs); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::SltConst: + if (inst.constant == 0) { + // Basically, getting the sign bit. Let's shift instead. + regs_.Map(inst); + SRLI_W(regs_.R(inst.dest), regs_.R(inst.src1), 31); + regs_.MarkGPRDirty(inst.dest, true); + } else { + regs_.Map(inst); + NormalizeSrc1(inst, &lhs, SCRATCH1, false); + + if ((int32_t)inst.constant >= -2048 && (int32_t)inst.constant <= 2047) { + SLTI(regs_.R(inst.dest), lhs, (int32_t)inst.constant); + } else { + LI(SCRATCH2, (int32_t)inst.constant); + SLT(regs_.R(inst.dest), lhs, SCRATCH2); + } + regs_.MarkGPRDirty(inst.dest, true); + } + break; + + case IROp::SltU: + regs_.Map(inst); + // It's still fine to sign extend, the biggest just get even bigger. + NormalizeSrc12(inst, &lhs, &rhs, SCRATCH1, SCRATCH2, true); + + SLTU(regs_.R(inst.dest), lhs, rhs); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::SltUConst: + if (inst.constant == 0) { + regs_.SetGPRImm(inst.dest, 0); + } else { + regs_.Map(inst); + NormalizeSrc1(inst, &lhs, SCRATCH1, false); + + // We sign extend because we're comparing against something normalized. + // It's also the most efficient to set. + if ((int32_t)inst.constant >= -2048 && (int32_t)inst.constant <= 2047) { + SLTUI(regs_.R(inst.dest), lhs, (int32_t)inst.constant); + } else { + LI(SCRATCH2, (int32_t)inst.constant); + SLTU(regs_.R(inst.dest), lhs, SCRATCH2); + } + regs_.MarkGPRDirty(inst.dest, true); + } + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_CondAssign(IRInst inst) { + CONDITIONAL_DISABLE; + + LoongArch64Reg lhs = INVALID_REG; + LoongArch64Reg rhs = INVALID_REG; + FixupBranch fixup; + switch (inst.op) { + case IROp::MovZ: + case IROp::MovNZ: + if (inst.dest == inst.src2) + return; + + // We could have a "zero" with wrong upper due to XOR, so we have to normalize. + regs_.Map(inst); + NormalizeSrc1(inst, &lhs, SCRATCH1, true); + + switch (inst.op) { + case IROp::MovZ: + fixup = BNEZ(lhs); + break; + case IROp::MovNZ: + fixup = BEQZ(lhs); + break; + default: + INVALIDOP; + break; + } + + MOVE(regs_.R(inst.dest), regs_.R(inst.src2)); + SetJumpTarget(fixup); + break; + + case IROp::Max: + if (inst.src1 != inst.src2) { + CompIR_Generic(inst); + } else if (inst.dest != inst.src1) { + regs_.Map(inst); + MOVE(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(inst.src1)); + } + break; + + case IROp::Min: + if (inst.src1 != inst.src2) { + CompIR_Generic(inst); + } else if (inst.dest != inst.src1) { + regs_.Map(inst); + MOVE(regs_.R(inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(inst.src1)); + } + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_HiLo(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::MtLo: + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } }); + // 32-63 bits of IRREG_LO + 0-31 bits of inst.src1 + BSTRINS_D(regs_.R(IRREG_LO), regs_.R(inst.src1), 31, 0); + break; + + case IROp::MtHi: + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } }); + BSTRINS_D(regs_.R(IRREG_LO), regs_.R(inst.src1), 63, 32); + break; + + case IROp::MfLo: + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::INIT } }); + // It won't be normalized, but that's fine... + MOVE(regs_.R(inst.dest), regs_.R(IRREG_LO)); + break; + + case IROp::MfHi: + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::INIT } }); + SRAI_D(regs_.R(inst.dest), regs_.R(IRREG_LO), 32); + regs_.MarkGPRDirty(inst.dest, true); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_Mult(IRInst inst) { + CONDITIONAL_DISABLE; + + auto putArgsIntoScratches = [&](LoongArch64Reg *lhs, LoongArch64Reg *rhs) { + MOVE(SCRATCH1, regs_.R(inst.src1)); + MOVE(SCRATCH2, regs_.R(inst.src2)); + *lhs = SCRATCH1; + *rhs = SCRATCH2; + }; + + LoongArch64Reg lhs = INVALID_REG; + LoongArch64Reg rhs = INVALID_REG; + switch (inst.op) { + case IROp::Mult: + // TODO: Maybe IR could simplify when HI is not needed or clobbered? + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::NOINIT } }); + NormalizeSrc12(inst, &lhs, &rhs, SCRATCH1, SCRATCH2, true); + MUL_D(regs_.R(IRREG_LO), lhs, rhs); + break; + + case IROp::MultU: + // This is an "anti-norm32" case. Let's just zero always. + // TODO: If we could know that LO was only needed, we could use MULW. + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::NOINIT } }); + putArgsIntoScratches(&lhs, &rhs); + MULW_D_WU(regs_.R(IRREG_LO), lhs, rhs); + break; + + case IROp::Madd: + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } }); + NormalizeSrc12(inst, &lhs, &rhs, SCRATCH1, SCRATCH2, true); + MUL_D(SCRATCH1, lhs, rhs); + ADD_D(regs_.R(IRREG_LO), regs_.R(IRREG_LO), SCRATCH1); + break; + + case IROp::MaddU: + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } }); + putArgsIntoScratches(&lhs, &rhs); + MULW_D_WU(SCRATCH1, lhs, rhs); + ADD_D(regs_.R(IRREG_LO), regs_.R(IRREG_LO), SCRATCH1); + break; + + case IROp::Msub: + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } }); + NormalizeSrc12(inst, &lhs, &rhs, SCRATCH1, SCRATCH2, true); + MUL_D(SCRATCH1, lhs, rhs); + SUB_D(regs_.R(IRREG_LO), regs_.R(IRREG_LO), SCRATCH1); + break; + + case IROp::MsubU: + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::DIRTY } }); + putArgsIntoScratches(&lhs, &rhs); + MULW_D_WU(SCRATCH1, lhs, rhs); + SUB_D(regs_.R(IRREG_LO), regs_.R(IRREG_LO), SCRATCH1); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_Div(IRInst inst) { + CONDITIONAL_DISABLE; + + LoongArch64Reg numReg, denomReg; + switch (inst.op) { + case IROp::Div: + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::NOINIT } }); + // We have to do this because of the divide by zero and overflow checks below. + NormalizeSrc12(inst, &numReg, &denomReg, SCRATCH1, SCRATCH2, true); + DIV_W(regs_.R(IRREG_LO), numReg, denomReg); + MOD_W(R_RA, numReg, denomReg); + // Now to combine them. We'll do more with them below... + BSTRINS_D(regs_.R(IRREG_LO), R_RA, 63, 32); + + // Now some tweaks for divide by zero and overflow. + { + // Start with divide by zero, the quotient and remainder are arbitrary numbers. + FixupBranch skipNonZero = BNEZ(denomReg); + // Clear the arbitrary number + XOR(regs_.R(IRREG_LO), regs_.R(IRREG_LO), regs_.R(IRREG_LO)); + // Replace remainder to numReg + BSTRINS_D(regs_.R(IRREG_LO), numReg, 63, 32); + FixupBranch keepNegOne = BGE(numReg, R_ZERO); + // Replace quotient with 1. + ADDI_D(regs_.R(IRREG_LO), regs_.R(IRREG_LO), 1); + SetJumpTarget(keepNegOne); + // Replace quotient with -1. + ADDI_D(regs_.R(IRREG_LO), regs_.R(IRREG_LO), -1); + SetJumpTarget(skipNonZero); + + // For overflow, LoongArch sets LO right, but remainder to zero. + // Cheating a bit by using R_RA as a temp... + LI(R_RA, (int32_t)0x80000000); + FixupBranch notMostNegative = BNE(numReg, R_RA); + LI(R_RA, -1); + FixupBranch notNegativeOne = BNE(denomReg, R_RA); + // Take our R_RA and put it in the high bits. + SLLI_D(R_RA, R_RA, 32); + OR(regs_.R(IRREG_LO), regs_.R(IRREG_LO), R_RA); + SetJumpTarget(notNegativeOne); + SetJumpTarget(notMostNegative); + } + break; + + case IROp::DivU: + regs_.MapWithExtra(inst, { { 'G', IRREG_LO, 2, MIPSMap::NOINIT } }); + // We have to do this because of the divide by zero check below. + NormalizeSrc12(inst, &numReg, &denomReg, SCRATCH1, SCRATCH2, true); + DIV_WU(regs_.R(IRREG_LO), numReg, denomReg); + MOD_WU(R_RA, numReg, denomReg); + + // On divide by zero, special dealing with the 0xFFFF case. + { + FixupBranch skipNonZero = BNEZ(denomReg); + // Move -1 to quotient. + ADDI_D(regs_.R(IRREG_LO), R_ZERO, -1); + // Move numReg to remainder (stores in RA currently). + MOVE(R_RA, numReg); + // Luckily, we don't need SCRATCH2/denomReg anymore. + LI(SCRATCH2, 0xFFFF); + FixupBranch keepNegOne = BLTU(SCRATCH2, numReg); + MOVE(regs_.R(IRREG_LO), SCRATCH2); + SetJumpTarget(keepNegOne); + SetJumpTarget(skipNonZero); + } + + // Now combine the remainder in. + BSTRINS_D(regs_.R(IRREG_LO), R_RA, 63, 32); + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp diff --git a/Core/MIPS/LoongArch64/LoongArch64CompBranch.cpp b/Core/MIPS/LoongArch64/LoongArch64CompBranch.cpp new file mode 100644 index 0000000000..129e386179 --- /dev/null +++ b/Core/MIPS/LoongArch64/LoongArch64CompBranch.cpp @@ -0,0 +1,143 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "Core/MIPS/LoongArch64/LoongArch64Jit.h" +#include "Core/MIPS/LoongArch64/LoongArch64RegCache.h" + +// This file contains compilation for exits. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace LoongArch64Gen; +using namespace LoongArch64JitConstants; + +void LoongArch64JitBackend::CompIR_Exit(IRInst inst) { + CONDITIONAL_DISABLE; + + LoongArch64Reg exitReg = INVALID_REG; + switch (inst.op) { + case IROp::ExitToConst: + FlushAll(); + WriteConstExit(inst.constant); + break; + + case IROp::ExitToReg: + exitReg = regs_.MapGPR(inst.src1); + FlushAll(); + // TODO: If ever we don't read this back in dispatcherPCInSCRATCH1_, we should zero upper. + MOVE(SCRATCH1, exitReg); + QuickJ(R_RA, dispatcherPCInSCRATCH1_); + break; + + case IROp::ExitToPC: + FlushAll(); + QuickJ(R_RA, dispatcherCheckCoreState_); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_ExitIf(IRInst inst) { + CONDITIONAL_DISABLE; + + LoongArch64Reg lhs = INVALID_REG; + LoongArch64Reg rhs = INVALID_REG; + FixupBranch fixup; + switch (inst.op) { + case IROp::ExitToConstIfEq: + case IROp::ExitToConstIfNeq: + regs_.Map(inst); + // We can't use SCRATCH1, which is destroyed by FlushAll()... but cheat and use R_RA. + NormalizeSrc12(inst, &lhs, &rhs, R_RA, SCRATCH2, true); + FlushAll(); + + switch (inst.op) { + case IROp::ExitToConstIfEq: + fixup = BNE(lhs, rhs); + break; + + case IROp::ExitToConstIfNeq: + fixup = BEQ(lhs, rhs); + break; + + default: + INVALIDOP; + break; + } + + WriteConstExit(inst.constant); + SetJumpTarget(fixup); + break; + + case IROp::ExitToConstIfGtZ: + case IROp::ExitToConstIfGeZ: + case IROp::ExitToConstIfLtZ: + case IROp::ExitToConstIfLeZ: + regs_.Map(inst); + NormalizeSrc1(inst, &lhs, SCRATCH2, true); + FlushAll(); + + switch (inst.op) { + case IROp::ExitToConstIfGtZ: + fixup = BGE(R_ZERO, lhs); + break; + + case IROp::ExitToConstIfGeZ: + fixup = BLT(lhs, R_ZERO); + break; + + case IROp::ExitToConstIfLtZ: + fixup = BGE(lhs, R_ZERO); + break; + + case IROp::ExitToConstIfLeZ: + fixup = BLT(R_ZERO, lhs); + break; + + default: + INVALIDOP; + break; + } + + WriteConstExit(inst.constant); + SetJumpTarget(fixup); + break; + + case IROp::ExitToConstIfFpTrue: + case IROp::ExitToConstIfFpFalse: + // Note: not used. + DISABLE; + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp diff --git a/Core/MIPS/LoongArch64/LoongArch64CompFPU.cpp b/Core/MIPS/LoongArch64/LoongArch64CompFPU.cpp new file mode 100644 index 0000000000..c7482117c2 --- /dev/null +++ b/Core/MIPS/LoongArch64/LoongArch64CompFPU.cpp @@ -0,0 +1,607 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "Core/MemMap.h" +#include "Core/MIPS/LoongArch64/LoongArch64Jit.h" +#include "Core/MIPS/LoongArch64/LoongArch64RegCache.h" + +// This file contains compilation for floating point related instructions. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace LoongArch64Gen; +using namespace LoongArch64JitConstants; + +void LoongArch64JitBackend::CompIR_FArith(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::FAdd: + regs_.Map(inst); + FADD_S(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2)); + break; + + case IROp::FSub: + regs_.Map(inst); + FSUB_S(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2)); + break; + + case IROp::FMul: + regs_.Map(inst); + // We'll assume everyone will make it such that 0 * infinity = NAN properly. + // See blame on this comment if that proves untrue. + FMUL_S(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2)); + break; + + case IROp::FDiv: + regs_.Map(inst); + FDIV_S(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2)); + break; + + case IROp::FSqrt: + regs_.Map(inst); + FSQRT_S(regs_.F(inst.dest), regs_.F(inst.src1)); + break; + + case IROp::FNeg: + regs_.Map(inst); + FNEG_S(regs_.F(inst.dest), regs_.F(inst.src1)); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_FCondAssign(IRInst inst) { + CONDITIONAL_DISABLE; + + regs_.Map(inst); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CUN); + MOVCF2GR(SCRATCH1, FCC0); + FixupBranch unordered = BNEZ(SCRATCH1); + + switch (inst.op) { + case IROp::FMin: + FMIN_S(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2)); + break; + + case IROp::FMax: + FMAX_S(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2)); + break; + + default: + INVALIDOP; + break; + } + + FixupBranch ordererDone = B(); + SetJumpTarget(unordered); + + MOVFR2GR_S(SCRATCH1, regs_.F(inst.src1)); + MOVFR2GR_S(SCRATCH2, regs_.F(inst.src2)); + + // If both are negative, we flip the comparison (not two's compliment.) + // We cheat and use RA... + AND(R_RA, SCRATCH1, SCRATCH2); + SRLI_W(R_RA, R_RA, 31); + + LoongArch64Reg isSrc1LowerReg = regs_.GetAndLockTempGPR(); + SLT(isSrc1LowerReg, SCRATCH1, SCRATCH2); + // Flip the flag (to reverse the min/max) based on if both were negative. + XOR(isSrc1LowerReg, isSrc1LowerReg, R_RA); + FixupBranch useSrc1; + switch (inst.op) { + case IROp::FMin: + useSrc1 = BNEZ(isSrc1LowerReg); + break; + + case IROp::FMax: + useSrc1 = BEQZ(isSrc1LowerReg); + break; + + default: + INVALIDOP; + break; + } + MOVE(SCRATCH1, SCRATCH2); + SetJumpTarget(useSrc1); + + MOVGR2FR_W(regs_.F(inst.dest), SCRATCH1); + + SetJumpTarget(ordererDone); +} + +void LoongArch64JitBackend::CompIR_FAssign(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::FMov: + if (inst.dest != inst.src1) { + regs_.Map(inst); + FMOV_S(regs_.F(inst.dest), regs_.F(inst.src1)); + } + break; + + case IROp::FAbs: + regs_.Map(inst); + FABS_S(regs_.F(inst.dest), regs_.F(inst.src1)); + break; + + case IROp::FSign: + { + regs_.Map(inst); + // Check if it's negative zero, either 0x20/0x200 is zero. + FCLASS_S(SCRATCHF1, regs_.F(inst.src1)); + MOVFR2GR_S(SCRATCH1, SCRATCHF1); + ANDI(SCRATCH1, SCRATCH1, 0x220); + SLTUI(SCRATCH1, SCRATCH1, 1); + // Okay, it's zero if zero, 1 otherwise. Convert 1 to a constant 1.0. + // Probably non-zero is the common case, so we make that the straight line. + FixupBranch skipOne = BEQZ(SCRATCH1); + LI(SCRATCH1, 1.0f); + + // Now we just need the sign from it. + MOVFR2GR_S(SCRATCH2, regs_.F(inst.src1)); + // Use a wall to isolate the sign, and combine. + SRAI_W(SCRATCH2, SCRATCH2, 31); + SLLI_W(SCRATCH2, SCRATCH2, 31); + OR(SCRATCH1, SCRATCH1, SCRATCH2); + + SetJumpTarget(skipOne); + MOVGR2FR_W(regs_.F(inst.dest), SCRATCH1); + break; + } + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_FRound(IRInst inst) { + CONDITIONAL_DISABLE; + + regs_.Map(inst); + // FTINT* instruction will convert NAN to zero, tested on 3A6000. + QuickFLI(32, SCRATCHF1, (uint32_t)0x7fffffffl, SCRATCH1); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src1), LoongArch64Fcond::CUN); + + switch (inst.op) { + case IROp::FRound: + FTINTRNE_W_S(regs_.F(inst.dest), regs_.F(inst.src1)); + break; + + case IROp::FTrunc: + FTINTRZ_W_S(regs_.F(inst.dest), regs_.F(inst.src1)); + break; + + case IROp::FCeil: + FTINTRP_W_S(regs_.F(inst.dest), regs_.F(inst.src1)); + break; + + case IROp::FFloor: + FTINTRM_W_S(regs_.F(inst.dest), regs_.F(inst.src1)); + break; + + default: + INVALIDOP; + break; + } + + // Switch to INT_MAX if it was NAN. + FSEL(regs_.F(inst.dest), regs_.F(inst.dest), SCRATCHF1, FCC0); +} + +void LoongArch64JitBackend::CompIR_FCvt(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::FCvtWS: + CompIR_Generic(inst); + break; + + case IROp::FCvtSW: + regs_.Map(inst); + FFINT_S_W(regs_.F(inst.dest), regs_.F(inst.src1)); + break; + + case IROp::FCvtScaledWS: + regs_.Map(inst); + // Prepare for the NAN result + QuickFLI(32, SCRATCHF1, (uint32_t)(0x7FFFFFFF), SCRATCH1); + // Prepare the multiplier. + QuickFLI(32, SCRATCHF1, (float)(1UL << (inst.src2 & 0x1F)), SCRATCH1); + + switch (inst.src2 >> 6) { + case 0: // RNE + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src1), LoongArch64Fcond::CUN); + FMUL_S(regs_.F(inst.dest), regs_.F(inst.src1), SCRATCHF1); + FTINTRNE_W_S(regs_.F(inst.dest), regs_.F(inst.dest)); + FSEL(regs_.F(inst.dest), regs_.F(inst.dest), SCRATCHF2, FCC0); + break; + case 1: // RZ + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src1), LoongArch64Fcond::CUN); + FMUL_S(regs_.F(inst.dest), regs_.F(inst.src1), SCRATCHF1); + FTINTRZ_W_S(regs_.F(inst.dest), regs_.F(inst.dest)); + FSEL(regs_.F(inst.dest), regs_.F(inst.dest), SCRATCHF2, FCC0); + break; + case 2: // RP + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src1), LoongArch64Fcond::CUN); + FMUL_S(regs_.F(inst.dest), regs_.F(inst.src1), SCRATCHF1); + FTINTRP_W_S(regs_.F(inst.dest), regs_.F(inst.dest)); + FSEL(regs_.F(inst.dest), regs_.F(inst.dest), SCRATCHF2, FCC0); + break; + case 3: // RM + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src1), LoongArch64Fcond::CUN); + FMUL_S(regs_.F(inst.dest), regs_.F(inst.src1), SCRATCHF1); + FTINTRM_W_S(regs_.F(inst.dest), regs_.F(inst.dest)); + FSEL(regs_.F(inst.dest), regs_.F(inst.dest), SCRATCHF2, FCC0); + break; + default: + _assert_msg_(false, "Invalid rounding mode for FCvtScaledWS"); + } + + break; + + case IROp::FCvtScaledSW: + regs_.Map(inst); + FFINT_S_W(regs_.F(inst.dest), regs_.F(inst.src1)); + + // Pre-divide so we can avoid any actual divide. + QuickFLI(32, SCRATCHF1, 1.0f / (1UL << (inst.src2 & 0x1F)), SCRATCH1); + FMUL_S(regs_.F(inst.dest), regs_.F(inst.dest), SCRATCHF1); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_FSat(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::FSat0_1: + regs_.Map(inst); + QuickFLI(32, SCRATCHF1, (float)1.0f, SCRATCH1); + // Check whether FMAX takes the larger of the two zeros, which is what we want. + QuickFLI(32, SCRATCHF2, (float)0.0f, SCRATCH1); + + FMIN_S(regs_.F(inst.dest), regs_.F(inst.src1), SCRATCHF1); + FMAX_S(regs_.F(inst.dest), regs_.F(inst.dest), SCRATCHF2); + break; + + case IROp::FSatMinus1_1: + regs_.Map(inst); + QuickFLI(32, SCRATCHF1, (float)1.0f, SCRATCH1); + FNEG_S(SCRATCHF2, SCRATCHF1); + + FMIN_S(regs_.F(inst.dest), regs_.F(inst.src1), SCRATCHF1); + FMAX_S(regs_.F(inst.dest), regs_.F(inst.dest), SCRATCHF2); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_FCompare(IRInst inst) { + CONDITIONAL_DISABLE; + + constexpr IRReg IRREG_VFPU_CC = IRREG_VFPU_CTRL_BASE + VFPU_CTRL_CC; + + switch (inst.op) { + case IROp::FCmp: + switch (inst.dest) { + case IRFpCompareMode::False: + regs_.SetGPRImm(IRREG_FPCOND, 0); + break; + + case IRFpCompareMode::EitherUnordered: + regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } }); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CUN); + MOVCF2GR(regs_.R(IRREG_FPCOND), FCC0); + regs_.MarkGPRDirty(IRREG_FPCOND, true); + break; + + case IRFpCompareMode::EqualOrdered: + regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } }); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CEQ); + MOVCF2GR(regs_.R(IRREG_FPCOND), FCC0); + regs_.MarkGPRDirty(IRREG_FPCOND, true); + break; + + case IRFpCompareMode::EqualUnordered: + regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } }); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CUEQ); + MOVCF2GR(regs_.R(IRREG_FPCOND), FCC0); + regs_.MarkGPRDirty(IRREG_FPCOND, true); + break; + + case IRFpCompareMode::LessEqualOrdered: + regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } }); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CLE); + MOVCF2GR(regs_.R(IRREG_FPCOND), FCC0); + regs_.MarkGPRDirty(IRREG_FPCOND, true); + break; + + case IRFpCompareMode::LessEqualUnordered: + regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } }); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CULE); + MOVCF2GR(regs_.R(IRREG_FPCOND), FCC0); + regs_.MarkGPRDirty(IRREG_FPCOND, true); + break; + + case IRFpCompareMode::LessOrdered: + regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } }); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CLT); + MOVCF2GR(regs_.R(IRREG_FPCOND), FCC0); + regs_.MarkGPRDirty(IRREG_FPCOND, true); + break; + + case IRFpCompareMode::LessUnordered: + regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } }); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CULT); + MOVCF2GR(regs_.R(IRREG_FPCOND), FCC0); + regs_.MarkGPRDirty(IRREG_FPCOND, true); + break; + + default: + _assert_msg_(false, "Unexpected IRFpCompareMode %d", inst.dest); + } + break; + + case IROp::FCmovVfpuCC: + regs_.MapWithExtra(inst, { { 'G', IRREG_VFPU_CC, 1, MIPSMap::INIT } }); + if ((inst.src2 & 0xF) == 0) { + ANDI(SCRATCH1, regs_.R(IRREG_VFPU_CC), 1); + } else { + BSTRPICK_D(SCRATCH1, regs_.R(IRREG_VFPU_CC), inst.src2 & 0xF, inst.src2 & 0xF); + } + if ((inst.src2 >> 7) & 1) { + FixupBranch skip = BEQZ(SCRATCH1); + FMOV_S(regs_.F(inst.dest), regs_.F(inst.src1)); + SetJumpTarget(skip); + } else { + FixupBranch skip = BNEZ(SCRATCH1); + FMOV_S(regs_.F(inst.dest), regs_.F(inst.src1)); + SetJumpTarget(skip); + } + break; + + case IROp::FCmpVfpuBit: + regs_.MapGPR(IRREG_VFPU_CC, MIPSMap::DIRTY); + + switch (VCondition(inst.dest & 0xF)) { + case VC_EQ: + regs_.Map(inst); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CEQ); + MOVCF2GR(SCRATCH1, FCC0); + break; + case VC_NE: + regs_.Map(inst); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CNE); + MOVCF2GR(SCRATCH1, FCC0); + break; + case VC_LT: + regs_.Map(inst); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CLT); + MOVCF2GR(SCRATCH1, FCC0); + break; + case VC_LE: + regs_.Map(inst); + FCMP_COND_S(FCC0, regs_.F(inst.src1), regs_.F(inst.src2), LoongArch64Fcond::CLE); + MOVCF2GR(SCRATCH1, FCC0); + break; + case VC_GT: + regs_.Map(inst); + FCMP_COND_S(FCC0, regs_.F(inst.src2), regs_.F(inst.src1), LoongArch64Fcond::CLT); + MOVCF2GR(SCRATCH1, FCC0); + break; + case VC_GE: + regs_.Map(inst); + FCMP_COND_S(FCC0, regs_.F(inst.src2), regs_.F(inst.src1), LoongArch64Fcond::CLE); + MOVCF2GR(SCRATCH1, FCC0); + break; + case VC_EZ: + case VC_NZ: + regs_.MapFPR(inst.src1); + // Zero is either 0x20 or 0x200. + FCLASS_S(SCRATCHF1, regs_.F(inst.src1)); + MOVFR2GR_S(SCRATCH1, SCRATCHF1); + ANDI(SCRATCH1, SCRATCH1, 0x220); + if ((inst.dest & 4) == 0) + SLTU(SCRATCH1, R_ZERO, SCRATCH1); + else + SLTUI(SCRATCH1, SCRATCH1, 1); + break; + case VC_EN: + case VC_NN: + regs_.MapFPR(inst.src1); + // NAN is either 0x1 or 0x2. + FCLASS_S(SCRATCHF1, regs_.F(inst.src1)); + MOVFR2GR_S(SCRATCH1, SCRATCHF1); + ANDI(SCRATCH1, SCRATCH1, 0x3); + if ((inst.dest & 4) == 0) + SLTU(SCRATCH1, R_ZERO, SCRATCH1); + else + SLTUI(SCRATCH1, SCRATCH1, 1); + break; + case VC_EI: + case VC_NI: + regs_.MapFPR(inst.src1); + // Infinity is either 0x40 or 0x04. + FCLASS_S(SCRATCHF1, regs_.F(inst.src1)); + MOVFR2GR_S(SCRATCH1, SCRATCHF1); + ANDI(SCRATCH1, SCRATCH1, 0x44); + if ((inst.dest & 4) == 0) + SLTU(SCRATCH1, R_ZERO, SCRATCH1); + else + SLTUI(SCRATCH1, SCRATCH1, 1); + break; + case VC_ES: + case VC_NS: + regs_.MapFPR(inst.src1); + // Infinity is either 0x40 or 0x04, NAN is either 0x1 or 0x2. + FCLASS_S(SCRATCHF1, regs_.F(inst.src1)); + MOVFR2GR_S(SCRATCH1, SCRATCHF1); + ANDI(SCRATCH1, SCRATCH1, 0x47); + if ((inst.dest & 4) == 0) + SLTU(SCRATCH1, R_ZERO, SCRATCH1); + else + SLTUI(SCRATCH1, SCRATCH1, 1); + break; + case VC_TR: + LI(SCRATCH1, 1); + break; + case VC_FL: + LI(SCRATCH1, 0); + break; + } + + ANDI(regs_.R(IRREG_VFPU_CC), regs_.R(IRREG_VFPU_CC), ~(1 << (inst.dest >> 4))); + if ((inst.dest >> 4) != 0) + SLLI_D(SCRATCH1, SCRATCH1, inst.dest >> 4); + OR(regs_.R(IRREG_VFPU_CC), regs_.R(IRREG_VFPU_CC), SCRATCH1); + break; + + case IROp::FCmpVfpuAggregate: + regs_.MapGPR(IRREG_VFPU_CC, MIPSMap::DIRTY); + if (inst.dest == 1) { + ANDI(SCRATCH1, regs_.R(IRREG_VFPU_CC), inst.dest); + // Negate so 1 becomes all bits set and zero stays zero, then mask to 0x30. + SUB_D(SCRATCH1, R_ZERO, SCRATCH1); + ANDI(SCRATCH1, SCRATCH1, 0x30); + + // Reject the old any/all bits and replace them with our own. + ANDI(regs_.R(IRREG_VFPU_CC), regs_.R(IRREG_VFPU_CC), ~0x30); + OR(regs_.R(IRREG_VFPU_CC), regs_.R(IRREG_VFPU_CC), SCRATCH1); + } else { + ANDI(SCRATCH1, regs_.R(IRREG_VFPU_CC), inst.dest); + FixupBranch skipZero = BEQZ(SCRATCH1); + + // To compare to inst.dest for "all", let's simply subtract it and compare to zero. + ADDI_D(SCRATCH1, SCRATCH1, -inst.dest); + SLTUI(SCRATCH1, SCRATCH1, 1); + // Now we combine with the "any" bit. + SLLI_D(SCRATCH1, SCRATCH1, 5); + ORI(SCRATCH1, SCRATCH1, 0x10); + + SetJumpTarget(skipZero); + + // Reject the old any/all bits and replace them with our own. + ANDI(regs_.R(IRREG_VFPU_CC), regs_.R(IRREG_VFPU_CC), ~0x30); + OR(regs_.R(IRREG_VFPU_CC), regs_.R(IRREG_VFPU_CC), SCRATCH1); + } + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_RoundingMode(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::RestoreRoundingMode: + RestoreRoundingMode(); + break; + + case IROp::ApplyRoundingMode: + ApplyRoundingMode(); + break; + + case IROp::UpdateRoundingMode: + // Do nothing, we don't use any instructions that need updating the rounding mode. + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_FSpecial(IRInst inst) { + CONDITIONAL_DISABLE; + + auto callFuncF_F = [&](float (*func)(float)) { + regs_.FlushBeforeCall(); + WriteDebugProfilerStatus(IRProfilerStatus::MATH_HELPER); + + // It might be in a non-volatile register. + // TODO: May have to handle a transfer if SIMD here. + if (regs_.IsFPRMapped(inst.src1)) { + FMOV_S(F0, regs_.F(inst.src1)); + } else { + int offset = offsetof(MIPSState, f) + inst.src1 * 4; + FLD_S(F0, CTXREG, offset); + } + QuickCallFunction(func, SCRATCH1); + + regs_.MapFPR(inst.dest, MIPSMap::NOINIT); + // If it's already F0, we're done - MapReg doesn't actually overwrite the reg in that case. + if (regs_.F(inst.dest) != F0) { + FMOV_S(regs_.F(inst.dest), F0); + } + + WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT); + }; + + switch (inst.op) { + case IROp::FSin: + callFuncF_F(&vfpu_sin); + break; + + case IROp::FCos: + callFuncF_F(&vfpu_cos); + break; + + case IROp::FRSqrt: + regs_.Map(inst); + FRSQRT_S(regs_.F(inst.dest), regs_.F(inst.src1)); + break; + + case IROp::FRecip: + regs_.Map(inst); + FRECIP_S(regs_.F(inst.dest), regs_.F(inst.src1)); + break; + + case IROp::FAsin: + callFuncF_F(&vfpu_asin); + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp \ No newline at end of file diff --git a/Core/MIPS/LoongArch64/LoongArch64CompLoadStore.cpp b/Core/MIPS/LoongArch64/LoongArch64CompLoadStore.cpp new file mode 100644 index 0000000000..51f773369f --- /dev/null +++ b/Core/MIPS/LoongArch64/LoongArch64CompLoadStore.cpp @@ -0,0 +1,396 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "Core/MemMap.h" +#include "Core/MIPS/LoongArch64/LoongArch64Jit.h" +#include "Core/MIPS/LoongArch64/LoongArch64RegCache.h" + +// This file contains compilation for load/store instructions. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace LoongArch64Gen; +using namespace LoongArch64JitConstants; + +void LoongArch64JitBackend::SetScratch1ToSrc1Address(IRReg src1) { + regs_.MapGPR(src1); +#ifdef MASKED_PSP_MEMORY + SLLI_W(SCRATCH1, regs_.R(src1), 2); + SRLI_W(SCRATCH1, SCRATCH1, 2); + ADD_D(SCRATCH1, SCRATCH1, MEMBASEREG); +#else + // Clear the top bits to be safe. + SLLI_D(SCRATCH1, regs_.R(src1), 32); + SRLI_D(SCRATCH1, SCRATCH1, 32); + ADD_D(SCRATCH1, SCRATCH1, MEMBASEREG); +#endif +} + +int32_t LoongArch64JitBackend::AdjustForAddressOffset(LoongArch64Gen::LoongArch64Reg *reg, int32_t constant, int32_t range) { + if (constant < -2048 || constant + range > 2047) { +#ifdef MASKED_PSP_MEMORY + if (constant > 0) + constant &= Memory::MEMVIEW32_MASK; +#endif + // It can't be this negative, must be a constant with top bit set. + if ((constant & 0xC0000000) == 0x80000000) { + LI(SCRATCH2, (uint32_t)constant); + ADD_D(SCRATCH1, *reg, SCRATCH2); + } else { + LI(SCRATCH2, constant); + ADD_D(SCRATCH1, *reg, SCRATCH2); + } + *reg = SCRATCH1; + return 0; + } + return constant; +} + +void LoongArch64JitBackend::CompIR_Load(IRInst inst) { + CONDITIONAL_DISABLE; + + regs_.SpillLockGPR(inst.dest, inst.src1); + LoongArch64Reg addrReg = INVALID_REG; + if (inst.src1 == MIPS_REG_ZERO) { + // This will get changed by AdjustForAddressOffset. + addrReg = MEMBASEREG; +#ifdef MASKED_PSP_MEMORY + inst.constant &= Memory::MEMVIEW32_MASK; +#endif + } else if (jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) { + addrReg = regs_.MapGPRAsPointer(inst.src1); + } else { + SetScratch1ToSrc1Address(inst.src1); + addrReg = SCRATCH1; + } + // With NOINIT, MapReg won't subtract MEMBASEREG even if dest == src1. + regs_.MapGPR(inst.dest, MIPSMap::NOINIT); + regs_.MarkGPRDirty(inst.dest, true); + + s32 imm = AdjustForAddressOffset(&addrReg, inst.constant); + + // TODO: Safe memory? Or enough to have crash handler + validate? + + switch (inst.op) { + case IROp::Load8: + LD_BU(regs_.R(inst.dest), addrReg, imm); + break; + + case IROp::Load8Ext: + LD_B(regs_.R(inst.dest), addrReg, imm); + break; + + case IROp::Load16: + LD_HU(regs_.R(inst.dest), addrReg, imm); + break; + + case IROp::Load16Ext: + LD_H(regs_.R(inst.dest), addrReg, imm); + break; + + case IROp::Load32: + LD_W(regs_.R(inst.dest), addrReg, imm); + break; + + case IROp::Load32Linked: + if (inst.dest != MIPS_REG_ZERO) + LD_W(regs_.R(inst.dest), addrReg, imm); + regs_.SetGPRImm(IRREG_LLBIT, 1); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_LoadShift(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Load32Left: + case IROp::Load32Right: + // Should not happen if the pass to split is active. + DISABLE; + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_FLoad(IRInst inst) { + CONDITIONAL_DISABLE; + + LoongArch64Reg addrReg = INVALID_REG; + if (inst.src1 == MIPS_REG_ZERO) { + // This will get changed by AdjustForAddressOffset. + addrReg = MEMBASEREG; +#ifdef MASKED_PSP_MEMORY + inst.constant &= Memory::MEMVIEW32_MASK; +#endif + } else if (jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) { + addrReg = regs_.MapGPRAsPointer(inst.src1); + } else { + SetScratch1ToSrc1Address(inst.src1); + addrReg = SCRATCH1; + } + + s32 imm = AdjustForAddressOffset(&addrReg, inst.constant); + + // TODO: Safe memory? Or enough to have crash handler + validate? + + switch (inst.op) { + case IROp::LoadFloat: + regs_.MapFPR(inst.dest, MIPSMap::NOINIT); + FLD_S(regs_.F(inst.dest), addrReg, imm); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_VecLoad(IRInst inst) { + CONDITIONAL_DISABLE; + + LoongArch64Reg addrReg = INVALID_REG; + if (inst.src1 == MIPS_REG_ZERO) { + // This will get changed by AdjustForAddressOffset. + addrReg = MEMBASEREG; +#ifdef MASKED_PSP_MEMORY + inst.constant &= Memory::MEMVIEW32_MASK; +#endif + } else if (jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) { + addrReg = regs_.MapGPRAsPointer(inst.src1); + } else { + SetScratch1ToSrc1Address(inst.src1); + addrReg = SCRATCH1; + } + + // We need to be able to address the whole 16 bytes, so offset of 12. + s32 imm = AdjustForAddressOffset(&addrReg, inst.constant, 12); + + // TODO: Safe memory? Or enough to have crash handler + validate? + + switch (inst.op) { + case IROp::LoadVec4: + if (cpu_info.LOONGARCH_LSX) { + regs_.MapVec4(inst.dest, MIPSMap::NOINIT); + VLD(regs_.V(inst.dest), addrReg, imm); + } else { + for (int i = 0; i < 4; ++i) { + // Spilling is okay. + regs_.MapFPR(inst.dest + i, MIPSMap::NOINIT); + FLD_S(regs_.F(inst.dest + i), addrReg, imm + 4 * i); + } + } + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_Store(IRInst inst) { + CONDITIONAL_DISABLE; + + regs_.SpillLockGPR(inst.src3, inst.src1); + LoongArch64Reg addrReg = INVALID_REG; + if (inst.src1 == MIPS_REG_ZERO) { + // This will get changed by AdjustForAddressOffset. + addrReg = MEMBASEREG; +#ifdef MASKED_PSP_MEMORY + inst.constant &= Memory::MEMVIEW32_MASK; +#endif + } else if ((jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) && inst.src3 != inst.src1) { + addrReg = regs_.MapGPRAsPointer(inst.src1); + } else { + SetScratch1ToSrc1Address(inst.src1); + addrReg = SCRATCH1; + } + LoongArch64Reg valueReg = regs_.TryMapTempImm(inst.src3); + if (valueReg == INVALID_REG) + valueReg = regs_.MapGPR(inst.src3); + + s32 imm = AdjustForAddressOffset(&addrReg, inst.constant); + + // TODO: Safe memory? Or enough to have crash handler + validate? + + switch (inst.op) { + case IROp::Store8: + ST_B(valueReg, addrReg, imm); + break; + + case IROp::Store16: + ST_H(valueReg, addrReg, imm); + break; + + case IROp::Store32: + ST_W(valueReg, addrReg, imm); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_CondStore(IRInst inst) { + CONDITIONAL_DISABLE; + if (inst.op != IROp::Store32Conditional) + INVALIDOP; + + regs_.SpillLockGPR(IRREG_LLBIT, inst.src3, inst.src1); + LoongArch64Reg addrReg = INVALID_REG; + if (inst.src1 == MIPS_REG_ZERO) { + // This will get changed by AdjustForAddressOffset. + addrReg = MEMBASEREG; +#ifdef MASKED_PSP_MEMORY + inst.constant &= Memory::MEMVIEW32_MASK; +#endif + } else if ((jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) && inst.src3 != inst.src1) { + addrReg = regs_.MapGPRAsPointer(inst.src1); + } else { + SetScratch1ToSrc1Address(inst.src1); + addrReg = SCRATCH1; + } + regs_.MapGPR(inst.src3, inst.dest == MIPS_REG_ZERO ? MIPSMap::INIT : MIPSMap::DIRTY); + regs_.MapGPR(IRREG_LLBIT); + + s32 imm = AdjustForAddressOffset(&addrReg, inst.constant); + + // TODO: Safe memory? Or enough to have crash handler + validate? + + FixupBranch condFailed = BEQZ(regs_.R(IRREG_LLBIT)); + ST_W(regs_.R(inst.src3), addrReg, imm); + + if (inst.dest != MIPS_REG_ZERO) { + LI(regs_.R(inst.dest), 1); + FixupBranch finish = B(); + + SetJumpTarget(condFailed); + LI(regs_.R(inst.dest), 0); + SetJumpTarget(finish); + } else { + SetJumpTarget(condFailed); + } +} + +void LoongArch64JitBackend::CompIR_StoreShift(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Store32Left: + case IROp::Store32Right: + // Should not happen if the pass to split is active. + DISABLE; + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_FStore(IRInst inst) { + CONDITIONAL_DISABLE; + + LoongArch64Reg addrReg = INVALID_REG; + if (inst.src1 == MIPS_REG_ZERO) { + // This will get changed by AdjustForAddressOffset. + addrReg = MEMBASEREG; +#ifdef MASKED_PSP_MEMORY + inst.constant &= Memory::MEMVIEW32_MASK; +#endif + } else if (jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) { + addrReg = regs_.MapGPRAsPointer(inst.src1); + } else { + SetScratch1ToSrc1Address(inst.src1); + addrReg = SCRATCH1; + } + + s32 imm = AdjustForAddressOffset(&addrReg, inst.constant); + + // TODO: Safe memory? Or enough to have crash handler + validate? + + switch (inst.op) { + case IROp::StoreFloat: + regs_.MapFPR(inst.src3); + FST_S(regs_.F(inst.src3), addrReg, imm); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_VecStore(IRInst inst) { + CONDITIONAL_DISABLE; + + LoongArch64Reg addrReg = INVALID_REG; + if (inst.src1 == MIPS_REG_ZERO) { + // This will get changed by AdjustForAddressOffset. + addrReg = MEMBASEREG; +#ifdef MASKED_PSP_MEMORY + inst.constant &= Memory::MEMVIEW32_MASK; +#endif + } else if (jo.cachePointers || regs_.IsGPRMappedAsPointer(inst.src1)) { + addrReg = regs_.MapGPRAsPointer(inst.src1); + } else { + SetScratch1ToSrc1Address(inst.src1); + addrReg = SCRATCH1; + } + + // We need to be able to address the whole 16 bytes, so offset of 12. + s32 imm = AdjustForAddressOffset(&addrReg, inst.constant, 12); + + // TODO: Safe memory? Or enough to have crash handler + validate? + + switch (inst.op) { + case IROp::StoreVec4: + if (cpu_info.LOONGARCH_LSX) { + regs_.MapVec4(inst.src3); + VST(regs_.V(inst.src3), addrReg, imm); + } else { + for (int i = 0; i < 4; ++i) { + // Spilling is okay, though not ideal. + regs_.MapFPR(inst.src3 + i); + FST_S(regs_.F(inst.src3 + i), addrReg, imm + 4 * i); + } + } + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp diff --git a/Core/MIPS/LoongArch64/LoongArch64CompSystem.cpp b/Core/MIPS/LoongArch64/LoongArch64CompSystem.cpp new file mode 100644 index 0000000000..759551834f --- /dev/null +++ b/Core/MIPS/LoongArch64/LoongArch64CompSystem.cpp @@ -0,0 +1,278 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include "Common/Profiler/Profiler.h" +#include "Core/Core.h" +#include "Core/HLE/HLE.h" +#include "Core/HLE/ReplaceTables.h" +#include "Core/MemMap.h" +#include "Core/MIPS/LoongArch64/LoongArch64Jit.h" +#include "Core/MIPS/LoongArch64/LoongArch64RegCache.h" + +// This file contains compilation for basic PC/downcount accounting, syscalls, debug funcs, etc. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace LoongArch64Gen; +using namespace LoongArch64JitConstants; + +void LoongArch64JitBackend::CompIR_Basic(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::SetConst: + // Sign extend all constants. We get 0xFFFFFFFF sometimes, and it's more work to truncate. + // The register only holds 32 bits in the end anyway. + regs_.SetGPRImm(inst.dest, (int32_t)inst.constant); + break; + + case IROp::SetConstF: + regs_.Map(inst); + if (inst.constant == 0) + MOVGR2FR_W(regs_.F(inst.dest), R_ZERO); + else + QuickFLI(32, regs_.F(inst.dest), inst.constant, SCRATCH1); + break; + + case IROp::Downcount: + if (inst.constant <= 2048) { + ADDI_D(DOWNCOUNTREG, DOWNCOUNTREG, -(s32)inst.constant); + } else { + LI(SCRATCH1, inst.constant); + SUB_D(DOWNCOUNTREG, DOWNCOUNTREG, SCRATCH1); + } + break; + + case IROp::SetPC: + regs_.Map(inst); + MovToPC(regs_.R(inst.src1)); + break; + + case IROp::SetPCConst: + LI(SCRATCH1, inst.constant); + MovToPC(SCRATCH1); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_Transfer(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::SetCtrlVFPU: + regs_.SetGPRImm(IRREG_VFPU_CTRL_BASE + inst.dest, inst.constant); + break; + + case IROp::SetCtrlVFPUReg: + regs_.Map(inst); + MOVE(regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.R(inst.src1)); + regs_.MarkGPRDirty(IRREG_VFPU_CTRL_BASE + inst.dest, regs_.IsNormalized32(inst.src1)); + break; + + case IROp::SetCtrlVFPUFReg: + regs_.Map(inst); + MOVGR2FR_W(regs_.R(IRREG_VFPU_CTRL_BASE + inst.dest), regs_.F(inst.src1)); + regs_.MarkGPRDirty(IRREG_VFPU_CTRL_BASE + inst.dest, true); + break; + + case IROp::FpCondFromReg: + regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } }); + MOVE(regs_.R(IRREG_FPCOND), regs_.R(inst.src1)); + break; + + case IROp::FpCondToReg: + regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::INIT } }); + MOVE(regs_.R(inst.dest), regs_.R(IRREG_FPCOND)); + regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(IRREG_FPCOND)); + break; + + case IROp::FpCtrlFromReg: + regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::NOINIT } }); + LI(SCRATCH1, 0x0181FFFF); + AND(SCRATCH1, regs_.R(inst.src1), SCRATCH1); + // Extract the new fpcond value. + BSTRPICK_D(regs_.R(IRREG_FPCOND), regs_.R(IRREG_FPCOND), 23, 23); + ST_W(SCRATCH1, CTXREG, IRREG_FCR31 * 4); + regs_.MarkGPRDirty(IRREG_FPCOND, true); + break; + + case IROp::FpCtrlToReg: + regs_.MapWithExtra(inst, { { 'G', IRREG_FPCOND, 1, MIPSMap::INIT } }); + // Load fcr31 and clear the fpcond bit. + LD_W(SCRATCH1, CTXREG, IRREG_FCR31 * 4); + LI(SCRATCH2, ~(1 << 23)); + AND(SCRATCH1, SCRATCH1, SCRATCH2); + + // Now get the correct fpcond bit. + ANDI(SCRATCH2, regs_.R(IRREG_FPCOND), 1); + SLLI_D(SCRATCH2, SCRATCH2, 23); + OR(regs_.R(inst.dest), SCRATCH1, SCRATCH2); + + // Also update mips->fcr31 while we're here. + ST_W(regs_.R(inst.dest), CTXREG, IRREG_FCR31 * 4); + regs_.MarkGPRDirty(inst.dest, true); + break; + + case IROp::VfpuCtrlToReg: + regs_.Map(inst); + MOVE(regs_.R(inst.dest), regs_.R(IRREG_VFPU_CTRL_BASE + inst.src1)); + regs_.MarkGPRDirty(inst.dest, regs_.IsNormalized32(IRREG_VFPU_CTRL_BASE + inst.src1)); + break; + + case IROp::FMovFromGPR: + if (regs_.IsGPRImm(inst.src1) && regs_.GetGPRImm(inst.src1) == 0) { + regs_.MapFPR(inst.dest, MIPSMap::NOINIT); + MOVGR2FR_W(regs_.F(inst.dest), R_ZERO); + FFINT_S_W(regs_.F(inst.dest), regs_.F(inst.dest)); + } else { + regs_.Map(inst); + MOVGR2FR_W(regs_.F(inst.dest), regs_.R(inst.src1)); + } + break; + + case IROp::FMovToGPR: + regs_.Map(inst); + MOVFR2GR_S(regs_.R(inst.dest), regs_.F(inst.src1)); + regs_.MarkGPRDirty(inst.dest, true); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_System(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Syscall: + FlushAll(); + SaveStaticRegisters(); + + WriteDebugProfilerStatus(IRProfilerStatus::SYSCALL); +#ifdef USE_PROFILER + // When profiling, we can't skip CallSyscall, since it times syscalls. + LI(R4, (int32_t)inst.constant); + QuickCallFunction(&CallSyscall, SCRATCH2); +#else + // Skip the CallSyscall where possible. + { + MIPSOpcode op(inst.constant); + void *quickFunc = GetQuickSyscallFunc(op); + if (quickFunc) { + LI(R4, (uintptr_t)GetSyscallFuncPointer(op)); + QuickCallFunction((const u8 *)quickFunc, SCRATCH2); + } else { + LI(R4, (int32_t)inst.constant); + QuickCallFunction(&CallSyscall, SCRATCH2); + } + } +#endif + + WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT); + LoadStaticRegisters(); + // This is always followed by an ExitToPC, where we check coreState. + break; + + case IROp::CallReplacement: + FlushAll(); + SaveStaticRegisters(); + WriteDebugProfilerStatus(IRProfilerStatus::REPLACEMENT); + QuickCallFunction(GetReplacementFunc(inst.constant)->replaceFunc, SCRATCH2); + WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT); + LoadStaticRegisters(); + + // Do not violate value in R4 + MOVE(SCRATCH1, R4); + SRAI_W(SCRATCH2, R4, 31); + // Absolute value trick: if neg, abs(x) == (x ^ -1) + 1. + XOR(SCRATCH1, SCRATCH1, SCRATCH2); + SUB_W(SCRATCH1, SCRATCH1, SCRATCH2); + SUB_D(DOWNCOUNTREG, DOWNCOUNTREG, SCRATCH1); + + // R4 might be the mapped reg, but there's only one. + // Set dest reg to the sign of the result. + regs_.Map(inst); + MOVE(regs_.R(inst.dest), SCRATCH2); + break; + + case IROp::Break: + FlushAll(); + // This doesn't naturally have restore/apply around it. + RestoreRoundingMode(true); + SaveStaticRegisters(); + MovFromPC(R4); + QuickCallFunction(&Core_BreakException, SCRATCH2); + LoadStaticRegisters(); + ApplyRoundingMode(true); + MovFromPC(SCRATCH1); + ADDI_D(SCRATCH1, SCRATCH1, 4); + QuickJ(R_RA, dispatcherPCInSCRATCH1_); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_Breakpoint(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Breakpoint: + case IROp::MemoryCheck: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_ValidateAddress(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::ValidateAddress8: + case IROp::ValidateAddress16: + case IROp::ValidateAddress32: + case IROp::ValidateAddress128: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp \ No newline at end of file diff --git a/Core/MIPS/LoongArch64/LoongArch64CompVec.cpp b/Core/MIPS/LoongArch64/LoongArch64CompVec.cpp new file mode 100644 index 0000000000..c11ae9b7e3 --- /dev/null +++ b/Core/MIPS/LoongArch64/LoongArch64CompVec.cpp @@ -0,0 +1,560 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include +#include "Core/MemMap.h" +#include "Core/MIPS/LoongArch64/LoongArch64Jit.h" +#include "Core/MIPS/LoongArch64/LoongArch64RegCache.h" + +// This file contains compilation for vector instructions. +// +// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. +// Currently known non working ones should have DISABLE. No flags because that's in IR already. + +// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; } +#define CONDITIONAL_DISABLE {} +#define DISABLE { CompIR_Generic(inst); return; } +#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; } + +namespace MIPSComp { + +using namespace LoongArch64Gen; +using namespace LoongArch64JitConstants; + +static bool Overlap(IRReg r1, int l1, IRReg r2, int l2) { + return r1 < r2 + l2 && r1 + l1 > r2; +} + +void LoongArch64JitBackend::CompIR_VecAssign(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Vec4Init: + regs_.Map(inst); + + switch ((Vec4Init)inst.src1) { + case Vec4Init::AllZERO: + if (cpu_info.LOONGARCH_LSX) + VREPLGR2VR_D(regs_.V(inst.dest), R_ZERO); + else + for (int i = 0; i < 4; ++i) + MOVGR2FR_W(regs_.F(inst.dest + i), R_ZERO); + break; + + case Vec4Init::AllONE: + LI(SCRATCH1, 1.0f); + if (cpu_info.LOONGARCH_LSX) { + VREPLGR2VR_W(regs_.V(inst.dest), SCRATCH1); + } else { + MOVGR2FR_W(regs_.F(inst.dest), SCRATCH1); + for (int i = 1; i < 4; ++i) + FMOV_S(regs_.F(inst.dest + i), regs_.F(inst.dest)); + } + break; + + case Vec4Init::AllMinusONE: + LI(SCRATCH1, -1.0f); + if (cpu_info.LOONGARCH_LSX) { + VREPLGR2VR_W(regs_.V(inst.dest), SCRATCH1); + } else { + MOVGR2FR_W(regs_.F(inst.dest), SCRATCH1); + for (int i = 1; i < 4; ++i) + FMOV_S(regs_.F(inst.dest + i), regs_.F(inst.dest)); + } + break; + + case Vec4Init::Set_1000: + LI(SCRATCH1, 1.0f); + if (cpu_info.LOONGARCH_LSX) { + VREPLGR2VR_D(regs_.V(inst.dest), R_ZERO); + VINSGR2VR_W(regs_.V(inst.dest), SCRATCH1, 0); + } else { + for (int i = 0; i < 4; ++i) { + if (i == 0) { + MOVGR2FR_W(regs_.F(inst.dest + i), SCRATCH1); + } else { + MOVGR2FR_W(regs_.F(inst.dest + i), R_ZERO); + } + } + } + break; + + case Vec4Init::Set_0100: + LI(SCRATCH1, 1.0f); + if (cpu_info.LOONGARCH_LSX) { + VREPLGR2VR_D(regs_.V(inst.dest), R_ZERO); + VINSGR2VR_W(regs_.V(inst.dest), SCRATCH1, 1); + } else { + for (int i = 0; i < 4; ++i) { + if (i == 1) { + MOVGR2FR_W(regs_.F(inst.dest + i), SCRATCH1); + } else { + MOVGR2FR_W(regs_.F(inst.dest + i), R_ZERO); + } + } + } + break; + + case Vec4Init::Set_0010: + LI(SCRATCH1, 1.0f); + if (cpu_info.LOONGARCH_LSX) { + VREPLGR2VR_D(regs_.V(inst.dest), R_ZERO); + VINSGR2VR_W(regs_.V(inst.dest), SCRATCH1, 2); + } else { + for (int i = 0; i < 4; ++i) { + if (i == 2) { + MOVGR2FR_W(regs_.F(inst.dest + i), SCRATCH1); + } else { + MOVGR2FR_W(regs_.F(inst.dest + i), R_ZERO); + } + } + } + break; + + case Vec4Init::Set_0001: + LI(SCRATCH1, 1.0f); + if (cpu_info.LOONGARCH_LSX) { + VREPLGR2VR_D(regs_.V(inst.dest), R_ZERO); + VINSGR2VR_W(regs_.V(inst.dest), SCRATCH1, 3); + } else { + for (int i = 0; i < 4; ++i) { + if (i == 3) { + MOVGR2FR_W(regs_.F(inst.dest + i), SCRATCH1); + } else { + MOVGR2FR_W(regs_.F(inst.dest + i), R_ZERO); + } + } + } + break; + } + break; + + case IROp::Vec4Shuffle: + if (cpu_info.LOONGARCH_LSX) { + regs_.Map(inst); + if (regs_.GetFPRLaneCount(inst.src1) == 1 && (inst.src1 & 3) == 0 && inst.src2 == 0) { + // This is a broadcast. If dest == src1, this won't clear it. + regs_.SpillLockFPR(inst.src1); + regs_.MapVec4(inst.dest, MIPSMap::NOINIT); + } else { + regs_.Map(inst); + } + + VSHUF4I_W(regs_.V(inst.dest), regs_.V(inst.src1), inst.src2); + } else { + if (inst.dest == inst.src1) { + regs_.Map(inst); + // Try to find the least swaps needed to move in place, never worse than 6 FMOVs. + // Would be better with a vmerge and vector regs. + int state[4]{ 0, 1, 2, 3 }; + int goal[4]{ (inst.src2 >> 0) & 3, (inst.src2 >> 2) & 3, (inst.src2 >> 4) & 3, (inst.src2 >> 6) & 3 }; + + static constexpr int NOT_FOUND = 4; + auto findIndex = [](int *arr, int val, int start = 0) { + return (int)(std::find(arr + start, arr + 4, val) - arr); + }; + auto moveChained = [&](const std::vector &lanes, bool rotate) { + int firstState = state[lanes.front()]; + if (rotate) + FMOV_S(SCRATCHF1, regs_.F(inst.dest + lanes.front())); + for (size_t i = 1; i < lanes.size(); ++i) { + FMOV_S(regs_.F(inst.dest + lanes[i - 1]), regs_.F(inst.dest + lanes[i])); + state[lanes[i - 1]] = state[lanes[i]]; + } + if (rotate) { + FMOV_S(regs_.F(inst.dest + lanes.back()), SCRATCHF1); + state[lanes.back()] = firstState; + } + }; + + for (int i = 0; i < 4; ++i) { + // Overlap, so if they match, nothing to do. + if (goal[i] == state[i]) + continue; + + int neededBy = findIndex(goal, state[i], i + 1); + int foundIn = findIndex(state, goal[i], 0); + _assert_(foundIn != NOT_FOUND); + + if (neededBy == NOT_FOUND || neededBy == foundIn) { + moveChained({ i, foundIn }, neededBy == foundIn); + continue; + } + + // Maybe we can avoid a swap and move the next thing into place. + int neededByDepth2 = findIndex(goal, state[neededBy], i + 1); + if (neededByDepth2 == NOT_FOUND || neededByDepth2 == foundIn) { + moveChained({ neededBy, i, foundIn }, neededByDepth2 == foundIn); + continue; + } + + // Since we only have 4 items, this is as deep as the chain could go. + int neededByDepth3 = findIndex(goal, state[neededByDepth2], i + 1); + moveChained({ neededByDepth2, neededBy, i, foundIn }, neededByDepth3 == foundIn); + } + } else { + regs_.Map(inst); + for (int i = 0; i < 4; ++i) { + int lane = (inst.src2 >> (i * 2)) & 3; + FMOV_S(regs_.F(inst.dest + i), regs_.F(inst.src1 + lane)); + } + } + } + break; + + case IROp::Vec4Blend: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) { + LoongArch64Reg src = regs_.V(inst.src1);; + uint8_t imm = inst.constant; + if (inst.dest == inst.src1) + src = regs_.V(inst.src2); + else if (inst.dest == inst.src2) + imm = ~imm; + else + VOR_V(regs_.V(inst.dest), src, src); + + for (int i = 0; i < 4; ++i) + if (imm & (1 << i)) { + VEXTRINS_W(regs_.V(inst.dest), src, (i << 4) | i); + } + } else { + for (int i = 0; i < 4; ++i) { + int which = (inst.constant >> i) & 1; + IRReg srcReg = which ? inst.src2 : inst.src1; + if (inst.dest != srcReg) + FMOV_S(regs_.F(inst.dest + i), regs_.F(srcReg + i)); + } + } + break; + + case IROp::Vec4Mov: + if (inst.dest != inst.src1) { + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) + VOR_V(regs_.V(inst.dest), regs_.V(inst.src1), regs_.V(inst.src1)); + else + for (int i = 0; i < 4; ++i) + FMOV_S(regs_.F(inst.dest + i), regs_.F(inst.src1 + i)); + } + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_VecArith(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Vec4Add: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) + VFADD_S(regs_.V(inst.dest), regs_.V(inst.src1), regs_.V(inst.src2)); + else + for (int i = 0; i < 4; ++i) + FADD_S(regs_.F(inst.dest + i), regs_.F(inst.src1 + i), regs_.F(inst.src2 + i)); + break; + + case IROp::Vec4Sub: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) + VFSUB_S(regs_.V(inst.dest), regs_.V(inst.src1), regs_.V(inst.src2)); + else + for (int i = 0; i < 4; ++i) + FSUB_S(regs_.F(inst.dest + i), regs_.F(inst.src1 + i), regs_.F(inst.src2 + i)); + break; + + case IROp::Vec4Mul: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) + VFMUL_S(regs_.V(inst.dest), regs_.V(inst.src1), regs_.V(inst.src2)); + else + for (int i = 0; i < 4; ++i) + FMUL_S(regs_.F(inst.dest + i), regs_.F(inst.src1 + i), regs_.F(inst.src2 + i)); + break; + + case IROp::Vec4Div: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) + VFDIV_S(regs_.V(inst.dest), regs_.V(inst.src1), regs_.V(inst.src2)); + else + for (int i = 0; i < 4; ++i) + FDIV_S(regs_.F(inst.dest + i), regs_.F(inst.src1 + i), regs_.F(inst.src2 + i)); + break; + + case IROp::Vec4Scale: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) { + if (Overlap(inst.dest, 4, inst.src2, 1) || Overlap(inst.src1, 4, inst.src2, 1)) + DISABLE; + + VSHUF4I_W(regs_.V(inst.src2), regs_.V(inst.src2), 0); + VFMUL_S(regs_.V(inst.dest), regs_.V(inst.src1), regs_.V(inst.src2)); + } else { + if (Overlap(inst.src2, 1, inst.dest, 3)) { + // We have to handle overlap, doing dest == src2 last. + for (int i = 0; i < 4; ++i) { + if (inst.src2 != inst.dest + i) + FMUL_S(regs_.F(inst.dest + i), regs_.F(inst.src1 + i), regs_.F(inst.src2)); + } + for (int i = 0; i < 4; ++i) { + if (inst.src2 == inst.dest + i) + FMUL_S(regs_.F(inst.dest + i), regs_.F(inst.src1 + i), regs_.F(inst.src2)); + } + } else { + for (int i = 0; i < 4; ++i) + FMUL_S(regs_.F(inst.dest + i), regs_.F(inst.src1 + i), regs_.F(inst.src2)); + } + } + break; + + case IROp::Vec4Neg: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) + VBITREVI_W(regs_.V(inst.dest), regs_.V(inst.src1), 31); + else + for (int i = 0; i < 4; ++i) + FNEG_S(regs_.F(inst.dest + i), regs_.F(inst.src1 + i)); + break; + + case IROp::Vec4Abs: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) + VBITSETI_W(regs_.V(inst.dest), regs_.V(inst.src1), 31); + else + for (int i = 0; i < 4; ++i) + FABS_S(regs_.F(inst.dest + i), regs_.F(inst.src1 + i)); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_VecHoriz(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Vec4Dot: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) { + if (Overlap(inst.dest, 1, inst.src1, 4) || Overlap(inst.dest, 1, inst.src2, 4)) + DISABLE; + + VFMUL_S(regs_.V(inst.dest), regs_.V(inst.src1), regs_.V(inst.src2)); + VOR_V(EncodeRegToV(SCRATCHF1), regs_.V(inst.dest), regs_.V(inst.dest)); + VSHUF4I_W(EncodeRegToV(SCRATCHF1), regs_.V(inst.dest), VFPU_SWIZZLE(1, 0, 3, 2)); + VFADD_S(regs_.V(inst.dest), regs_.V(inst.dest), EncodeRegToV(SCRATCHF1)); + VEXTRINS_D(EncodeRegToV(SCRATCHF1), regs_.V(inst.dest), 1); + // Do we need care about upper 96 bits? + VFADD_S(regs_.V(inst.dest), regs_.V(inst.dest), EncodeRegToV(SCRATCHF1)); + } else { + if (Overlap(inst.dest, 1, inst.src1, 4) || Overlap(inst.dest, 1, inst.src2, 4)) { + // This means inst.dest overlaps one of src1 or src2. We have to do that one first. + // Technically this may impact -0.0 and such, but dots accurately need to be aligned anyway. + for (int i = 0; i < 4; ++i) { + if (inst.dest == inst.src1 + i || inst.dest == inst.src2 + i) + FMUL_S(regs_.F(inst.dest), regs_.F(inst.src1 + i), regs_.F(inst.src2 + i)); + } + for (int i = 0; i < 4; ++i) { + if (inst.dest != inst.src1 + i && inst.dest != inst.src2 + i) + FMADD_S(regs_.F(inst.dest), regs_.F(inst.src1 + i), regs_.F(inst.src2 + i), regs_.F(inst.dest)); + } + } else { + FMUL_S(regs_.F(inst.dest), regs_.F(inst.src1), regs_.F(inst.src2)); + for (int i = 1; i < 4; ++i) + FMADD_S(regs_.F(inst.dest), regs_.F(inst.src1 + i), regs_.F(inst.src2 + i), regs_.F(inst.dest)); + } + } + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_VecPack(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Vec2Unpack16To31: + case IROp::Vec2Pack31To16: + CompIR_Generic(inst); + break; + + case IROp::Vec4Pack32To8: + if (cpu_info.LOONGARCH_LSX) { + regs_.Map(inst); + if (Overlap(inst.dest, 1, inst.src1, 4)) + DISABLE; + + VSRLI_W(EncodeRegToV(SCRATCHF1), regs_.V(inst.src1), 23); + VPICKEV_B(EncodeRegToV(SCRATCHF1), EncodeRegToV(SCRATCHF1), EncodeRegToV(SCRATCHF1)); + VPICKEV_B(regs_.V(inst.dest), EncodeRegToV(SCRATCHF1), EncodeRegToV(SCRATCHF1)); + } else { + CompIR_Generic(inst); + } + break; + + case IROp::Vec4Unpack8To32: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) { + if (Overlap(inst.dest, 1, inst.src1, 4)) + DISABLE; + + VSLLWIL_HU_BU(regs_.V(inst.dest), regs_.V(inst.src1), 0); + VSLLWIL_WU_HU(regs_.V(inst.dest), regs_.V(inst.dest), 0); + } else { + MOVFR2GR_S(SCRATCH2, regs_.F(inst.src1)); + for (int i = 0; i < 4; ++i) { + // Mask using walls. + if (i != 0) { + SRLI_D(SCRATCH1, SCRATCH2, i * 8); + SLLI_D(SCRATCH1, SCRATCH1, 24); + } else { + SLLI_D(SCRATCH1, SCRATCH2, 24); + } + MOVGR2FR_W(regs_.F(inst.dest + i), SCRATCH1); + } + } + break; + + case IROp::Vec2Unpack16To32: + // TODO: This works for now, but may need to handle aliasing for vectors. + if (cpu_info.LOONGARCH_LSX) { + CompIR_Generic(inst); + break; + } + regs_.Map(inst); + MOVFR2GR_S(SCRATCH2, regs_.F(inst.src1)); + SLLI_D(SCRATCH1, SCRATCH2, 16); + MOVGR2FR_W(regs_.F(inst.dest), SCRATCH1); + SRLI_D(SCRATCH1, SCRATCH2, 16); + SLLI_D(SCRATCH1, SCRATCH1, 16); + MOVGR2FR_W(regs_.F(inst.dest + 1), SCRATCH1); + break; + + case IROp::Vec4DuplicateUpperBitsAndShift1: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) { + VSRLI_W(EncodeRegToV(SCRATCHF1), regs_.V(inst.src1), 16); + VOR_V(EncodeRegToV(SCRATCHF1), EncodeRegToV(SCRATCHF1), regs_.V(inst.src1)); + VSRLI_W(regs_.V(inst.dest), EncodeRegToV(SCRATCHF1), 8); + VOR_V(regs_.V(inst.dest), regs_.V(inst.dest), EncodeRegToV(SCRATCHF1)); + VSRLI_W(regs_.V(inst.dest), regs_.V(inst.dest), 1); + } else { + for (int i = 0; i < 4; i++) { + MOVFR2GR_S(SCRATCH1, regs_.F(inst.src1 + i)); + SRLI_W(SCRATCH2, SCRATCH1, 8); + OR(SCRATCH1, SCRATCH1, SCRATCH2); + SRLI_W(SCRATCH2, SCRATCH1, 16); + OR(SCRATCH1, SCRATCH1, SCRATCH2); + SRLI_W(SCRATCH1, SCRATCH1, 1); + MOVGR2FR_W(regs_.F(inst.dest + i), SCRATCH1); + } + } + break; + + case IROp::Vec4Pack31To8: + // TODO: This works for now, but may need to handle aliasing for vectors. + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) { + if (Overlap(inst.dest, 1, inst.src1, 4)) + DISABLE; + + VSRLI_W(EncodeRegToV(SCRATCHF1), regs_.V(inst.src1), 23); + VPICKEV_B(EncodeRegToV(SCRATCHF1), EncodeRegToV(SCRATCHF1), EncodeRegToV(SCRATCHF1)); + VPICKEV_B(regs_.V(inst.dest), EncodeRegToV(SCRATCHF1), EncodeRegToV(SCRATCHF1)); + }else { + for (int i = 0; i < 4; ++i) { + MOVFR2GR_S(SCRATCH1, regs_.F(inst.src1 + i)); + SRLI_D(SCRATCH1, SCRATCH1, 23); + if (i == 0) { + ANDI(SCRATCH2, SCRATCH1, 0xFF); + } else { + ANDI(SCRATCH1, SCRATCH1, 0xFF); + SLLI_D(SCRATCH1, SCRATCH1, 8 * i); + OR(SCRATCH2, SCRATCH2, SCRATCH1); + } + } + MOVGR2FR_W(regs_.F(inst.dest), SCRATCH2); + } + break; + + case IROp::Vec2Pack32To16: + // TODO: This works for now, but may need to handle aliasing for vectors. + if (cpu_info.LOONGARCH_LSX) { + CompIR_Generic(inst); + break; + } + regs_.Map(inst); + MOVFR2GR_S(SCRATCH1, regs_.F(inst.src1)); + MOVFR2GR_S(SCRATCH2, regs_.F(inst.src1 + 1)); + // Keep in mind, this was sign-extended, so we have to zero the upper. + SLLI_D(SCRATCH1, SCRATCH1, 32); + // Now we just set (SCRATCH2 & 0xFFFF0000) | SCRATCH1. + SRLI_D(SCRATCH1, SCRATCH1, 48); + // Use a wall to mask. We can ignore the upper 32 here. + SRLI_D(SCRATCH2, SCRATCH2, 16); + SLLI_D(SCRATCH2, SCRATCH2, 16); + OR(SCRATCH1, SCRATCH1, SCRATCH2); + // Okay, to the floating point register. + MOVGR2FR_W(regs_.F(inst.dest), SCRATCH1); + break; + + default: + INVALIDOP; + break; + } +} + +void LoongArch64JitBackend::CompIR_VecClamp(IRInst inst) { + CONDITIONAL_DISABLE; + + switch (inst.op) { + case IROp::Vec4ClampToZero: + regs_.Map(inst); + if (cpu_info.LOONGARCH_LSX) { + VREPLGR2VR_D(EncodeRegToV(SCRATCHF1), R_ZERO); + VMAX_W(regs_.V(inst.dest), regs_.V(inst.src1), EncodeRegToV(SCRATCHF1)); + } else { + for (int i = 0; i < 4; i++) { + MOVFR2GR_S(SCRATCH1, regs_.F(inst.src1 + i)); + SRAI_W(SCRATCH2, SCRATCH1, 31); + ORN(SCRATCH2, R_ZERO, SCRATCH2); + AND(SCRATCH1, SCRATCH1, SCRATCH2); + MOVGR2FR_W(regs_.F(inst.dest + i), SCRATCH1); + } + } + break; + + case IROp::Vec2ClampToZero: + CompIR_Generic(inst); + break; + + default: + INVALIDOP; + break; + } +} + +} // namespace MIPSComp diff --git a/Core/MIPS/LoongArch64/LoongArch64Jit.cpp b/Core/MIPS/LoongArch64/LoongArch64Jit.cpp new file mode 100644 index 0000000000..cbb5869573 --- /dev/null +++ b/Core/MIPS/LoongArch64/LoongArch64Jit.cpp @@ -0,0 +1,411 @@ +// Copyright (c) 2025- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include +#include "Core/MemMap.h" +#include "Core/MIPS/MIPSTables.h" +#include "Core/MIPS/LoongArch64/LoongArch64Jit.h" +#include "Core/MIPS/LoongArch64/LoongArch64RegCache.h" + +#include +// for std::min + +namespace MIPSComp { + +using namespace LoongArch64Gen; +using namespace LoongArch64JitConstants; + +// Needs space for a LI and J which might both be 32-bit offsets. +static constexpr int MIN_BLOCK_NORMAL_LEN = 16; +static constexpr int MIN_BLOCK_EXIT_LEN = 8; + +LoongArch64JitBackend::LoongArch64JitBackend(JitOptions &jitopt, IRBlockCache &blocks) + : IRNativeBackend(blocks), jo(jitopt), regs_(&jo) { + // Automatically disable incompatible options. + if (((intptr_t)Memory::base & 0x00000000FFFFFFFFUL) != 0) { + jo.enablePointerify = false; + } + jo.optimizeForInterpreter = false; + + // Since we store the offset, this is as big as it can be. + // We could shift off one bit to double it, would need to change LoongArch64Asm. + AllocCodeSpace(1024 * 1024 * 16); + + regs_.Init(this); +} + +LoongArch64JitBackend::~LoongArch64JitBackend(){ +} + +static void NoBlockExits() { + _assert_msg_(false, "Never exited block, invalid IR?"); +} + +bool LoongArch64JitBackend::CompileBlock(IRBlockCache *irBlockCache, int block_num) { + if (GetSpaceLeft() < 0x800) + return false; + + IRBlock *block = irBlockCache->GetBlock(block_num); + BeginWrite(std::min(GetSpaceLeft(), (size_t)block->GetNumIRInstructions() * 32)); + + u32 startPC = block->GetOriginalStart(); + bool wroteCheckedOffset = false; + if (jo.enableBlocklink && !jo.useBackJump) { + SetBlockCheckedOffset(block_num, (int)GetOffset(GetCodePointer())); + wroteCheckedOffset = true; + + WriteDebugPC(startPC); + + FixupBranch normalEntry = BGE(DOWNCOUNTREG, R_ZERO); + LI(SCRATCH1, startPC); + QuickJ(R_RA, outerLoopPCInSCRATCH1_); + SetJumpTarget(normalEntry); + } + + // Don't worry, the codespace isn't large enough to overflow offsets. + const u8 *blockStart = GetCodePointer(); + block->SetNativeOffset((int)GetOffset(blockStart)); + compilingBlockNum_ = block_num; + + regs_.Start(irBlockCache, block_num); + + std::vector addresses; + const IRInst *instructions = irBlockCache->GetBlockInstructionPtr(*block); + for (int i = 0; i < block->GetNumIRInstructions(); ++i) { + const IRInst &inst = instructions[i]; + regs_.SetIRIndex(i); + addresses.push_back(GetCodePtr()); + + CompileIRInst(inst); + + if (jo.Disabled(JitDisable::REGALLOC_GPR) || jo.Disabled(JitDisable::REGALLOC_FPR)) + regs_.FlushAll(jo.Disabled(JitDisable::REGALLOC_GPR), jo.Disabled(JitDisable::REGALLOC_FPR)); + + // Safety check, in case we get a bunch of really large jit ops without a lot of branching. + if (GetSpaceLeft() < 0x800) { + compilingBlockNum_ = -1; + return false; + } + } + + // We should've written an exit above. If we didn't, bad things will happen. + // Only check if debug stats are enabled - needlessly wastes jit space. + if (DebugStatsEnabled()) { + QuickCallFunction(&NoBlockExits, SCRATCH2); + QuickJ(R_RA, hooks_.crashHandler); + } + + int len = (int)GetOffset(GetCodePointer()) - block->GetNativeOffset(); + if (len < MIN_BLOCK_NORMAL_LEN) { + // We need at least 16 bytes to invalidate blocks with, but larger doesn't need to align. + ReserveCodeSpace(MIN_BLOCK_NORMAL_LEN - len); + } + + if (!wroteCheckedOffset) { + // Always record this, even if block link disabled - it's used for size calc. + SetBlockCheckedOffset(block_num, (int)GetOffset(GetCodePointer())); + } + + if (jo.enableBlocklink && jo.useBackJump) { + WriteDebugPC(startPC); + + // Most blocks shouldn't be >= 256KB, so usually we can just BGE. + if (BranchInRange(blockStart)) { + BGE(DOWNCOUNTREG, R_ZERO, blockStart); + } else { + FixupBranch skip = BLT(DOWNCOUNTREG, R_ZERO); + B(blockStart); + SetJumpTarget(skip); + } + LI(SCRATCH1, startPC); + QuickJ(R_RA, outerLoopPCInSCRATCH1_); + } + + if (logBlocks_ > 0) { + --logBlocks_; + + std::map addressesLookup; + for (int i = 0; i < (int)addresses.size(); ++i) + addressesLookup[addresses[i]] = i; + + INFO_LOG(Log::JIT, "=============== LoongArch64 (%08x, %d bytes) ===============", startPC, len); + const IRInst *instructions = irBlockCache->GetBlockInstructionPtr(*block); + for (const u8 *p = blockStart; p < GetCodePointer(); ) { + auto it = addressesLookup.find(p); + if (it != addressesLookup.end()) { + const IRInst &inst = instructions[it->second]; + + char temp[512]; + DisassembleIR(temp, sizeof(temp), inst); + INFO_LOG(Log::JIT, "IR: #%d %s", it->second, temp); + } + + auto next = std::next(it); + const u8 *nextp = next == addressesLookup.end() ? GetCodePointer() : next->first; + +#if PPSSPP_ARCH(LOONGARCH64) + auto lines = DisassembleLA64(p, (int)(nextp - p)); + for (const auto &line : lines) + INFO_LOG(Log::JIT, "LA: %s", line.c_str()); +#endif + p = nextp; + } + } + + EndWrite(); + FlushIcache(); + compilingBlockNum_ = -1; + + return true; +} + +void LoongArch64JitBackend::WriteConstExit(uint32_t pc) { + int block_num = blocks_.GetBlockNumberFromStartAddress(pc); + const IRNativeBlock *nativeBlock = GetNativeBlock(block_num); + + int exitStart = (int)GetOffset(GetCodePointer()); + if (block_num >= 0 && jo.enableBlocklink && nativeBlock && nativeBlock->checkedOffset != 0) { + QuickJ(SCRATCH1, GetBasePtr() + nativeBlock->checkedOffset); + } else { + LI(SCRATCH1, pc); + QuickJ(R_RA, dispatcherPCInSCRATCH1_); + } + + if (jo.enableBlocklink) { + // In case of compression or early link, make sure it's large enough. + int len = (int)GetOffset(GetCodePointer()) - exitStart; + if (len < MIN_BLOCK_EXIT_LEN) { + ReserveCodeSpace(MIN_BLOCK_EXIT_LEN - len); + len = MIN_BLOCK_EXIT_LEN; + } + + AddLinkableExit(compilingBlockNum_, pc, exitStart, len); + } +} + +void LoongArch64JitBackend::OverwriteExit(int srcOffset, int len, int block_num) { + _dbg_assert_(len >= MIN_BLOCK_EXIT_LEN); + + const IRNativeBlock *nativeBlock = GetNativeBlock(block_num); + if (nativeBlock) { + u8 *writable = GetWritablePtrFromCodePtr(GetBasePtr()) + srcOffset; + if (PlatformIsWXExclusive()) { + ProtectMemoryPages(writable, len, MEM_PROT_READ | MEM_PROT_WRITE); + } + + LoongArch64Emitter emitter(GetBasePtr() + srcOffset, writable); + emitter.QuickJ(SCRATCH1, GetBasePtr() + nativeBlock->checkedOffset); + int bytesWritten = (int)(emitter.GetWritableCodePtr() - writable); + if (bytesWritten < len) + emitter.ReserveCodeSpace(len - bytesWritten); + emitter.FlushIcache(); + + if (PlatformIsWXExclusive()) { + ProtectMemoryPages(writable, 16, MEM_PROT_READ | MEM_PROT_EXEC); + } + } +} + +void LoongArch64JitBackend::CompIR_Generic(IRInst inst) { + // If we got here, we're going the slow way. + uint64_t value; + memcpy(&value, &inst, sizeof(inst)); + + FlushAll(); + LI(R4, value); + SaveStaticRegisters(); + WriteDebugProfilerStatus(IRProfilerStatus::IR_INTERPRET); + QuickCallFunction(&DoIRInst, SCRATCH2); + WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT); + LoadStaticRegisters(); + + // We only need to check the return value if it's a potential exit. + if ((GetIRMeta(inst.op)->flags & IRFLAG_EXIT) != 0) { + MOVE(SCRATCH1, R4); + + if (BranchZeroInRange(dispatcherPCInSCRATCH1_)) { + BNEZ(R4, dispatcherPCInSCRATCH1_); + } else { + FixupBranch skip = BEQZ(R4); + QuickJ(R_RA, dispatcherPCInSCRATCH1_); + SetJumpTarget(skip); + } + } +} + +void LoongArch64JitBackend::CompIR_Interpret(IRInst inst) { + MIPSOpcode op(inst.constant); + + // IR protects us against this being a branching instruction (well, hopefully.) + FlushAll(); + SaveStaticRegisters(); + WriteDebugProfilerStatus(IRProfilerStatus::INTERPRET); + if (DebugStatsEnabled()) { + LI(R4, MIPSGetName(op)); + QuickCallFunction(&NotifyMIPSInterpret, SCRATCH2); + } + LI(R4, (int32_t)inst.constant); + QuickCallFunction((const u8 *)MIPSGetInterpretFunc(op), SCRATCH2); + WriteDebugProfilerStatus(IRProfilerStatus::IN_JIT); + LoadStaticRegisters(); +} + +void LoongArch64JitBackend::FlushAll() { + regs_.FlushAll(); +} + +bool LoongArch64JitBackend::DescribeCodePtr(const u8 *ptr, std::string &name) const { + // Used in disassembly viewer. + // Don't use spaces; profilers get confused or truncate them. + if (ptr == dispatcherPCInSCRATCH1_) { + name = "dispatcherPCInSCRATCH1"; + } else if (ptr == outerLoopPCInSCRATCH1_) { + name = "outerLoopPCInSCRATCH1"; + } else if (ptr == dispatcherNoCheck_) { + name = "dispatcherNoCheck"; + } else if (ptr == saveStaticRegisters_) { + name = "saveStaticRegisters"; + } else if (ptr == loadStaticRegisters_) { + name = "loadStaticRegisters"; + } else if (ptr == applyRoundingMode_) { + name = "applyRoundingMode"; + } else if (ptr >= GetBasePtr() && ptr < GetBasePtr() + jitStartOffset_) { + name = "fixedCode"; + } else { + return IRNativeBackend::DescribeCodePtr(ptr, name); + } + return true; +} + +void LoongArch64JitBackend::ClearAllBlocks() { + ClearCodeSpace(jitStartOffset_); + FlushIcacheSection(region + jitStartOffset_, region + region_size - jitStartOffset_); + EraseAllLinks(-1); +} + +void LoongArch64JitBackend::InvalidateBlock(IRBlockCache *irBlockCache, int block_num) { + IRBlock *block = irBlockCache->GetBlock(block_num); + int offset = block->GetNativeOffset(); + u8 *writable = GetWritablePtrFromCodePtr(GetBasePtr()) + offset; + + // Overwrite the block with a jump to compile it again. + u32 pc = block->GetOriginalStart(); + if (pc != 0) { + // Hopefully we always have at least 16 bytes, which should be all we need. + if (PlatformIsWXExclusive()) { + ProtectMemoryPages(writable, MIN_BLOCK_NORMAL_LEN, MEM_PROT_READ | MEM_PROT_WRITE); + } + + LoongArch64Emitter emitter(GetBasePtr() + offset, writable); + // We sign extend to ensure it will fit in 32-bit and 8 bytes LI. + // TODO: May need to change if dispatcher doesn't reload PC. + emitter.LI(SCRATCH1, (int32_t)pc); + emitter.QuickJ(R_RA, dispatcherPCInSCRATCH1_); + int bytesWritten = (int)(emitter.GetWritableCodePtr() - writable); + if (bytesWritten < MIN_BLOCK_NORMAL_LEN) + emitter.ReserveCodeSpace(MIN_BLOCK_NORMAL_LEN - bytesWritten); + emitter.FlushIcache(); + + if (PlatformIsWXExclusive()) { + ProtectMemoryPages(writable, MIN_BLOCK_NORMAL_LEN, MEM_PROT_READ | MEM_PROT_EXEC); + } + } + + EraseAllLinks(block_num); +} + +void LoongArch64JitBackend::RestoreRoundingMode(bool force) { + MOVGR2FCSR(FCSR3, R_ZERO); // 0 = RNE - Round Nearest Even +} + +void LoongArch64JitBackend::ApplyRoundingMode(bool force) { + QuickCallFunction(applyRoundingMode_); +} + +void LoongArch64JitBackend::MovFromPC(LoongArch64Reg r) { + LD_WU(r, CTXREG, offsetof(MIPSState, pc)); +} + +void LoongArch64JitBackend::MovToPC(LoongArch64Reg r) { + ST_W(r, CTXREG, offsetof(MIPSState, pc)); +} + +void LoongArch64JitBackend::WriteDebugPC(uint32_t pc) { + if (hooks_.profilerPC) { + int offset = (const u8 *)hooks_.profilerPC - GetBasePtr(); + LI(SCRATCH2, hooks_.profilerPC); + LI(R_RA, (int32_t)pc); + ST_W(R_RA, SCRATCH2, 0); + } +} + +void LoongArch64JitBackend::WriteDebugPC(LoongArch64Reg r) { + if (hooks_.profilerPC) { + int offset = (const u8 *)hooks_.profilerPC - GetBasePtr(); + LI(SCRATCH2, hooks_.profilerPC); + ST_W(r, SCRATCH2, 0); + } +} + +void LoongArch64JitBackend::WriteDebugProfilerStatus(IRProfilerStatus status) { + if (hooks_.profilerPC) { + int offset = (const u8 *)hooks_.profilerStatus - GetBasePtr(); + LI(SCRATCH2, hooks_.profilerStatus); + LI(R_RA, (int)status); + ST_W(R_RA, SCRATCH2, 0); + } +} + +void LoongArch64JitBackend::SaveStaticRegisters() { + if (jo.useStaticAlloc) { + QuickCallFunction(saveStaticRegisters_); + } else { + // Inline the single operation + ST_W(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount)); + } +} + +void LoongArch64JitBackend::LoadStaticRegisters() { + if (jo.useStaticAlloc) { + QuickCallFunction(loadStaticRegisters_); + } else { + LD_W(DOWNCOUNTREG, CTXREG, offsetof(MIPSState, downcount)); + } +} + +void LoongArch64JitBackend::NormalizeSrc1(IRInst inst, LoongArch64Reg *reg, LoongArch64Reg tempReg, bool allowOverlap) { + *reg = NormalizeR(inst.src1, allowOverlap ? 0 : inst.dest, tempReg); +} + +void LoongArch64JitBackend::NormalizeSrc12(IRInst inst, LoongArch64Reg *lhs, LoongArch64Reg *rhs, LoongArch64Reg lhsTempReg, LoongArch64Reg rhsTempReg, bool allowOverlap) { + *lhs = NormalizeR(inst.src1, allowOverlap ? 0 : inst.dest, lhsTempReg); + *rhs = NormalizeR(inst.src2, allowOverlap ? 0 : inst.dest, rhsTempReg); +} + +LoongArch64Reg LoongArch64JitBackend::NormalizeR(IRReg rs, IRReg rd, LoongArch64Reg tempReg) { + // For proper compare, we must sign extend so they both match or don't match. + // But don't change pointers, in case one is SP (happens in LittleBigPlanet.) + if (regs_.IsGPRImm(rs) && regs_.GetGPRImm(rs) == 0) { + return R_ZERO; + } else if (regs_.IsGPRMappedAsPointer(rs) || rs == rd) { + return regs_.Normalize32(rs, tempReg); + } else { + return regs_.Normalize32(rs); + } +} + +} // namespace MIPSComp \ No newline at end of file diff --git a/Core/MIPS/LoongArch64/LoongArch64Jit.h b/Core/MIPS/LoongArch64/LoongArch64Jit.h new file mode 100644 index 0000000000..15224f0a89 --- /dev/null +++ b/Core/MIPS/LoongArch64/LoongArch64Jit.h @@ -0,0 +1,142 @@ +// Copyright (c) 2025- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#pragma once + +#include +#include +#include "Common/LoongArch64Emitter.h" +#include "Core/MIPS/IR/IRJit.h" +#include "Core/MIPS/IR/IRNativeCommon.h" +#include "Core/MIPS/JitCommon/JitState.h" +#include "Core/MIPS/JitCommon/JitCommon.h" +#include "Core/MIPS/LoongArch64/LoongArch64RegCache.h" + +namespace MIPSComp { + +class LoongArch64JitBackend : public LoongArch64Gen::LoongArch64CodeBlock, public IRNativeBackend { +public: + LoongArch64JitBackend(JitOptions &jo, IRBlockCache &blocks); + ~LoongArch64JitBackend(); + + bool DescribeCodePtr(const u8 *ptr, std::string &name) const override; + + void GenerateFixedCode(MIPSState *mipsState) override; + bool CompileBlock(IRBlockCache *irBlockCache, int block_num) override; + void ClearAllBlocks() override; + void InvalidateBlock(IRBlockCache *irBlockCache, int block_num) override; + +protected: + const CodeBlockCommon &CodeBlock() const override { + return *this; + } +private: + void RestoreRoundingMode(bool force = false); + void ApplyRoundingMode(bool force = false); + void MovFromPC(LoongArch64Gen::LoongArch64Reg r); + void MovToPC(LoongArch64Gen::LoongArch64Reg r); + void WriteDebugPC(uint32_t pc); + void WriteDebugPC(LoongArch64Gen::LoongArch64Reg r); + void WriteDebugProfilerStatus(IRProfilerStatus status); + + void SaveStaticRegisters(); + void LoadStaticRegisters(); + + // Note: destroys SCRATCH1. + void FlushAll(); + + void WriteConstExit(uint32_t pc); + void OverwriteExit(int srcOffset, int len, int block_num) override; + + void CompIR_Arith(IRInst inst) override; + void CompIR_Assign(IRInst inst) override; + void CompIR_Basic(IRInst inst) override; + void CompIR_Bits(IRInst inst) override; + void CompIR_Breakpoint(IRInst inst) override; + void CompIR_Compare(IRInst inst) override; + void CompIR_CondAssign(IRInst inst) override; + void CompIR_CondStore(IRInst inst) override; + void CompIR_Div(IRInst inst) override; + void CompIR_Exit(IRInst inst) override; + void CompIR_ExitIf(IRInst inst) override; + void CompIR_FArith(IRInst inst) override; + void CompIR_FAssign(IRInst inst) override; + void CompIR_FCompare(IRInst inst) override; + void CompIR_FCondAssign(IRInst inst) override; + void CompIR_FCvt(IRInst inst) override; + void CompIR_FLoad(IRInst inst) override; + void CompIR_FRound(IRInst inst) override; + void CompIR_FSat(IRInst inst) override; + void CompIR_FSpecial(IRInst inst) override; + void CompIR_FStore(IRInst inst) override; + void CompIR_Generic(IRInst inst) override; + void CompIR_HiLo(IRInst inst) override; + void CompIR_Interpret(IRInst inst) override; + void CompIR_Load(IRInst inst) override; + void CompIR_LoadShift(IRInst inst) override; + void CompIR_Logic(IRInst inst) override; + void CompIR_Mult(IRInst inst) override; + void CompIR_RoundingMode(IRInst inst) override; + void CompIR_Shift(IRInst inst) override; + void CompIR_Store(IRInst inst) override; + void CompIR_StoreShift(IRInst inst) override; + void CompIR_System(IRInst inst) override; + void CompIR_Transfer(IRInst inst) override; + void CompIR_VecArith(IRInst inst) override; + void CompIR_VecAssign(IRInst inst) override; + void CompIR_VecClamp(IRInst inst) override; + void CompIR_VecHoriz(IRInst inst) override; + void CompIR_VecLoad(IRInst inst) override; + void CompIR_VecPack(IRInst inst) override; + void CompIR_VecStore(IRInst inst) override; + void CompIR_ValidateAddress(IRInst inst) override; + + void SetScratch1ToSrc1Address(IRReg src1); + // Modifies SCRATCH regs. + int32_t AdjustForAddressOffset(LoongArch64Gen::LoongArch64Reg *reg, int32_t constant, int32_t range = 0); + void NormalizeSrc1(IRInst inst, LoongArch64Gen::LoongArch64Reg *reg, LoongArch64Gen::LoongArch64Reg tempReg, bool allowOverlap); + void NormalizeSrc12(IRInst inst, LoongArch64Gen::LoongArch64Reg *lhs, LoongArch64Gen::LoongArch64Reg *rhs, LoongArch64Gen::LoongArch64Reg lhsTempReg, LoongArch64Gen::LoongArch64Reg rhsTempReg, bool allowOverlap); + LoongArch64Gen::LoongArch64Reg NormalizeR(IRReg rs, IRReg rd, LoongArch64Gen::LoongArch64Reg tempReg); + + JitOptions &jo; + LoongArch64RegCache regs_; + + const u8 *outerLoop_ = nullptr; + const u8 *outerLoopPCInSCRATCH1_ = nullptr; + const u8 *dispatcherCheckCoreState_ = nullptr; + const u8 *dispatcherPCInSCRATCH1_ = nullptr; + const u8 *dispatcherNoCheck_ = nullptr; + const u8 *applyRoundingMode_ = nullptr; + + const u8 *saveStaticRegisters_ = nullptr; + const u8 *loadStaticRegisters_ = nullptr; + + int jitStartOffset_ = 0; + int compilingBlockNum_ = -1; + int logBlocks_ = 0; +}; + +class LoongArch64Jit : public IRNativeJit{ +public: + LoongArch64Jit(MIPSState *mipsState) : IRNativeJit(mipsState), la64Backend_(jo, blocks_) { + Init(la64Backend_); + } +private: + LoongArch64JitBackend la64Backend_; +}; + +} // namespace MIPSComp \ No newline at end of file diff --git a/Core/MIPS/LoongArch64/LoongArch64RegCache.cpp b/Core/MIPS/LoongArch64/LoongArch64RegCache.cpp new file mode 100644 index 0000000000..d62b53ad9d --- /dev/null +++ b/Core/MIPS/LoongArch64/LoongArch64RegCache.cpp @@ -0,0 +1,721 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#ifndef offsetof +#include +#endif + +#include "Common/CPUDetect.h" +#include "Core/MIPS/IR/IRInst.h" +#include "Core/MIPS/IR/IRAnalysis.h" +#include "Core/MIPS/LoongArch64/LoongArch64RegCache.h" +#include "Core/MIPS/JitCommon/JitState.h" +#include "Core/Reporting.h" + +using namespace LoongArch64Gen; +using namespace LoongArch64JitConstants; + +LoongArch64RegCache::LoongArch64RegCache(MIPSComp::JitOptions *jo) + : IRNativeRegCacheBase(jo) { + // The V(LSX) regs overlap F regs, so we just use one slot. + config_.totalNativeRegs = NUM_LAGPR + NUM_LAFPR; + // F regs are used for both FPU and Vec, so we don't need VREGs. + config_.mapUseVRegs = false; + config_.mapFPUSIMD = true; +} + +void LoongArch64RegCache::Init(LoongArch64Emitter *emitter) { + emit_ = emitter; +} + +void LoongArch64RegCache::SetupInitialRegs() { + IRNativeRegCacheBase::SetupInitialRegs(); + + // Treat R_ZERO a bit specially, but it's basically static alloc too. + nrInitial_[R_ZERO].mipsReg = MIPS_REG_ZERO; + nrInitial_[R_ZERO].normalized32 = true; + + // Since we also have a fixed zero, mark it as a static allocation. + mrInitial_[MIPS_REG_ZERO].loc = MIPSLoc::REG_IMM; + mrInitial_[MIPS_REG_ZERO].nReg = R_ZERO; + mrInitial_[MIPS_REG_ZERO].imm = 0; + mrInitial_[MIPS_REG_ZERO].isStatic = true; +} + +const int *LoongArch64RegCache::GetAllocationOrder(MIPSLoc type, MIPSMap flags, int &count, int &base) const { + base = R0; + + if (type == MIPSLoc::REG) { + // R22-R26 (Also R27) are most suitable for static allocation. Those that are chosen for static allocation + static const int allocationOrder[] = { + R22, R23, R24, R25, R26, R27, R4, R5, R6, R7, R8, R9, R10, R11, R14, R15, R16, R17, R18, R19, R20, + }; + static const int allocationOrderStaticAlloc[] = { + R4, R5, R6, R7, R8, R9, R10, R11, R14, R15, R16, R17, R18, R19, R20, + }; + + if (jo_->useStaticAlloc) { + count = ARRAY_SIZE(allocationOrderStaticAlloc); + return allocationOrderStaticAlloc; + } else { + count = ARRAY_SIZE(allocationOrder); + return allocationOrder; + } + } else if (type == MIPSLoc::FREG) { + static const int allocationOrder[] = { + F24, F25, F26, F27, F28, F29, F30, F31, + F0, F1, F2, F3, F4, F5, F6, F7, + F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, + }; + + count = ARRAY_SIZE(allocationOrder); + return allocationOrder; + } else { + _assert_msg_(false, "Allocation order not yet implemented"); + count = 0; + return nullptr; + } +} + +const LoongArch64RegCache::StaticAllocation *LoongArch64RegCache::GetStaticAllocations(int &count) const { + static const StaticAllocation allocs[] = { + { MIPS_REG_SP, R22, MIPSLoc::REG, true }, + { MIPS_REG_V0, R23, MIPSLoc::REG }, + { MIPS_REG_V1, R24, MIPSLoc::REG }, + { MIPS_REG_A0, R25, MIPSLoc::REG }, + { MIPS_REG_A1, R26, MIPSLoc::REG }, + { MIPS_REG_RA, R27, MIPSLoc::REG }, + }; + + if (jo_->useStaticAlloc) { + count = ARRAY_SIZE(allocs); + return allocs; + } + return IRNativeRegCacheBase::GetStaticAllocations(count); +} + +void LoongArch64RegCache::EmitLoadStaticRegisters() { + int count; + const StaticAllocation *allocs = GetStaticAllocations(count); + for (int i = 0; i < count; i++) { + int offset = GetMipsRegOffset(allocs[i].mr); + if (allocs[i].pointerified && jo_->enablePointerify) { + emit_->LD_WU((LoongArch64Reg)allocs[i].nr, CTXREG, offset); + emit_->ADD_D((LoongArch64Reg)allocs[i].nr, (LoongArch64Reg)allocs[i].nr, MEMBASEREG); + } else { + emit_->LD_W((LoongArch64Reg)allocs[i].nr, CTXREG, offset); + } + } +} + +void LoongArch64RegCache::EmitSaveStaticRegisters() { + int count; + const StaticAllocation *allocs = GetStaticAllocations(count); + // This only needs to run once (by Asm) so checks don't need to be fast. + for (int i = 0; i < count; i++) { + int offset = GetMipsRegOffset(allocs[i].mr); + emit_->ST_W((LoongArch64Reg)allocs[i].nr, CTXREG, offset); + } +} + +void LoongArch64RegCache::FlushBeforeCall() { + // These registers are not preserved by function calls. + // They match between R0 and F0, conveniently. + for (int i = 4; i <= 20; ++i) { + FlushNativeReg(R0 + i); + } + for (int i = 0; i <= 23; ++i) { + FlushNativeReg(F0 + i); + } +} + +bool LoongArch64RegCache::IsNormalized32(IRReg mipsReg) { + _dbg_assert_(IsValidGPR(mipsReg)); + if (mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM) { + return nr[mr[mipsReg].nReg].normalized32; + } + return false; +} + +LoongArch64Gen::LoongArch64Reg LoongArch64RegCache::Normalize32(IRReg mipsReg, LoongArch64Gen::LoongArch64Reg destReg) { + _dbg_assert_(IsValidGPR(mipsReg)); + _dbg_assert_(destReg == INVALID_REG || (destReg > R0 && destReg <= R31)); + + LoongArch64Reg reg = (LoongArch64Reg)mr[mipsReg].nReg; + + switch (mr[mipsReg].loc) { + case MIPSLoc::IMM: + case MIPSLoc::MEM: + _assert_msg_(false, "Cannot normalize an imm or mem"); + return INVALID_REG; + + case MIPSLoc::REG: + case MIPSLoc::REG_IMM: + if (!nr[mr[mipsReg].nReg].normalized32) { + if (destReg == INVALID_REG) { + emit_->ADDI_W((LoongArch64Reg)mr[mipsReg].nReg, (LoongArch64Reg)mr[mipsReg].nReg, 0); + nr[mr[mipsReg].nReg].normalized32 = true; + nr[mr[mipsReg].nReg].pointerified = false; + } else { + emit_->ADDI_W(destReg, (LoongArch64Reg)mr[mipsReg].nReg, 0); + } + } else if (destReg != INVALID_REG) { + emit_->ADDI_W(destReg, (LoongArch64Reg)mr[mipsReg].nReg, 0); + } + break; + + case MIPSLoc::REG_AS_PTR: + _dbg_assert_(nr[mr[mipsReg].nReg].normalized32 == false); + if (destReg == INVALID_REG) { + // If we can pointerify, ADDI_W will be enough. + if (!jo_->enablePointerify) + AdjustNativeRegAsPtr(mr[mipsReg].nReg, false); + emit_->ADDI_W((LoongArch64Reg)mr[mipsReg].nReg, (LoongArch64Reg)mr[mipsReg].nReg, 0); + mr[mipsReg].loc = MIPSLoc::REG; + nr[mr[mipsReg].nReg].normalized32 = true; + nr[mr[mipsReg].nReg].pointerified = false; + } else if (!jo_->enablePointerify) { + emit_->SUB_D(destReg, (LoongArch64Reg)mr[mipsReg].nReg, MEMBASEREG); + emit_->ADDI_W(destReg, destReg, 0); + } else { + emit_->ADDI_W(destReg, (LoongArch64Reg)mr[mipsReg].nReg, 0); + } + break; + + default: + _assert_msg_(false, "Should not normalize32 floats"); + break; + } + + return destReg == INVALID_REG ? reg : destReg; +} + +LoongArch64Reg LoongArch64RegCache::TryMapTempImm(IRReg r) { + _dbg_assert_(IsValidGPR(r)); + // If already mapped, no need for a temporary. + if (IsGPRMapped(r)) { + return R(r); + } + + if (mr[r].loc == MIPSLoc::IMM) { + if (mr[r].imm == 0) { + return R_ZERO; + } + + // Try our luck - check for an exact match in another LoongArch reg. + for (int i = 0; i < TOTAL_MAPPABLE_IRREGS; ++i) { + if (mr[i].loc == MIPSLoc::REG_IMM && mr[i].imm == mr[r].imm) { + // Awesome, let's just use this reg. + return (LoongArch64Reg)mr[i].nReg; + } + } + } + + return INVALID_REG; +} + +LoongArch64Reg LoongArch64RegCache::GetAndLockTempGPR() { + LoongArch64Reg reg = (LoongArch64Reg)AllocateReg(MIPSLoc::REG, MIPSMap::INIT); + if (reg != INVALID_REG) { + nr[reg].tempLockIRIndex = irIndex_; + } + return reg; +} + +LoongArch64Reg LoongArch64RegCache::MapWithFPRTemp(const IRInst &inst) { + return (LoongArch64Reg)MapWithTemp(inst, MIPSLoc::FREG); +} + +LoongArch64Reg LoongArch64RegCache::MapGPR(IRReg mipsReg, MIPSMap mapFlags) { + _dbg_assert_(IsValidGPR(mipsReg)); + + // Okay, not mapped, so we need to allocate an LA register. + IRNativeReg nreg = MapNativeReg(MIPSLoc::REG, mipsReg, 1, mapFlags); + return (LoongArch64Reg)nreg; +} + +LoongArch64Reg LoongArch64RegCache::MapGPRAsPointer(IRReg reg) { + return (LoongArch64Reg)MapNativeRegAsPointer(reg); +} + +LoongArch64Reg LoongArch64RegCache::MapFPR(IRReg mipsReg, MIPSMap mapFlags) { + _dbg_assert_(IsValidFPR(mipsReg)); + _dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::MEM || mr[mipsReg + 32].loc == MIPSLoc::FREG); + + IRNativeReg nreg = MapNativeReg(MIPSLoc::FREG, mipsReg + 32, 1, mapFlags); + if (nreg != -1) + return (LoongArch64Reg)nreg; + return INVALID_REG; +} + +LoongArch64Reg LoongArch64RegCache::MapVec4(IRReg first, MIPSMap mapFlags) { + _dbg_assert_(IsValidFPR(first)); + _dbg_assert_((first & 3) == 0); + _dbg_assert_(mr[first + 32].loc == MIPSLoc::MEM || mr[first + 32].loc == MIPSLoc::FREG); + + IRNativeReg nreg = MapNativeReg(MIPSLoc::FREG, first + 32, 4, mapFlags); + if (nreg != -1) + return EncodeRegToV((LoongArch64Reg)nreg); + return INVALID_REG; +} + +void LoongArch64RegCache::AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) { + LoongArch64Reg r = (LoongArch64Reg)(R0 + nreg); + _assert_(r >= R0 && r <= R31); + if (state) { +#ifdef MASKED_PSP_MEMORY + // This destroys the value... + _dbg_assert_(!nr[nreg].isDirty); + emit_->SLLI_W(r, r, 2); + emit_->SRLI_W(r, r, 2); + emit_->ADD_D(r, r, MEMBASEREG); +#else + // Clear the top bits to be safe. + emit_->SLLI_D(r, r, 32); + emit_->SRLI_D(r, r, 32); + emit_->ADD_D(r, r, MEMBASEREG); +#endif + nr[nreg].normalized32 = false; + } else { +#ifdef MASKED_PSP_MEMORY + _dbg_assert_(!nr[nreg].isDirty); +#endif + emit_->SUB_D(r, r, MEMBASEREG); + nr[nreg].normalized32 = false; + } +} + +bool LoongArch64RegCache::IsNativeRegCompatible(IRNativeReg nreg, MIPSLoc type, MIPSMap flags, int lanes) { + // No special flags except VREG, skip the check for a little speed. + if (type != MIPSLoc::VREG) + return true; + return IRNativeRegCacheBase::IsNativeRegCompatible(nreg, type, flags, lanes); +} + +void LoongArch64RegCache::LoadNativeReg(IRNativeReg nreg, IRReg first, int lanes) { + LoongArch64Reg r = (LoongArch64Reg)(R0 + nreg); + _dbg_assert_(r > R0); + _dbg_assert_(first != MIPS_REG_ZERO); + if (r <= R31) { + _assert_(lanes == 1 || (lanes == 2 && first == IRREG_LO)); + if (lanes == 1) + emit_->LD_W(r, CTXREG, GetMipsRegOffset(first)); + else if (lanes == 2) + emit_->LD_D(r, CTXREG, GetMipsRegOffset(first)); + else + _assert_(false); + nr[nreg].normalized32 = true; + } else { + _dbg_assert_(r >= F0 && r <= F31); + _assert_msg_(mr[first].loc == MIPSLoc::FREG, "Cannot store this type: %d", (int)mr[first].loc); + if (lanes == 1) + emit_->FLD_S(r, CTXREG, GetMipsRegOffset(first)); + else if (lanes == 2) + emit_->FLD_D(r, CTXREG, GetMipsRegOffset(first)); + else if (lanes == 4) + emit_->VLD(EncodeRegToV(r), CTXREG, GetMipsRegOffset(first)); + else + _assert_(false); + } +} + +void LoongArch64RegCache::StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) { + LoongArch64Reg r = (LoongArch64Reg)(R0 + nreg); + _dbg_assert_(r > R0); + _dbg_assert_(first != MIPS_REG_ZERO); + if (r <= R31) { + _assert_(lanes == 1 || (lanes == 2 && first == IRREG_LO)); + _assert_(mr[first].loc == MIPSLoc::REG || mr[first].loc == MIPSLoc::REG_IMM); + if (lanes == 1) + emit_->ST_W(r, CTXREG, GetMipsRegOffset(first)); + else if (lanes == 2) + emit_->ST_D(r, CTXREG, GetMipsRegOffset(first)); + else + _assert_(false); + } else { + _dbg_assert_(r >= F0 && r <= F31); + _assert_msg_(mr[first].loc == MIPSLoc::FREG, "Cannot store this type: %d", (int)mr[first].loc); + if (lanes == 1) + emit_->FST_S(r, CTXREG, GetMipsRegOffset(first)); + else if (lanes == 2) + emit_->FST_D(r, CTXREG, GetMipsRegOffset(first)); + else if (lanes == 4) + emit_->VST(EncodeRegToV(r), CTXREG, GetMipsRegOffset(first)); + else + _assert_(false); + } +} + +void LoongArch64RegCache::SetNativeRegValue(IRNativeReg nreg, uint32_t imm) { + LoongArch64Reg r = (LoongArch64Reg)(R0 + nreg); + if (r == R_ZERO && imm == 0) + return; + _dbg_assert_(r > R0 && r <= R31); + emit_->LI(r, (int32_t)imm); + + // We always use 32-bit immediates, so this is normalized now. + nr[nreg].normalized32 = true; +} + +void LoongArch64RegCache::StoreRegValue(IRReg mreg, uint32_t imm) { + _assert_(IsValidGPRNoZero(mreg)); + // Try to optimize using a different reg. + LoongArch64Reg storeReg = INVALID_REG; + + // Zero is super easy. + if (imm == 0) { + storeReg = R_ZERO; + } else { + // Could we get lucky? Check for an exact match in another lareg. + for (int i = 0; i < TOTAL_MAPPABLE_IRREGS; ++i) { + if (mr[i].loc == MIPSLoc::REG_IMM && mr[i].imm == imm) { + // Awesome, let's just store this reg. + storeReg = (LoongArch64Reg)mr[i].nReg; + break; + } + } + + if (storeReg == INVALID_REG) { + emit_->LI(SCRATCH1, imm); + storeReg = SCRATCH1; + } + } + + emit_->ST_W(storeReg, CTXREG, GetMipsRegOffset(mreg)); +} + +bool LoongArch64RegCache::TransferNativeReg(IRNativeReg nreg, IRNativeReg dest, MIPSLoc type, IRReg first, int lanes, MIPSMap flags) { + bool allowed = !mr[nr[nreg].mipsReg].isStatic; + // There's currently no support for non-FREGs here. + allowed = allowed && type == MIPSLoc::FREG; + + if (dest == -1) + dest = nreg; + + if (allowed && (flags == MIPSMap::INIT || flags == MIPSMap::DIRTY)) { + // Alright, changing lane count (possibly including lane position.) + IRReg oldfirst = nr[nreg].mipsReg; + int oldlanes = 0; + while (mr[oldfirst + oldlanes].nReg == nreg) + oldlanes++; + _assert_msg_(oldlanes != 0, "TransferNativeReg encountered nreg mismatch"); + _assert_msg_(oldlanes != lanes, "TransferNativeReg transfer to same lanecount, misaligned?"); + + if (lanes == 1 && TransferVecTo1(nreg, dest, first, oldlanes)) + return true; + if (oldlanes == 1 && Transfer1ToVec(nreg, dest, first, lanes)) + return true; + } + + return IRNativeRegCacheBase::TransferNativeReg(nreg, dest, type, first, lanes, flags); +} + +bool LoongArch64RegCache::TransferVecTo1(IRNativeReg nreg, IRNativeReg dest, IRReg first, int oldlanes) { + IRReg oldfirst = nr[nreg].mipsReg; + + // Is it worth preserving any of the old regs? + int numKept = 0; + for (int i = 0; i < oldlanes; ++i) { + // Skip whichever one this is extracting. + if (oldfirst + i == first) + continue; + // If 0 isn't being transfered, easy to keep in its original reg. + if (i == 0 && dest != nreg) { + numKept++; + continue; + } + + IRNativeReg freeReg = FindFreeReg(MIPSLoc::FREG, MIPSMap::INIT); + if (freeReg != -1 && IsRegRead(MIPSLoc::FREG, oldfirst + i)) { + // If there's one free, use it. Don't modify nreg, though. + emit_->VREPLVEI_W(FromNativeReg(freeReg), FromNativeReg(nreg), i); + + // Update accounting. + nr[freeReg].isDirty = nr[nreg].isDirty; + nr[freeReg].mipsReg = oldfirst + i; + mr[oldfirst + i].lane = -1; + mr[oldfirst + i].nReg = freeReg; + numKept++; + } + } + + // Unless all other lanes were kept, store. + if (nr[nreg].isDirty && numKept < oldlanes - 1) { + StoreNativeReg(nreg, oldfirst, oldlanes); + // Set false even for regs that were split out, since they were flushed too. + for (int i = 0; i < oldlanes; ++i) { + if (mr[oldfirst + i].nReg != -1) + nr[mr[oldfirst + i].nReg].isDirty = false; + } + } + + // Next, shuffle the desired element into first place. + if (mr[first].lane > 0) { + emit_->VREPLVEI_W(FromNativeReg(dest), FromNativeReg(nreg), mr[first].lane); + } else if (mr[first].lane <= 0 && dest != nreg) { + emit_->VREPLVEI_W(FromNativeReg(dest), FromNativeReg(nreg), 0); + } + + // Now update accounting. + for (int i = 0; i < oldlanes; ++i) { + auto &mreg = mr[oldfirst + i]; + if (oldfirst + i == first) { + mreg.lane = -1; + mreg.nReg = dest; + } else if (mreg.nReg == nreg && i == 0 && nreg != dest) { + // Still in the same register, but no longer a vec. + mreg.lane = -1; + } else if (mreg.nReg == nreg) { + // No longer in a register. + mreg.nReg = -1; + mreg.lane = -1; + mreg.loc = MIPSLoc::MEM; + } + } + + if (dest != nreg) { + nr[dest].isDirty = nr[nreg].isDirty; + if (oldfirst == first) { + nr[nreg].mipsReg = -1; + nr[nreg].isDirty = false; + } + } + nr[dest].mipsReg = first; + + return true; +} + +bool LoongArch64RegCache::Transfer1ToVec(IRNativeReg nreg, IRNativeReg dest, IRReg first, int lanes) { + LoongArch64Reg destReg = FromNativeReg(dest); + LoongArch64Reg cur[4]{}; + int numInRegs = 0; + u8 blendMask = 0; + for (int i = 0; i < lanes; ++i) { + if (mr[first + i].lane != -1 || (i != 0 && mr[first + i].spillLockIRIndex >= irIndex_)) { + // Can't do it, either double mapped or overlapping vec. + return false; + } + + if (mr[first + i].nReg == -1) { + cur[i] = INVALID_REG; + blendMask |= 1 << i; + } else { + cur[i] = FromNativeReg(mr[first + i].nReg); + numInRegs++; + } + } + + // Shouldn't happen, this should only get called to transfer one in a reg. + if (numInRegs == 0) + return false; + + // If everything's currently in a reg, move it into this reg. + if (lanes == 4) { + // Go with an exhaustive approach, only 15 possibilities... + if (blendMask == 0) { + // y = yw##, x = xz##, dest = xyzw. + emit_->VILVL_W(EncodeRegToV(cur[1]), EncodeRegToV(cur[3]), EncodeRegToV(cur[1])); + emit_->VILVL_W(EncodeRegToV(cur[0]), EncodeRegToV(cur[2]), EncodeRegToV(cur[0])); + emit_->VILVL_W(EncodeRegToV(destReg), EncodeRegToV(cur[1]), EncodeRegToV(cur[0])); + } else if (blendMask == 0b0001) { + // y = yw##, w = x###, w = xz##, dest = xyzw. + emit_->VILVL_W(EncodeRegToV(cur[1]), EncodeRegToV(cur[3]), EncodeRegToV(cur[1])); + emit_->FLD_S( SCRATCHF1, CTXREG, GetMipsRegOffset(first + 0)); + emit_->VEXTRINS_W(EncodeRegToV(cur[3]), EncodeRegToV(SCRATCHF1), 0); + emit_->VILVL_W(EncodeRegToV(cur[3]), EncodeRegToV(cur[2]), EncodeRegToV(cur[3])); + emit_->VILVL_W(EncodeRegToV(destReg), EncodeRegToV(cur[1]), EncodeRegToV(cur[3])); + } else if (blendMask == 0b0010) { + // x = xz##, z = y###, z = yw##, dest = xyzw. + emit_->VILVL_W(EncodeRegToV(cur[0]), EncodeRegToV(cur[2]), EncodeRegToV(cur[0])); + emit_->FLD_S( SCRATCHF1, CTXREG, GetMipsRegOffset(first + 1)); + emit_->VEXTRINS_W(EncodeRegToV(cur[2]), EncodeRegToV(SCRATCHF1), 0); + emit_->VILVL_W(EncodeRegToV(cur[2]), EncodeRegToV(cur[3]), EncodeRegToV(cur[2])); + emit_->VILVL_W(EncodeRegToV(destReg), EncodeRegToV(cur[2]), EncodeRegToV(cur[0])); + } else if (blendMask == 0b0011 && (first & 1) == 0) { + // z = zw##, w = xy##, dest = xyzw. Mixed lane sizes. + emit_->VILVL_W(EncodeRegToV(cur[2]), EncodeRegToV(cur[3]), EncodeRegToV(cur[2])); + emit_->FLD_D( SCRATCHF1, CTXREG, GetMipsRegOffset(first + 0)); + emit_->VEXTRINS_D(EncodeRegToV(cur[3]), EncodeRegToV(SCRATCHF1), 0); + emit_->VILVL_W(EncodeRegToV(destReg), EncodeRegToV(cur[2]), EncodeRegToV(cur[3])); + } else if (blendMask == 0b0100) { + // y = yw##, w = z###, x = xz##, dest = xyzw. + emit_->VILVL_W(EncodeRegToV(cur[1]), EncodeRegToV(cur[3]), EncodeRegToV(cur[1])); + emit_->FLD_S( SCRATCHF1, CTXREG, GetMipsRegOffset(first + 2)); + emit_->VEXTRINS_W(EncodeRegToV(cur[3]), EncodeRegToV(SCRATCHF1), 0); + emit_->VILVL_W(EncodeRegToV(cur[0]), EncodeRegToV(cur[3]), EncodeRegToV(cur[0])); + emit_->VILVL_W(EncodeRegToV(destReg), EncodeRegToV(cur[1]), EncodeRegToV(cur[0])); + } else if (blendMask == 0b0101 && (first & 3) == 0) { + // y = yw##, w=x#z#, w = xz##, dest = xyzw. + emit_->VILVL_W(EncodeRegToV(cur[1]), EncodeRegToV(cur[3]), EncodeRegToV(cur[1])); + emit_->VLD(EncodeRegToV(cur[3]), CTXREG, GetMipsRegOffset(first)); + emit_->VPICKEV_W(EncodeRegToV(cur[3]), EncodeRegToV(cur[3]), EncodeRegToV(cur[3])); + emit_->VILVL_W(EncodeRegToV(destReg), EncodeRegToV(cur[1]), EncodeRegToV(cur[3])); + } else if (blendMask == 0b0110 && (first & 3) == 0) { + if (destReg == cur[0]) { + // w = wx##, dest = #yz#, dest = xyz#, dest = xyzw. + emit_->VILVL_W(EncodeRegToV(cur[3]), EncodeRegToV(cur[0]), EncodeRegToV(cur[3])); + emit_->VLD(EncodeRegToV(destReg), CTXREG, GetMipsRegOffset(first)); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[3]), 1); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[3]), (3 << 4)); + } else { + // Assumes destReg may equal cur[3]. + // x = xw##, dest = #yz#, dest = xyz#, dest = xyzw. + emit_->VILVL_W(EncodeRegToV(cur[0]), EncodeRegToV(cur[3]), EncodeRegToV(cur[0])); + emit_->VLD(EncodeRegToV(destReg), CTXREG, GetMipsRegOffset(first)); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[0]), 0); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[0]), (3 << 4 | 1)); + } + } else if (blendMask == 0b0111 && (first & 3) == 0 && destReg != cur[3]) { + // dest = xyz#, dest = xyzw. + emit_->VLD(EncodeRegToV(destReg), CTXREG, GetMipsRegOffset(first)); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[3]), (3 << 4)); + } else if (blendMask == 0b1000) { + // x = xz##, z = w###, y = yw##, dest = xyzw. + emit_->VILVL_W(EncodeRegToV(cur[0]), EncodeRegToV(cur[2]), EncodeRegToV(cur[0])); + emit_->FLD_S(SCRATCHF1, CTXREG, GetMipsRegOffset(first + 3)); + emit_->VEXTRINS_W(EncodeRegToV(cur[2]), EncodeRegToV(SCRATCHF1), 0); + emit_->VILVL_W(EncodeRegToV(cur[1]), EncodeRegToV(cur[2]), EncodeRegToV(cur[1])); + emit_->VILVL_W(EncodeRegToV(destReg), EncodeRegToV(cur[1]), EncodeRegToV(cur[0])); + } else if (blendMask == 0b1001 && (first & 3) == 0) { + if (destReg == cur[1]) { + // w = zy##, dest = x##w, dest = xy#w, dest = xyzw. + emit_->VILVL_W(EncodeRegToV(cur[2]), EncodeRegToV(cur[1]), EncodeRegToV(cur[2])); + emit_->VLD(EncodeRegToV(destReg), CTXREG, GetMipsRegOffset(first)); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[2]), (1 << 4 | 1)); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[2]), (2 << 4)); + } else { + // Assumes destReg may equal cur[2]. + // y = yz##, dest = x##w, dest = xy#w, dest = xyzw. + emit_->VILVL_W(EncodeRegToV(cur[1]), EncodeRegToV(cur[2]), EncodeRegToV(cur[1])); + emit_->VLD(EncodeRegToV(destReg), CTXREG, GetMipsRegOffset(first)); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[1]), (1 << 4)); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[1]), (2 << 4 | 1)); + } + } else if (blendMask == 0b1010 && (first & 3) == 0) { + // x = xz##, z = #y#w, z=yw##, dest = xyzw. + emit_->VILVL_W(EncodeRegToV(cur[0]), EncodeRegToV(cur[2]), EncodeRegToV(cur[0])); + emit_->VLD(EncodeRegToV(cur[2]), CTXREG, GetMipsRegOffset(first)); + emit_->VPICKOD_W(EncodeRegToV(cur[2]), EncodeRegToV(cur[2]), EncodeRegToV(cur[2])); + emit_->VILVL_W(EncodeRegToV(destReg), EncodeRegToV(cur[2]), EncodeRegToV(cur[0])); + } else if (blendMask == 0b1011 && (first & 3) == 0 && destReg != cur[2]) { + // dest = xy#w, dest = xyzw. + emit_->VLD(EncodeRegToV(destReg), CTXREG, GetMipsRegOffset(first)); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[2]), (2 << 4)); + } else if (blendMask == 0b1100 && (first & 1) == 0) { + // x = xy##, y = zw##, dest = xyzw. Mixed lane sizes. + emit_->VILVL_W(EncodeRegToV(cur[0]), EncodeRegToV(cur[1]), EncodeRegToV(cur[0])); + emit_->FLD_D(SCRATCHF1, CTXREG, GetMipsRegOffset(first + 2)); + emit_->VEXTRINS_D(EncodeRegToV(cur[1]), EncodeRegToV(SCRATCHF1), 0); + emit_->VILVL_D(EncodeRegToV(destReg), EncodeRegToV(cur[1]), EncodeRegToV(cur[0])); + } else if (blendMask == 0b1101 && (first & 3) == 0 && destReg != cur[1]) { + // dest = x#zw, dest = xyzw. + emit_->VLD(EncodeRegToV(destReg), CTXREG, GetMipsRegOffset(first)); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[1]), (1 << 4)); + } else if (blendMask == 0b1110 && (first & 3) == 0 && destReg != cur[0]) { + // dest = #yzw, dest = xyzw. + emit_->VLD(EncodeRegToV(destReg), CTXREG, GetMipsRegOffset(first)); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(cur[0]), 0); + } else if (blendMask == 0b1110 && (first & 3) == 0) { + // If dest == cur[0] (which may be common), we need a temp... + IRNativeReg freeReg = FindFreeReg(MIPSLoc::FREG, MIPSMap::INIT); + // Very unfortunate. + if (freeReg == INVALID_REG) + return false; + + // free = x###, dest = #yzw, dest = xyzw. + emit_->VREPLVEI_W(EncodeRegToV(FromNativeReg(freeReg)), EncodeRegToV(cur[0]), 0); + emit_->VLD(EncodeRegToV(destReg), CTXREG, GetMipsRegOffset(first)); + emit_->VEXTRINS_W(EncodeRegToV(destReg), EncodeRegToV(FromNativeReg(freeReg)), 0); + } else { + return false; + } + } else { + return false; + } + + mr[first].lane = 0; + for (int i = 0; i < lanes; ++i) { + if (mr[first + i].nReg != -1) { + // If this was dirty, the combined reg is now dirty. + if (nr[mr[first + i].nReg].isDirty) + nr[dest].isDirty = true; + + // Throw away the other register we're no longer using. + if (i != 0) + DiscardNativeReg(mr[first + i].nReg); + } + + // And set it as using the new one. + mr[first + i].lane = i; + mr[first + i].loc = MIPSLoc::FREG; + mr[first + i].nReg = dest; + } + + if (dest != nreg) { + nr[dest].mipsReg = first; + nr[nreg].mipsReg = -1; + nr[nreg].isDirty = false; + } + + return true; +} + +LoongArch64Reg LoongArch64RegCache::R(IRReg mipsReg) { + _dbg_assert_(IsValidGPR(mipsReg)); + _dbg_assert_(mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM); + if (mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM) { + return (LoongArch64Reg)mr[mipsReg].nReg; + } else { + ERROR_LOG_REPORT(Log::JIT, "Reg %i not in LoongArch64 reg", mipsReg); + return INVALID_REG; // BAAAD + } +} + +LoongArch64Reg LoongArch64RegCache::RPtr(IRReg mipsReg) { + _dbg_assert_(IsValidGPR(mipsReg)); + _dbg_assert_(mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM || mr[mipsReg].loc == MIPSLoc::REG_AS_PTR); + if (mr[mipsReg].loc == MIPSLoc::REG_AS_PTR) { + return (LoongArch64Reg)mr[mipsReg].nReg; + } else if (mr[mipsReg].loc == MIPSLoc::REG || mr[mipsReg].loc == MIPSLoc::REG_IMM) { + int la = mr[mipsReg].nReg; + _dbg_assert_(nr[la].pointerified); + if (nr[la].pointerified) { + return (LoongArch64Reg)mr[mipsReg].nReg; + } else { + ERROR_LOG(Log::JIT, "Tried to use a non-pointer register as a pointer"); + return INVALID_REG; + } + } else { + ERROR_LOG_REPORT(Log::JIT, "Reg %i not in LoongArch64 reg", mipsReg); + return INVALID_REG; // BAAAD + } +} + +LoongArch64Reg LoongArch64RegCache::F(IRReg mipsReg) { + _dbg_assert_(IsValidFPR(mipsReg)); + _dbg_assert_(mr[mipsReg + 32].loc == MIPSLoc::FREG); + if (mr[mipsReg + 32].loc == MIPSLoc::FREG) { + return (LoongArch64Reg)mr[mipsReg + 32].nReg; + } else { + ERROR_LOG_REPORT(Log::JIT, "Reg %i not in LoongArch64 reg", mipsReg); + return INVALID_REG; // BAAAD + } +} + +LoongArch64Reg LoongArch64RegCache::V(IRReg mipsReg) { + return EncodeRegToV(F(mipsReg)); +} diff --git a/Core/MIPS/LoongArch64/LoongArch64RegCache.h b/Core/MIPS/LoongArch64/LoongArch64RegCache.h new file mode 100644 index 0000000000..30dff82aad --- /dev/null +++ b/Core/MIPS/LoongArch64/LoongArch64RegCache.h @@ -0,0 +1,102 @@ +// Copyright (c) 2023- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#pragma once + +#include "Common/LoongArch64Emitter.h" +#include "Core/MIPS/MIPS.h" +#include "Core/MIPS/IR/IRJit.h" +#include "Core/MIPS/IR/IRRegCache.h" + +namespace LoongArch64JitConstants { + +const LoongArch64Gen::LoongArch64Reg DOWNCOUNTREG = LoongArch64Gen::R28; +const LoongArch64Gen::LoongArch64Reg JITBASEREG = LoongArch64Gen::R29; +const LoongArch64Gen::LoongArch64Reg CTXREG = LoongArch64Gen::R30; +const LoongArch64Gen::LoongArch64Reg MEMBASEREG = LoongArch64Gen::R31; +const LoongArch64Gen::LoongArch64Reg SCRATCH1 = LoongArch64Gen::R12; +const LoongArch64Gen::LoongArch64Reg SCRATCH2 = LoongArch64Gen::R13; +const LoongArch64Gen::LoongArch64Reg SCRATCHF1 = LoongArch64Gen::F8; +const LoongArch64Gen::LoongArch64Reg SCRATCHF2 = LoongArch64Gen::F9; + +} // namespace LoongArch64JitConstants + +class LoongArch64RegCache : public IRNativeRegCacheBase { +public: + LoongArch64RegCache(MIPSComp::JitOptions *jo); + + void Init(LoongArch64Gen::LoongArch64Emitter *emitter); + + // May fail and return INVALID_REG if it needs flushing. + LoongArch64Gen::LoongArch64Reg TryMapTempImm(IRReg reg); + + // Returns an LA register containing the requested MIPS register. + LoongArch64Gen::LoongArch64Reg MapGPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT); + LoongArch64Gen::LoongArch64Reg MapGPRAsPointer(IRReg reg); + LoongArch64Gen::LoongArch64Reg MapFPR(IRReg reg, MIPSMap mapFlags = MIPSMap::INIT); + LoongArch64Gen::LoongArch64Reg MapVec4(IRReg first, MIPSMap mapFlags = MIPSMap::INIT); + + LoongArch64Gen::LoongArch64Reg MapWithFPRTemp(const IRInst &inst); + + bool IsNormalized32(IRReg reg); + + // Copies to another reg if specified, otherwise same reg. + LoongArch64Gen::LoongArch64Reg Normalize32(IRReg reg, LoongArch64Gen::LoongArch64Reg destReg = LoongArch64Gen::INVALID_REG); + + void FlushBeforeCall(); + + LoongArch64Gen::LoongArch64Reg GetAndLockTempGPR(); + + LoongArch64Gen::LoongArch64Reg R(IRReg preg); // Returns a cached register, while checking that it's NOT mapped as a pointer + LoongArch64Gen::LoongArch64Reg RPtr(IRReg preg); // Returns a cached register, if it has been mapped as a pointer + LoongArch64Gen::LoongArch64Reg F(IRReg preg); + LoongArch64Gen::LoongArch64Reg V(IRReg preg); + + // These are called once on startup to generate functions, that you should then call. + void EmitLoadStaticRegisters(); + void EmitSaveStaticRegisters(); + +protected: + void SetupInitialRegs() override; + const StaticAllocation *GetStaticAllocations(int &count) const override; + const int *GetAllocationOrder(MIPSLoc type, MIPSMap flags, int &count, int &base) const override; + void AdjustNativeRegAsPtr(IRNativeReg nreg, bool state) override; + + bool IsNativeRegCompatible(IRNativeReg nreg, MIPSLoc type, MIPSMap flags, int lanes) override; + void LoadNativeReg(IRNativeReg nreg, IRReg first, int lanes) override; + void StoreNativeReg(IRNativeReg nreg, IRReg first, int lanes) override; + void SetNativeRegValue(IRNativeReg nreg, uint32_t imm) override; + void StoreRegValue(IRReg mreg, uint32_t imm) override; + bool TransferNativeReg(IRNativeReg nreg, IRNativeReg dest, MIPSLoc type, IRReg first, int lanes, MIPSMap flags) override; + +private: + bool TransferVecTo1(IRNativeReg nreg, IRNativeReg dest, IRReg first, int oldlanes); + bool Transfer1ToVec(IRNativeReg nreg, IRNativeReg dest, IRReg first, int lanes); + + LoongArch64Gen::LoongArch64Reg FromNativeReg(IRNativeReg r) { + if (r >= NUM_LAGPR) + return (LoongArch64Gen::LoongArch64Reg)(LoongArch64Gen::V0 + (r - NUM_LAGPR)); + return (LoongArch64Gen::LoongArch64Reg)(LoongArch64Gen::R0 + r); + } + + LoongArch64Gen::LoongArch64Emitter *emit_ = nullptr; + + enum { + NUM_LAGPR = 32, + NUM_LAFPR = 32, + }; +}; diff --git a/Core/MemFault.cpp b/Core/MemFault.cpp index e788c72420..80ffc9a120 100644 --- a/Core/MemFault.cpp +++ b/Core/MemFault.cpp @@ -98,6 +98,12 @@ static bool DisassembleNativeAt(const uint8_t *codePtr, int instructionSize, std *dest = lines[0]; return true; } +#elif PPSSPP_ARCH(LOONGARCH64) + auto lines = DisassembleLA64(codePtr, instructionSize); + if (!lines.empty()) { + *dest = lines[0]; + return true; + } #endif return false; } diff --git a/UWP/CoreUWP/CoreUWP.vcxproj b/UWP/CoreUWP/CoreUWP.vcxproj index 672b819f73..88e16b6d91 100644 --- a/UWP/CoreUWP/CoreUWP.vcxproj +++ b/UWP/CoreUWP/CoreUWP.vcxproj @@ -326,6 +326,7 @@ + @@ -628,6 +629,7 @@ + diff --git a/UWP/CoreUWP/CoreUWP.vcxproj.filters b/UWP/CoreUWP/CoreUWP.vcxproj.filters index dada5b41fc..e45d4aac05 100644 --- a/UWP/CoreUWP/CoreUWP.vcxproj.filters +++ b/UWP/CoreUWP/CoreUWP.vcxproj.filters @@ -276,6 +276,7 @@ + @@ -650,6 +651,7 @@ + diff --git a/android/jni/Android.mk b/android/jni/Android.mk index 5987d02894..fb6a6222c2 100644 --- a/android/jni/Android.mk +++ b/android/jni/Android.mk @@ -976,13 +976,16 @@ ifeq ($(UNITTEST),1) $(SRC)/Common/ArmEmitter.cpp \ $(SRC)/Common/Arm64Emitter.cpp \ $(SRC)/Common/RiscVEmitter.cpp \ + $(SRC)/Common/LoongArch64Emitter.cpp \ $(SRC)/Core/MIPS/ARM/ArmRegCacheFPU.cpp \ $(SRC)/Core/Util/DisArm64.cpp \ $(SRC)/ext/disarm.cpp \ $(SRC)/ext/riscv-disas.cpp \ + $(SRC)/ext/loongarch-disasm.cpp \ $(SRC)/unittest/TestArmEmitter.cpp \ $(SRC)/unittest/TestArm64Emitter.cpp \ $(SRC)/unittest/TestRiscVEmitter.cpp \ + $(SRC)/unittest/TestLoongArch64Emitter.cpp \ $(SRC)/unittest/TestX64Emitter.cpp endif diff --git a/ext/loongarch-disasm.cpp b/ext/loongarch-disasm.cpp new file mode 100644 index 0000000000..c9c2bfd657 --- /dev/null +++ b/ext/loongarch-disasm.cpp @@ -0,0 +1,9925 @@ +/* + * LoongArch64 Disassembler + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "loongarch-disasm.h" +#include +#include +#include + +const IR2_OPND_TYPE ir2_opnd_type_table[] ={ + IR2_OPND_NONE, //OPD_INVALID + IR2_OPND_CC, //FCC_CA + IR2_OPND_CC, //FCC_CD + IR2_OPND_CC, //FCC_CJ + IR2_OPND_NONE, //IMM_CODE + IR2_OPND_IMM, //IMM_CONDF + IR2_OPND_IMM, //IMM_CONDH + IR2_OPND_IMM, //IMM_CONDL + IR2_OPND_NONE, //OPD_CSR + IR2_OPND_FPR, //FPR_FA + IR2_OPND_FCSR, //OPD_FCSRH + IR2_OPND_FCSR, //OPD_FCSRL + IR2_OPND_FPR, //FPR_FD + IR2_OPND_FPR, //FPR_FJ + IR2_OPND_FPR, //FPR_FK + IR2_OPND_IMM, //IMM_HINTL + IR2_OPND_IMM, //IMM_HINTS + IR2_OPND_IMM, //IMM_I13 + IR2_OPND_NONE, //IMM_IDXS + IR2_OPND_NONE, //IMM_IDXM + IR2_OPND_NONE, //IMM_IDXL + IR2_OPND_NONE, //IMM_IDXLL + IR2_OPND_NONE, //IMM_LEVEL + IR2_OPND_IMM, //IMM_LSBD + IR2_OPND_IMM, //IMM_LSBW + IR2_OPND_IMM, //IMM_MODE + IR2_OPND_IMM, //IMM_MSBD + IR2_OPND_IMM, //IMM_MSBW + IR2_OPND_IMM, //IMM_OFFS + IR2_OPND_IMM, //IMM_OFFL + IR2_OPND_IMM, //IMM_OFFLL + IR2_OPND_NONE, //OPD_OPCACHE + IR2_OPND_IMM, //IMM_OPX86 + IR2_OPND_IMM, //IMM_PTR + IR2_OPND_GPR, //GPR_RD + IR2_OPND_GPR, //GPR_RJ + IR2_OPND_GPR, //GPR_RK + IR2_OPND_IMM, //IMM_SA2 + IR2_OPND_IMM, //IMM_SA3 + IR2_OPND_SCR, //SCR_SD + IR2_OPND_NONE, //IMM_SEQ + IR2_OPND_IMM, //IMM_SI10 + IR2_OPND_IMM, //IMM_SI11 + IR2_OPND_IMM, //IMM_SI12 + IR2_OPND_IMM, //IMM_SI14 + IR2_OPND_IMM, //IMM_SI16 + IR2_OPND_IMM, //IMM_SI20 + IR2_OPND_IMM, //IMM_SI5 + IR2_OPND_IMM, //IMM_SI8 + IR2_OPND_IMM, //IMM_SI9 + IR2_OPND_SCR, //SCR_SJ + IR2_OPND_IMM, //IMM_UI1 + IR2_OPND_IMM, //IMM_UI12 + IR2_OPND_IMM, //IMM_UI2 + IR2_OPND_IMM, //IMM_UI3 + IR2_OPND_IMM, //IMM_UI4 + IR2_OPND_IMM, //IMM_UI5H + IR2_OPND_IMM, //IMM_UI5L + IR2_OPND_IMM, //IMM_UI6 + IR2_OPND_IMM, //IMM_UI7 + IR2_OPND_IMM, //IMM_UI8 + IR2_OPND_FPR, //FPR_VA + IR2_OPND_FPR, //FPR_VD + IR2_OPND_FPR, //FPR_VJ + IR2_OPND_FPR, //FPR_VK + IR2_OPND_FPR, //FPR_XA + IR2_OPND_FPR, //FPR_XD + IR2_OPND_FPR, //FPR_XJ + IR2_OPND_FPR, //FPR_XK +}; + +const GM_OPERAND_PLACE_RELATION bit_field_table[] = { + {OPD_INVALID, {-1, -1}, {-1, -1} }, + {FCC_CA, {15, 17}, {-1, -1} }, + {FCC_CD, {0, 2}, {-1, -1} }, + {FCC_CJ, {5, 7}, {-1, -1} }, + {IMM_CODE, {0, 14}, {-1, -1} }, + {IMM_CONDF, {15, 19}, {-1, -1} }, + {IMM_CONDH, {10, 13}, {-1, -1} }, + {IMM_CONDL, {0, 3}, {-1, -1} }, + {OPD_CSR, {10, 23}, {-1, -1} }, + {FPR_FA, {15, 19}, {-1, -1} }, + {OPD_FCSRH, {5, 9}, {-1, -1} }, + {OPD_FCSRL, {0, 4}, {-1, -1} }, + {FPR_FD, {0, 4}, {-1, -1} }, + {FPR_FJ, {5, 9}, {-1, -1} }, + {FPR_FK, {10, 14}, {-1, -1} }, + {IMM_HINTL, {0, 14}, {-1, -1} }, + {IMM_HINTS, {0, 4}, {-1, -1} }, + {IMM_I13, {5, 17}, {-1, -1} }, + {IMM_IDXS, {18, 18}, {-1, -1} }, + {IMM_IDXM, {18, 19}, {-1, -1} }, + {IMM_IDXL, {18, 20}, {-1, -1} }, + {IMM_IDXLL, {18, 21}, {-1, -1} }, + {IMM_LEVEL, {10, 17}, {-1, -1} }, + {IMM_LSBD, {10, 15}, {-1, -1} }, + {IMM_LSBW, {10, 14}, {-1, -1} }, + {IMM_MODE, {5, 9}, {-1, -1} }, + {IMM_MSBD, {16, 21}, {-1, -1} }, + {IMM_MSBW, {16, 20}, {-1, -1} }, + {IMM_OFFS, {10, 25}, {-1, -1} }, + {IMM_OFFL, {10, 25}, {0, 4} }, + {IMM_OFFLL, {10, 25}, {0, 9} }, + {OPD_OPCACHE, {0, 4}, {-1, -1} }, + {IMM_OPX86, {5, 9}, {-1, -1} }, + {IMM_PTR, {5, 7}, {-1, -1} }, + {GPR_RD, {0, 4}, {-1, -1} }, + {GPR_RJ, {5, 9}, {-1, -1} }, + {GPR_RK, {10, 14}, {-1, -1} }, + {IMM_SA2, {15, 16}, {-1, -1} }, + {IMM_SA3, {15, 17}, {-1, -1} }, + {SCR_SD, {0, 1}, {-1, -1} }, + {IMM_SEQ, {10, 17}, {-1, -1} }, + {IMM_SI10, {10, 19}, {-1, -1} }, + {IMM_SI11, {10, 20}, {-1, -1} }, + {IMM_SI12, {10, 21}, {-1, -1} }, + {IMM_SI14, {10, 23}, {-1, -1} }, + {IMM_SI16, {10, 25}, {-1, -1} }, + {IMM_SI20, {5, 24}, {-1, -1} }, + {IMM_SI5, {10, 14}, {-1, -1} }, + {IMM_SI8, {10, 17}, {-1, -1} }, + {IMM_SI9, {10, 18}, {-1, -1} }, + {SCR_SJ, {5, 6}, {-1, -1} }, + {IMM_UI1, {10, 10}, {-1, -1} }, + {IMM_UI12, {10, 21}, {-1, -1} }, + {IMM_UI2, {10, 11}, {-1, -1} }, + {IMM_UI3, {10, 12}, {-1, -1} }, + {IMM_UI4, {10, 13}, {-1, -1} }, + {IMM_UI5H, {15, 19}, {-1, -1} }, + {IMM_UI5L, {10, 14}, {-1, -1} }, + {IMM_UI6, {10, 15}, {-1, -1} }, + {IMM_UI7, {10, 16}, {-1, -1} }, + {IMM_UI8, {10, 17}, {-1, -1} }, + {FPR_VA, {15, 19}, {-1, -1} }, + {FPR_VD, {0, 4}, {-1, -1} }, + {FPR_VJ, {5, 9}, {-1, -1} }, + {FPR_VK, {10, 14}, {-1, -1} }, + {FPR_XA, {15, 19}, {-1, -1} }, + {FPR_XD, {0, 4}, {-1, -1} }, + {FPR_XJ, {5, 9}, {-1, -1} }, + {FPR_XK, {10, 14}, {-1, -1} }, +}; + +const GM_LA_OPCODE_FORMAT lisa_format_table[] = { + {LISA_INVALID, 0x0, {OPD_INVALID}}, + {LISA_ILL, 0xffffffff, {OPD_INVALID}}, + {LISA_LABEL, 0x0, {OPD_INVALID}}, + {LISA_X86_INST, 0x0, {OPD_INVALID}}, + {LISA_DUP, 0x0, {OPD_INVALID}}, + {LISA_MOV64, 0x0, {OPD_INVALID}}, + {LISA_MOV32_SX, 0x0, {OPD_INVALID}}, + {LISA_MOV32_ZX, 0x0, {OPD_INVALID}}, + {LISA_CLR_H32, 0x0, {OPD_INVALID}}, + {LISA_ADD, 0x0, {OPD_INVALID}}, + {LISA_SUB, 0x0, {OPD_INVALID}}, + {LISA_ADDI_ADDRX, 0x0, {OPD_INVALID}}, + {LISA_LOAD_ADDRX, 0x0, {OPD_INVALID}}, + {LISA_STORE_ADDRX, 0x0, {OPD_INVALID}}, + {LISA_GR2SCR, 0x00000800, {SCR_SD, GPR_RJ}}, + {LISA_SCR2GR, 0x00000c00, {GPR_RD, SCR_SJ}}, + {LISA_CLO_W, 0x00001000, {GPR_RD, GPR_RJ}}, + {LISA_CLZ_W, 0x00001400, {GPR_RD, GPR_RJ}}, + {LISA_CTO_W, 0x00001800, {GPR_RD, GPR_RJ}}, + {LISA_CTZ_W, 0x00001c00, {GPR_RD, GPR_RJ}}, + {LISA_CLO_D, 0x00002000, {GPR_RD, GPR_RJ}}, + {LISA_CLZ_D, 0x00002400, {GPR_RD, GPR_RJ}}, + {LISA_CTO_D, 0x00002800, {GPR_RD, GPR_RJ}}, + {LISA_CTZ_D, 0x00002c00, {GPR_RD, GPR_RJ}}, + {LISA_REVB_2H, 0x00003000, {GPR_RD, GPR_RJ}}, + {LISA_REVB_4H, 0x00003400, {GPR_RD, GPR_RJ}}, + {LISA_REVB_2W, 0x00003800, {GPR_RD, GPR_RJ}}, + {LISA_REVB_D, 0x00003c00, {GPR_RD, GPR_RJ}}, + {LISA_REVH_2W, 0x00004000, {GPR_RD, GPR_RJ}}, + {LISA_REVH_D, 0x00004400, {GPR_RD, GPR_RJ}}, + {LISA_BITREV_4B, 0x00004800, {GPR_RD, GPR_RJ}}, + {LISA_BITREV_8B, 0x00004c00, {GPR_RD, GPR_RJ}}, + {LISA_BITREV_W, 0x00005000, {GPR_RD, GPR_RJ}}, + {LISA_BITREV_D, 0x00005400, {GPR_RD, GPR_RJ}}, + {LISA_EXT_W_H, 0x00005800, {GPR_RD, GPR_RJ}}, + {LISA_EXT_W_B, 0x00005c00, {GPR_RD, GPR_RJ}}, + {LISA_RDTIMEL_W, 0x00006000, {GPR_RD, GPR_RJ}}, + {LISA_RDTIMEH_W, 0x00006400, {GPR_RD, GPR_RJ}}, + {LISA_RDTIME_D, 0x00006800, {GPR_RD, GPR_RJ}}, + {LISA_CPUCFG, 0x00006c00, {GPR_RD, GPR_RJ}}, + {LISA_X86MTTOP, 0x00007000, {IMM_PTR}}, + {LISA_X86MFTOP, 0x00007400, {GPR_RD}}, + {LISA_X86LOOPE, 0x00007800, {GPR_RD, GPR_RJ}}, + {LISA_X86LOOPNE, 0x00007c00, {GPR_RD, GPR_RJ}}, + {LISA_X86INC_B, 0x00008000, {GPR_RJ}}, + {LISA_X86INC_H, 0x00008001, {GPR_RJ}}, + {LISA_X86INC_W, 0x00008002, {GPR_RJ}}, + {LISA_X86INC_D, 0x00008003, {GPR_RJ}}, + {LISA_X86DEC_B, 0x00008004, {GPR_RJ}}, + {LISA_X86DEC_H, 0x00008005, {GPR_RJ}}, + {LISA_X86DEC_W, 0x00008006, {GPR_RJ}}, + {LISA_X86DEC_D, 0x00008007, {GPR_RJ}}, + {LISA_X86SETTM, 0x00008008, {}}, + {LISA_X86CLRTM, 0x00008028, {}}, + {LISA_X86INCTOP, 0x00008009, {}}, + {LISA_X86DECTOP, 0x00008029, {}}, + {LISA_ASRTLE_D, 0x00010000, {GPR_RJ, GPR_RK}}, + {LISA_ASRTGT_D, 0x00018000, {GPR_RJ, GPR_RK}}, + {LISA_ALSL_W, 0x00040000, {GPR_RD, GPR_RJ, GPR_RK, IMM_SA2}}, + {LISA_ALSL_WU, 0x00060000, {GPR_RD, GPR_RJ, GPR_RK, IMM_SA2}}, + {LISA_BYTEPICK_W, 0x00080000, {GPR_RD, GPR_RJ, GPR_RK, IMM_SA2}}, + {LISA_BYTEPICK_D, 0x000c0000, {GPR_RD, GPR_RJ, GPR_RK, IMM_SA3}}, + {LISA_ADD_W, 0x00100000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ADD_D, 0x00108000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SUB_W, 0x00110000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SUB_D, 0x00118000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SLT, 0x00120000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SLTU, 0x00128000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MASKEQZ, 0x00130000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MASKNEZ, 0x00138000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_NOR, 0x00140000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_AND, 0x00148000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_OR, 0x00150000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_XOR, 0x00158000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ORN, 0x00160000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ANDN, 0x00168000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SLL_W, 0x00170000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SRL_W, 0x00178000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SRA_W, 0x00180000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SLL_D, 0x00188000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SRL_D, 0x00190000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SRA_D, 0x00198000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ROTR_B, 0x001a0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ROTR_H, 0x001a8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ROTR_W, 0x001b0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ROTR_D, 0x001b8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MUL_W, 0x001c0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MULH_W, 0x001c8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MULH_WU, 0x001d0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MUL_D, 0x001d8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MULH_D, 0x001e0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MULH_DU, 0x001e8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MULW_D_W, 0x001f0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MULW_D_WU, 0x001f8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_DIV_W, 0x00200000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MOD_W, 0x00208000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_DIV_WU, 0x00210000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MOD_WU, 0x00218000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_DIV_D, 0x00220000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MOD_D, 0x00228000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_DIV_DU, 0x00230000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_MOD_DU, 0x00238000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_CRC_W_B_W, 0x00240000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_CRC_W_H_W, 0x00248000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_CRC_W_W_W, 0x00250000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_CRC_W_D_W, 0x00258000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_CRCC_W_B_W, 0x00260000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_CRCC_W_H_W, 0x00268000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_CRCC_W_W_W, 0x00270000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_CRCC_W_D_W, 0x00278000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ADDU12I_W, 0x00290000, {GPR_RD, GPR_RJ, IMM_SI5}}, + {LISA_ADDU12I_D, 0x00298000, {GPR_RD, GPR_RJ, IMM_SI5}}, + {LISA_BREAK, 0x002a0000, {IMM_CODE}}, + {LISA_DBGCALL, 0x002a8000, {IMM_CODE}}, + {LISA_SYSCALL, 0x002b0000, {IMM_CODE}}, + {LISA_HYPCALL, 0x002b8000, {IMM_CODE}}, + {LISA_ALSL_D, 0x002c0000, {GPR_RD, GPR_RJ, GPR_RK, IMM_SA2}}, + {LISA_ADC_B, 0x00300000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ADC_H, 0x00308000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ADC_W, 0x00310000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ADC_D, 0x00318000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SBC_B, 0x00320000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SBC_H, 0x00328000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SBC_W, 0x00330000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_SBC_D, 0x00338000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_RCR_B, 0x00340000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_RCR_H, 0x00348000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_RCR_W, 0x00350000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_RCR_D, 0x00358000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_ARMMOVE, 0x00364000, {GPR_RD, GPR_RJ, IMM_CONDH}}, + {LISA_SETX86J, 0x00368000, {GPR_RD, IMM_CONDH}}, + {LISA_SETARMJ, 0x0036c000, {GPR_RD, IMM_CONDH}}, + {LISA_ARMADD_W, 0x00370010, {GPR_RJ, GPR_RK, IMM_CONDL}}, + {LISA_ARMSUB_W, 0x00378010, {GPR_RJ, GPR_RK, IMM_CONDL}}, + {LISA_ARMADC_W, 0x00380010, {GPR_RJ, GPR_RK, IMM_CONDL}}, + {LISA_ARMSBC_W, 0x00388010, {GPR_RJ, GPR_RK, IMM_CONDL}}, + {LISA_ARMAND_W, 0x00390010, {GPR_RJ, GPR_RK, IMM_CONDL}}, + {LISA_ARMOR_W, 0x00398010, {GPR_RJ, GPR_RK, IMM_CONDL}}, + {LISA_ARMXOR_W, 0x003a0010, {GPR_RJ, GPR_RK, IMM_CONDL}}, + {LISA_ARMSLL_W, 0x003a8010, {GPR_RJ, GPR_RK, IMM_CONDL}}, + {LISA_ARMSRL_W, 0x003b0010, {GPR_RJ, GPR_RK, IMM_CONDL}}, + {LISA_ARMSRA_W, 0x003b8010, {GPR_RJ, GPR_RK, IMM_CONDL}}, + {LISA_ARMROTR_W, 0x003c0010, {GPR_RJ, GPR_RK, IMM_CONDL}}, + {LISA_ARMSLLI_W, 0x003c8010, {GPR_RJ, IMM_UI5L, IMM_CONDL}}, + {LISA_ARMSRLI_W, 0x003d0010, {GPR_RJ, IMM_UI5L, IMM_CONDL}}, + {LISA_ARMSRAI_W, 0x003d8010, {GPR_RJ, IMM_UI5L, IMM_CONDL}}, + {LISA_ARMROTRI_W, 0x003e0010, {GPR_RJ, IMM_UI5L, IMM_CONDL}}, + {LISA_X86MUL_B, 0x003e8000, {GPR_RJ, GPR_RK}}, + {LISA_X86MUL_H, 0x003e8001, {GPR_RJ, GPR_RK}}, + {LISA_X86MUL_W, 0x003e8002, {GPR_RJ, GPR_RK}}, + {LISA_X86MUL_D, 0x003e8003, {GPR_RJ, GPR_RK}}, + {LISA_X86MUL_BU, 0x003e8004, {GPR_RJ, GPR_RK}}, + {LISA_X86MUL_HU, 0x003e8005, {GPR_RJ, GPR_RK}}, + {LISA_X86MUL_WU, 0x003e8006, {GPR_RJ, GPR_RK}}, + {LISA_X86MUL_DU, 0x003e8007, {GPR_RJ, GPR_RK}}, + {LISA_X86ADD_WU, 0x003f0000, {GPR_RJ, GPR_RK}}, + {LISA_X86ADD_DU, 0x003f0001, {GPR_RJ, GPR_RK}}, + {LISA_X86SUB_WU, 0x003f0002, {GPR_RJ, GPR_RK}}, + {LISA_X86SUB_DU, 0x003f0003, {GPR_RJ, GPR_RK}}, + {LISA_X86ADD_B, 0x003f0004, {GPR_RJ, GPR_RK}}, + {LISA_X86ADD_H, 0x003f0005, {GPR_RJ, GPR_RK}}, + {LISA_X86ADD_W, 0x003f0006, {GPR_RJ, GPR_RK}}, + {LISA_X86ADD_D, 0x003f0007, {GPR_RJ, GPR_RK}}, + {LISA_X86SUB_B, 0x003f0008, {GPR_RJ, GPR_RK}}, + {LISA_X86SUB_H, 0x003f0009, {GPR_RJ, GPR_RK}}, + {LISA_X86SUB_W, 0x003f000a, {GPR_RJ, GPR_RK}}, + {LISA_X86SUB_D, 0x003f000b, {GPR_RJ, GPR_RK}}, + {LISA_X86ADC_B, 0x003f000c, {GPR_RJ, GPR_RK}}, + {LISA_X86ADC_H, 0x003f000d, {GPR_RJ, GPR_RK}}, + {LISA_X86ADC_W, 0x003f000e, {GPR_RJ, GPR_RK}}, + {LISA_X86ADC_D, 0x003f000f, {GPR_RJ, GPR_RK}}, + {LISA_X86SBC_B, 0x003f0010, {GPR_RJ, GPR_RK}}, + {LISA_X86SBC_H, 0x003f0011, {GPR_RJ, GPR_RK}}, + {LISA_X86SBC_W, 0x003f0012, {GPR_RJ, GPR_RK}}, + {LISA_X86SBC_D, 0x003f0013, {GPR_RJ, GPR_RK}}, + {LISA_X86SLL_B, 0x003f0014, {GPR_RJ, GPR_RK}}, + {LISA_X86SLL_H, 0x003f0015, {GPR_RJ, GPR_RK}}, + {LISA_X86SLL_W, 0x003f0016, {GPR_RJ, GPR_RK}}, + {LISA_X86SLL_D, 0x003f0017, {GPR_RJ, GPR_RK}}, + {LISA_X86SRL_B, 0x003f0018, {GPR_RJ, GPR_RK}}, + {LISA_X86SRL_H, 0x003f0019, {GPR_RJ, GPR_RK}}, + {LISA_X86SRL_W, 0x003f001a, {GPR_RJ, GPR_RK}}, + {LISA_X86SRL_D, 0x003f001b, {GPR_RJ, GPR_RK}}, + {LISA_X86SRA_B, 0x003f001c, {GPR_RJ, GPR_RK}}, + {LISA_X86SRA_H, 0x003f001d, {GPR_RJ, GPR_RK}}, + {LISA_X86SRA_W, 0x003f001e, {GPR_RJ, GPR_RK}}, + {LISA_X86SRA_D, 0x003f001f, {GPR_RJ, GPR_RK}}, + {LISA_X86ROTR_B, 0x003f8000, {GPR_RJ, GPR_RK}}, + {LISA_X86ROTR_H, 0x003f8001, {GPR_RJ, GPR_RK}}, + {LISA_X86ROTR_D, 0x003f8002, {GPR_RJ, GPR_RK}}, + {LISA_X86ROTR_W, 0x003f8003, {GPR_RJ, GPR_RK}}, + {LISA_X86ROTL_B, 0x003f8004, {GPR_RJ, GPR_RK}}, + {LISA_X86ROTL_H, 0x003f8005, {GPR_RJ, GPR_RK}}, + {LISA_X86ROTL_W, 0x003f8006, {GPR_RJ, GPR_RK}}, + {LISA_X86ROTL_D, 0x003f8007, {GPR_RJ, GPR_RK}}, + {LISA_X86RCR_B, 0x003f8008, {GPR_RJ, GPR_RK}}, + {LISA_X86RCR_H, 0x003f8009, {GPR_RJ, GPR_RK}}, + {LISA_X86RCR_W, 0x003f800a, {GPR_RJ, GPR_RK}}, + {LISA_X86RCR_D, 0x003f800b, {GPR_RJ, GPR_RK}}, + {LISA_X86RCL_B, 0x003f800c, {GPR_RJ, GPR_RK}}, + {LISA_X86RCL_H, 0x003f800d, {GPR_RJ, GPR_RK}}, + {LISA_X86RCL_W, 0x003f800e, {GPR_RJ, GPR_RK}}, + {LISA_X86RCL_D, 0x003f800f, {GPR_RJ, GPR_RK}}, + {LISA_X86AND_B, 0x003f8010, {GPR_RJ, GPR_RK}}, + {LISA_X86AND_H, 0x003f8011, {GPR_RJ, GPR_RK}}, + {LISA_X86AND_W, 0x003f8012, {GPR_RJ, GPR_RK}}, + {LISA_X86AND_D, 0x003f8013, {GPR_RJ, GPR_RK}}, + {LISA_X86OR_B, 0x003f8014, {GPR_RJ, GPR_RK}}, + {LISA_X86OR_H, 0x003f8015, {GPR_RJ, GPR_RK}}, + {LISA_X86OR_W, 0x003f8016, {GPR_RJ, GPR_RK}}, + {LISA_X86OR_D, 0x003f8017, {GPR_RJ, GPR_RK}}, + {LISA_X86XOR_B, 0x003f8018, {GPR_RJ, GPR_RK}}, + {LISA_X86XOR_H, 0x003f8019, {GPR_RJ, GPR_RK}}, + {LISA_X86XOR_W, 0x003f801a, {GPR_RJ, GPR_RK}}, + {LISA_X86XOR_D, 0x003f801b, {GPR_RJ, GPR_RK}}, + {LISA_ARMNOT_W, 0x003fc01c, {GPR_RJ, IMM_CONDH}}, + {LISA_ARMMOV_W, 0x003fc01d, {GPR_RJ, IMM_CONDH}}, + {LISA_ARMMOV_D, 0x003fc01e, {GPR_RJ, IMM_CONDH}}, + {LISA_ARMRRX_W, 0x003fc01f, {GPR_RJ, IMM_CONDH}}, + {LISA_SLLI_W, 0x00408000, {GPR_RD, GPR_RJ, IMM_UI5L}}, + {LISA_SLLI_D, 0x00410000, {GPR_RD, GPR_RJ, IMM_UI6}}, + {LISA_SRLI_W, 0x00448000, {GPR_RD, GPR_RJ, IMM_UI5L}}, + {LISA_SRLI_D, 0x00450000, {GPR_RD, GPR_RJ, IMM_UI6}}, + {LISA_SRAI_W, 0x00488000, {GPR_RD, GPR_RJ, IMM_UI5L}}, + {LISA_SRAI_D, 0x00490000, {GPR_RD, GPR_RJ, IMM_UI6}}, + {LISA_ROTRI_B, 0x004c2000, {GPR_RD, GPR_RJ, IMM_UI3}}, + {LISA_ROTRI_H, 0x004c4000, {GPR_RD, GPR_RJ, IMM_UI4}}, + {LISA_ROTRI_W, 0x004c8000, {GPR_RD, GPR_RJ, IMM_UI5L}}, + {LISA_ROTRI_D, 0x004d0000, {GPR_RD, GPR_RJ, IMM_UI6}}, + {LISA_RCRI_B, 0x00502000, {GPR_RD, GPR_RJ, IMM_UI3}}, + {LISA_RCRI_H, 0x00504000, {GPR_RD, GPR_RJ, IMM_UI4}}, + {LISA_RCRI_W, 0x00508000, {GPR_RD, GPR_RJ, IMM_UI5L}}, + {LISA_RCRI_D, 0x00510000, {GPR_RD, GPR_RJ, IMM_UI6}}, + {LISA_X86SLLI_B, 0x00542000, {GPR_RJ, IMM_UI3}}, + {LISA_X86SLLI_H, 0x00544001, {GPR_RJ, IMM_UI4}}, + {LISA_X86SLLI_W, 0x00548002, {GPR_RJ, IMM_UI5L}}, + {LISA_X86SLLI_D, 0x00550003, {GPR_RJ, IMM_UI6}}, + {LISA_X86SRLI_B, 0x00542004, {GPR_RJ, IMM_UI3}}, + {LISA_X86SRLI_H, 0x00544005, {GPR_RJ, IMM_UI4}}, + {LISA_X86SRLI_W, 0x00548006, {GPR_RJ, IMM_UI5L}}, + {LISA_X86SRLI_D, 0x00550007, {GPR_RJ, IMM_UI6}}, + {LISA_X86SRAI_B, 0x00542008, {GPR_RJ, IMM_UI3}}, + {LISA_X86SRAI_H, 0x00544009, {GPR_RJ, IMM_UI4}}, + {LISA_X86SRAI_W, 0x0054800a, {GPR_RJ, IMM_UI5L}}, + {LISA_X86SRAI_D, 0x0055000b, {GPR_RJ, IMM_UI6}}, + {LISA_X86ROTRI_B, 0x0054200c, {GPR_RJ, IMM_UI3}}, + {LISA_X86ROTRI_H, 0x0054400d, {GPR_RJ, IMM_UI4}}, + {LISA_X86ROTRI_W, 0x0054800e, {GPR_RJ, IMM_UI5L}}, + {LISA_X86ROTRI_D, 0x0055000f, {GPR_RJ, IMM_UI6}}, + {LISA_X86RCRI_B, 0x00542010, {GPR_RJ, IMM_UI3}}, + {LISA_X86RCRI_H, 0x00544011, {GPR_RJ, IMM_UI4}}, + {LISA_X86RCRI_W, 0x00548012, {GPR_RJ, IMM_UI5L}}, + {LISA_X86RCRI_D, 0x00550013, {GPR_RJ, IMM_UI6}}, + {LISA_X86ROTLI_B, 0x00542014, {GPR_RJ, IMM_UI3}}, + {LISA_X86ROTLI_H, 0x00544015, {GPR_RJ, IMM_UI4}}, + {LISA_X86ROTLI_W, 0x00548016, {GPR_RJ, IMM_UI5L}}, + {LISA_X86ROTLI_D, 0x00550017, {GPR_RJ, IMM_UI6}}, + {LISA_X86RCLI_B, 0x00542018, {GPR_RJ, IMM_UI3}}, + {LISA_X86RCLI_H, 0x00544019, {GPR_RJ, IMM_UI4}}, + {LISA_X86RCLI_W, 0x0054801a, {GPR_RJ, IMM_UI5L}}, + {LISA_X86RCLI_D, 0x0055001b, {GPR_RJ, IMM_UI6}}, + {LISA_X86SETTAG, 0x00580000, {GPR_RD, IMM_OPX86, IMM_UI8}}, + {LISA_X86MFFLAG, 0x005c0000, {GPR_RD, IMM_UI8}}, + {LISA_X86MTFLAG, 0x005c0020, {GPR_RD, IMM_UI8}}, + {LISA_ARMMFFLAG, 0x005c0040, {GPR_RD, IMM_UI8}}, + {LISA_ARMMTFLAG, 0x005c0060, {GPR_RD, IMM_UI8}}, + {LISA_BSTRINS_W, 0x00600000, {GPR_RD, GPR_RJ, IMM_MSBW, IMM_LSBW}}, + {LISA_BSTRPICK_W, 0x00608000, {GPR_RD, GPR_RJ, IMM_MSBW, IMM_LSBW}}, + {LISA_BSTRINS_D, 0x00800000, {GPR_RD, GPR_RJ, IMM_MSBD, IMM_LSBD}}, + {LISA_BSTRPICK_D, 0x00c00000, {GPR_RD, GPR_RJ, IMM_MSBD, IMM_LSBD}}, + {LISA_SLTI, 0x02000000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_SLTUI, 0x02400000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_ADDI_W, 0x02800000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_ADDI_D, 0x02c00000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_LU52I_D, 0x03000000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_ANDI, 0x03400000, {GPR_RD, GPR_RJ, IMM_UI12}}, + {LISA_ORI, 0x03800000, {GPR_RD, GPR_RJ, IMM_UI12}}, + {LISA_XORI, 0x03c00000, {GPR_RD, GPR_RJ, IMM_UI12}}, + {LISA_ADDU16I_D, 0x10000000, {GPR_RD, GPR_RJ, IMM_SI16}}, + {LISA_LU12I_W, 0x14000000, {GPR_RD, IMM_SI20}}, + {LISA_LU32I_D, 0x16000000, {GPR_RD, IMM_SI20}}, + {LISA_PCADDI, 0x18000000, {GPR_RD, IMM_SI20}}, + {LISA_PCALAU12I, 0x1a000000, {GPR_RD, IMM_SI20}}, + {LISA_PCADDU12I, 0x1c000000, {GPR_RD, IMM_SI20}}, + {LISA_PCADDU18I, 0x1e000000, {GPR_RD, IMM_SI20}}, + {LISA_LL_W, 0x20000000, {GPR_RD, GPR_RJ, IMM_SI14}}, + {LISA_SC_W, 0x21000000, {GPR_RD, GPR_RJ, IMM_SI14}}, + {LISA_LL_D, 0x22000000, {GPR_RD, GPR_RJ, IMM_SI14}}, + {LISA_SC_D, 0x23000000, {GPR_RD, GPR_RJ, IMM_SI14}}, + {LISA_LDPTR_W, 0x24000000, {GPR_RD, GPR_RJ, IMM_SI14}}, + {LISA_STPTR_W, 0x25000000, {GPR_RD, GPR_RJ, IMM_SI14}}, + {LISA_LDPTR_D, 0x26000000, {GPR_RD, GPR_RJ, IMM_SI14}}, + {LISA_STPTR_D, 0x27000000, {GPR_RD, GPR_RJ, IMM_SI14}}, + {LISA_LD_B, 0x28000000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_LD_H, 0x28400000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_LD_W, 0x28800000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_LD_D, 0x28c00000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_ST_B, 0x29000000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_ST_H, 0x29400000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_ST_W, 0x29800000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_ST_D, 0x29c00000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_LD_BU, 0x2a000000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_LD_HU, 0x2a400000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_LD_WU, 0x2a800000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_PRELD, 0x2ac00000, {IMM_HINTS, GPR_RJ, IMM_SI12}}, + {LISA_FLD_S, 0x2b000000, {FPR_FD, GPR_RJ, IMM_SI12}}, + {LISA_FST_S, 0x2b400000, {FPR_FD, GPR_RJ, IMM_SI12}}, + {LISA_FLD_D, 0x2b800000, {FPR_FD, GPR_RJ, IMM_SI12}}, + {LISA_FST_D, 0x2bc00000, {FPR_FD, GPR_RJ, IMM_SI12}}, + {LISA_VLD, 0x2c000000, {FPR_VD, GPR_RJ, IMM_SI12}}, + {LISA_VST, 0x2c400000, {FPR_VD, GPR_RJ, IMM_SI12}}, + {LISA_XVLD, 0x2c800000, {FPR_XD, GPR_RJ, IMM_SI12}}, + {LISA_XVST, 0x2cc00000, {FPR_XD, GPR_RJ, IMM_SI12}}, + {LISA_LDL_W, 0x2e000000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_LDR_W, 0x2e400000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_LDL_D, 0x2e800000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_LDR_D, 0x2ec00000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_STL_W, 0x2f000000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_STR_W, 0x2f400000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_STL_D, 0x2f800000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_STR_D, 0x2fc00000, {GPR_RD, GPR_RJ, IMM_SI12}}, + {LISA_VLDREPL_D, 0x30100000, {FPR_VD, GPR_RJ, IMM_SI9}}, + {LISA_VLDREPL_W, 0x30200000, {FPR_VD, GPR_RJ, IMM_SI10}}, + {LISA_VLDREPL_H, 0x30400000, {FPR_VD, GPR_RJ, IMM_SI11}}, + {LISA_VLDREPL_B, 0x30800000, {FPR_VD, GPR_RJ, IMM_SI12}}, + {LISA_VSTELM_D, 0x31100000, {FPR_VD, GPR_RJ, IMM_SI8, IMM_IDXS}}, + {LISA_VSTELM_W, 0x31200000, {FPR_VD, GPR_RJ, IMM_SI8, IMM_IDXM}}, + {LISA_VSTELM_H, 0x31400000, {FPR_VD, GPR_RJ, IMM_SI8, IMM_IDXL}}, + {LISA_VSTELM_B, 0x31800000, {FPR_VD, GPR_RJ, IMM_SI8, IMM_IDXLL}}, + {LISA_XVLDREPL_D, 0x32100000, {FPR_XD, GPR_RJ, IMM_SI9}}, + {LISA_XVLDREPL_W, 0x32200000, {FPR_XD, GPR_RJ, IMM_SI10}}, + {LISA_XVLDREPL_H, 0x32400000, {FPR_XD, GPR_RJ, IMM_SI11}}, + {LISA_XVLDREPL_B, 0x32800000, {FPR_XD, GPR_RJ, IMM_SI12}}, + {LISA_XVSTELM_D, 0x33100000, {FPR_XD, GPR_RJ, IMM_SI8, IMM_IDXS}}, + {LISA_XVSTELM_W, 0x33200000, {FPR_XD, GPR_RJ, IMM_SI8, IMM_IDXM}}, + {LISA_XVSTELM_H, 0x33400000, {FPR_XD, GPR_RJ, IMM_SI8, IMM_IDXL}}, + {LISA_XVSTELM_B, 0x33800000, {FPR_XD, GPR_RJ, IMM_SI8, IMM_IDXLL}}, + {LISA_LDX_B, 0x38000000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDX_H, 0x38040000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDX_W, 0x38080000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDX_D, 0x380c0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STX_B, 0x38100000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STX_H, 0x38140000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STX_W, 0x38180000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STX_D, 0x381c0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDX_BU, 0x38200000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDX_HU, 0x38240000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDX_WU, 0x38280000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_PRELDX, 0x382c0000, {IMM_HINTS, GPR_RJ, GPR_RK}}, + {LISA_FLDX_S, 0x38300000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_FLDX_D, 0x38340000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_FSTX_S, 0x38380000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_FSTX_D, 0x383c0000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_VLDX, 0x38400000, {FPR_VD, GPR_RJ, GPR_RK}}, + {LISA_VSTX, 0x38440000, {FPR_VD, GPR_RJ, GPR_RK}}, + {LISA_XVLDX, 0x38480000, {FPR_XD, GPR_RJ, GPR_RK}}, + {LISA_XVSTX, 0x384c0000, {FPR_XD, GPR_RJ, GPR_RK}}, + {LISA_AMSWAP_W, 0x38600000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMSWAP_D, 0x38608000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMADD_W, 0x38610000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMADD_D, 0x38618000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMAND_W, 0x38620000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMAND_D, 0x38628000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMOR_W, 0x38630000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMOR_D, 0x38638000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMXOR_W, 0x38640000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMXOR_D, 0x38648000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMAX_W, 0x38650000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMAX_D, 0x38658000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMIN_W, 0x38660000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMIN_D, 0x38668000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMAX_WU, 0x38670000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMAX_DU, 0x38678000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMIN_WU, 0x38680000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMIN_DU, 0x38688000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMSWAP_DB_W, 0x38690000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMSWAP_DB_D, 0x38698000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMADD_DB_W, 0x386a0000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMADD_DB_D, 0x386a8000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMAND_DB_W, 0x386b0000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMAND_DB_D, 0x386b8000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMOR_DB_W, 0x386c0000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMOR_DB_D, 0x386c8000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMXOR_DB_W, 0x386d0000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMXOR_DB_D, 0x386d8000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMAX_DB_W, 0x386e0000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMAX_DB_D, 0x386e8000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMIN_DB_W, 0x386f0000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMIN_DB_D, 0x386f8000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMAX_DB_WU, 0x38700000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMAX_DB_DU, 0x38708000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMIN_DB_WU, 0x38710000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_AMMIN_DB_DU, 0x38718000, {GPR_RD, GPR_RK, GPR_RJ}}, + {LISA_DBAR, 0x38720000, {IMM_HINTL}}, + {LISA_IBAR, 0x38728000, {IMM_HINTL}}, + {LISA_FLDGT_S, 0x38740000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_FLDGT_D, 0x38748000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_FLDLE_S, 0x38750000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_FLDLE_D, 0x38758000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_FSTGT_S, 0x38760000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_FSTGT_D, 0x38768000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_FSTLE_S, 0x38770000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_FSTLE_D, 0x38778000, {FPR_FD, GPR_RJ, GPR_RK}}, + {LISA_LDGT_B, 0x38780000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDGT_H, 0x38788000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDGT_W, 0x38790000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDGT_D, 0x38798000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDLE_B, 0x387a0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDLE_H, 0x387a8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDLE_W, 0x387b0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_LDLE_D, 0x387b8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STGT_B, 0x387c0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STGT_H, 0x387c8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STGT_W, 0x387d0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STGT_D, 0x387d8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STLE_B, 0x387e0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STLE_H, 0x387e8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STLE_W, 0x387f0000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_STLE_D, 0x387f8000, {GPR_RD, GPR_RJ, GPR_RK}}, + {LISA_BEQZ, 0x40000000, {GPR_RJ, IMM_OFFL}}, + {LISA_BNEZ, 0x44000000, {GPR_RJ, IMM_OFFL}}, + {LISA_BCEQZ, 0x48000000, {FCC_CJ, IMM_OFFL}}, + {LISA_BCNEZ, 0x48000100, {FCC_CJ, IMM_OFFL}}, + {LISA_JISCR0, 0x48000200, {IMM_OFFL}}, + {LISA_JISCR1, 0x48000300, {IMM_OFFL}}, + {LISA_JIRL, 0x4c000000, {GPR_RD, GPR_RJ, IMM_OFFS}}, + {LISA_B, 0x50000000, {IMM_OFFLL}}, + {LISA_BL, 0x54000000, {IMM_OFFLL}}, + {LISA_BEQ, 0x58000000, {GPR_RJ, GPR_RD, IMM_OFFS}}, + {LISA_BNE, 0x5c000000, {GPR_RJ, GPR_RD, IMM_OFFS}}, + {LISA_BLT, 0x60000000, {GPR_RJ, GPR_RD, IMM_OFFS}}, + {LISA_BGE, 0x64000000, {GPR_RJ, GPR_RD, IMM_OFFS}}, + {LISA_BLTU, 0x68000000, {GPR_RJ, GPR_RD, IMM_OFFS}}, + {LISA_BGEU, 0x6c000000, {GPR_RJ, GPR_RD, IMM_OFFS}}, + {LISA_FADD_S, 0x01008000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FADD_D, 0x01010000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FSUB_S, 0x01028000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FSUB_D, 0x01030000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FMUL_S, 0x01048000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FMUL_D, 0x01050000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FDIV_S, 0x01068000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FDIV_D, 0x01070000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FMAX_S, 0x01088000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FMAX_D, 0x01090000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FMIN_S, 0x010a8000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FMIN_D, 0x010b0000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FMAXA_S, 0x010c8000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FMAXA_D, 0x010d0000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FMINA_S, 0x010e8000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FMINA_D, 0x010f0000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FSCALEB_S, 0x01108000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FSCALEB_D, 0x01110000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FCOPYSIGN_S, 0x01128000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FCOPYSIGN_D, 0x01130000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FABS_S, 0x01140400, {FPR_FD, FPR_FJ}}, + {LISA_FABS_D, 0x01140800, {FPR_FD, FPR_FJ}}, + {LISA_FNEG_S, 0x01141400, {FPR_FD, FPR_FJ}}, + {LISA_FNEG_D, 0x01141800, {FPR_FD, FPR_FJ}}, + {LISA_FLOGB_S, 0x01142400, {FPR_FD, FPR_FJ}}, + {LISA_FLOGB_D, 0x01142800, {FPR_FD, FPR_FJ}}, + {LISA_FCLASS_S, 0x01143400, {FPR_FD, FPR_FJ}}, + {LISA_FCLASS_D, 0x01143800, {FPR_FD, FPR_FJ}}, + {LISA_FSQRT_S, 0x01144400, {FPR_FD, FPR_FJ}}, + {LISA_FSQRT_D, 0x01144800, {FPR_FD, FPR_FJ}}, + {LISA_FRECIP_S, 0x01145400, {FPR_FD, FPR_FJ}}, + {LISA_FRECIP_D, 0x01145800, {FPR_FD, FPR_FJ}}, + {LISA_FRSQRT_S, 0x01146400, {FPR_FD, FPR_FJ}}, + {LISA_FRSQRT_D, 0x01146800, {FPR_FD, FPR_FJ}}, + {LISA_FMOV_S, 0x01149400, {FPR_FD, FPR_FJ}}, + {LISA_FMOV_D, 0x01149800, {FPR_FD, FPR_FJ}}, + {LISA_MOVGR2FR_W, 0x0114a400, {FPR_FD, GPR_RJ}}, + {LISA_MOVGR2FR_D, 0x0114a800, {FPR_FD, GPR_RJ}}, + {LISA_MOVGR2FRH_W, 0x0114ac00, {FPR_FD, GPR_RJ}}, + {LISA_MOVFR2GR_S, 0x0114b400, {GPR_RD, FPR_FJ}}, + {LISA_MOVFR2GR_D, 0x0114b800, {GPR_RD, FPR_FJ}}, + {LISA_MOVFRH2GR_S, 0x0114bc00, {GPR_RD, FPR_FJ}}, + {LISA_MOVGR2FCSR, 0x0114c000, {OPD_FCSRL, GPR_RJ}}, + {LISA_MOVFCSR2GR, 0x0114c800, {GPR_RD, OPD_FCSRH}}, + {LISA_MOVFR2CF, 0x0114d000, {FCC_CD, FPR_FJ}}, + {LISA_MOVCF2FR, 0x0114d400, {FPR_FD, FCC_CJ}}, + {LISA_MOVGR2CF, 0x0114d800, {FCC_CD, GPR_RJ}}, + {LISA_MOVCF2GR, 0x0114dc00, {GPR_RD, FCC_CJ}}, + {LISA_FCVT_LD_D, 0x0114e000, {FPR_FD, FPR_FJ}}, + {LISA_FCVT_UD_D, 0x0114e400, {FPR_FD, FPR_FJ}}, + {LISA_FCVT_D_LD, 0x01150000, {FPR_FD, FPR_FJ, FPR_FK}}, + {LISA_FCVT_S_D, 0x01191800, {FPR_FD, FPR_FJ}}, + {LISA_FCVT_D_S, 0x01192400, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRM_W_S, 0x011a0400, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRM_W_D, 0x011a0800, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRM_L_S, 0x011a2400, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRM_L_D, 0x011a2800, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRP_W_S, 0x011a4400, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRP_W_D, 0x011a4800, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRP_L_S, 0x011a6400, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRP_L_D, 0x011a6800, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRZ_W_S, 0x011a8400, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRZ_W_D, 0x011a8800, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRZ_L_S, 0x011aa400, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRZ_L_D, 0x011aa800, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRNE_W_S, 0x011ac400, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRNE_W_D, 0x011ac800, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRNE_L_S, 0x011ae400, {FPR_FD, FPR_FJ}}, + {LISA_FTINTRNE_L_D, 0x011ae800, {FPR_FD, FPR_FJ}}, + {LISA_FTINT_W_S, 0x011b0400, {FPR_FD, FPR_FJ}}, + {LISA_FTINT_W_D, 0x011b0800, {FPR_FD, FPR_FJ}}, + {LISA_FTINT_L_S, 0x011b2400, {FPR_FD, FPR_FJ}}, + {LISA_FTINT_L_D, 0x011b2800, {FPR_FD, FPR_FJ}}, + {LISA_FFINT_S_W, 0x011d1000, {FPR_FD, FPR_FJ}}, + {LISA_FFINT_S_L, 0x011d1800, {FPR_FD, FPR_FJ}}, + {LISA_FFINT_D_W, 0x011d2000, {FPR_FD, FPR_FJ}}, + {LISA_FFINT_D_L, 0x011d2800, {FPR_FD, FPR_FJ}}, + {LISA_FRINT_S, 0x011e4400, {FPR_FD, FPR_FJ}}, + {LISA_FRINT_D, 0x011e4800, {FPR_FD, FPR_FJ}}, + {LISA_FMADD_S, 0x08100000, {FPR_FD, FPR_FJ, FPR_FK, FPR_FA}}, + {LISA_FMADD_D, 0x08200000, {FPR_FD, FPR_FJ, FPR_FK, FPR_FA}}, + {LISA_FMSUB_S, 0x08500000, {FPR_FD, FPR_FJ, FPR_FK, FPR_FA}}, + {LISA_FMSUB_D, 0x08600000, {FPR_FD, FPR_FJ, FPR_FK, FPR_FA}}, + {LISA_FNMADD_S, 0x08900000, {FPR_FD, FPR_FJ, FPR_FK, FPR_FA}}, + {LISA_FNMADD_D, 0x08a00000, {FPR_FD, FPR_FJ, FPR_FK, FPR_FA}}, + {LISA_FNMSUB_S, 0x08d00000, {FPR_FD, FPR_FJ, FPR_FK, FPR_FA}}, + {LISA_FNMSUB_D, 0x08e00000, {FPR_FD, FPR_FJ, FPR_FK, FPR_FA}}, + {LISA_VFMADD_S, 0x09100000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_VFMADD_D, 0x09200000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_VFMSUB_S, 0x09500000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_VFMSUB_D, 0x09600000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_VFNMADD_S, 0x09900000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_VFNMADD_D, 0x09a00000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_VFNMSUB_S, 0x09d00000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_VFNMSUB_D, 0x09e00000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_XVFMADD_S, 0x0a100000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_XVFMADD_D, 0x0a200000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_XVFMSUB_S, 0x0a500000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_XVFMSUB_D, 0x0a600000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_XVFNMADD_S, 0x0a900000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_XVFNMADD_D, 0x0aa00000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_XVFNMSUB_S, 0x0ad00000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_XVFNMSUB_D, 0x0ae00000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_FCMP_COND_S, 0x0c100000, {FCC_CD, FPR_FJ, FPR_FK, IMM_CONDF}}, + {LISA_FCMP_COND_D, 0x0c200000, {FCC_CD, FPR_FJ, FPR_FK, IMM_CONDF}}, + {LISA_VFCMP_COND_S, 0x0c500000, {FPR_VD, FPR_VJ, FPR_VK, IMM_CONDF}}, + {LISA_VFCMP_COND_D, 0x0c600000, {FPR_VD, FPR_VJ, FPR_VK, IMM_CONDF}}, + {LISA_XVFCMP_COND_S, 0x0c900000, {FPR_XD, FPR_XJ, FPR_XK, IMM_CONDF}}, + {LISA_XVFCMP_COND_D, 0x0ca00000, {FPR_XD, FPR_XJ, FPR_XK, IMM_CONDF}}, + {LISA_FSEL, 0x0d000000, {FPR_FD, FPR_FJ, FPR_FK, FCC_CA}}, + {LISA_VBITSEL_V, 0x0d100000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_XVBITSEL_V, 0x0d200000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_VSHUF_B, 0x0d500000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_XVSHUF_B, 0x0d600000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_VEXTR_V, 0x0d900000, {FPR_VD, FPR_VJ, FPR_VK, IMM_UI5H}}, + {LISA_XVEXTR_V, 0x0da00000, {FPR_XD, FPR_XJ, FPR_XK, IMM_UI5H}}, + {LISA_VFMADDSUB_S, 0x0e900000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_VFMADDSUB_D, 0x0ea00000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_VFMSUBADD_S, 0x0ed00000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_VFMSUBADD_D, 0x0ee00000, {FPR_VD, FPR_VJ, FPR_VK, FPR_VA}}, + {LISA_XVFMADDSUB_S, 0x0f100000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_XVFMADDSUB_D, 0x0f200000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_XVFMSUBADD_S, 0x0f500000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_XVFMSUBADD_D, 0x0f600000, {FPR_XD, FPR_XJ, FPR_XK, FPR_XA}}, + {LISA_VSEQ_B, 0x70000000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSEQ_H, 0x70008000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSEQ_W, 0x70010000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSEQ_D, 0x70018000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLE_B, 0x70020000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLE_H, 0x70028000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLE_W, 0x70030000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLE_D, 0x70038000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLE_BU, 0x70040000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLE_HU, 0x70048000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLE_WU, 0x70050000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLE_DU, 0x70058000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLT_B, 0x70060000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLT_H, 0x70068000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLT_W, 0x70070000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLT_D, 0x70078000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLT_BU, 0x70080000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLT_HU, 0x70088000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLT_WU, 0x70090000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLT_DU, 0x70098000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADD_B, 0x700a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADD_H, 0x700a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADD_W, 0x700b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADD_D, 0x700b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUB_B, 0x700c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUB_H, 0x700c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUB_W, 0x700d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUB_D, 0x700d8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDW_H_H_B, 0x700e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDW_W_W_H, 0x700e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDW_D_D_W, 0x700f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDW_H_H_BU, 0x70100000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDW_W_W_HU, 0x70108000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDW_D_D_WU, 0x70110000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBW_H_H_B, 0x70120000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBW_W_W_H, 0x70128000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBW_D_D_W, 0x70130000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBW_H_H_BU, 0x70140000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBW_W_W_HU, 0x70148000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBW_D_D_WU, 0x70150000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADDW_H_H_B, 0x70160000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADDW_W_W_H, 0x70168000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADDW_D_D_W, 0x70170000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADDW_HU_HU_BU, 0x70180000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADDW_WU_WU_HU, 0x70188000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADDW_DU_DU_WU, 0x70190000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUBW_H_H_B, 0x701a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUBW_W_W_H, 0x701a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUBW_D_D_W, 0x701b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUBW_HU_HU_BU, 0x701c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUBW_WU_WU_HU, 0x701c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUBW_DU_DU_WU, 0x701d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_H_B, 0x701e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_W_H, 0x701e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_D_W, 0x701f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_Q_D, 0x701f8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWEV_H_B, 0x70200000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWEV_W_H, 0x70208000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWEV_D_W, 0x70210000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWEV_Q_D, 0x70218000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_H_B, 0x70220000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_W_H, 0x70228000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_D_W, 0x70230000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_Q_D, 0x70238000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWOD_H_B, 0x70240000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWOD_W_H, 0x70248000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWOD_D_W, 0x70250000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWOD_Q_D, 0x70258000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_H_B, 0x70260000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_W_H, 0x70268000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_D_W, 0x70270000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_Q_D, 0x70278000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWL_H_B, 0x70280000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWL_W_H, 0x70288000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWL_D_W, 0x70290000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWL_Q_D, 0x70298000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_H_B, 0x702a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_W_H, 0x702a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_D_W, 0x702b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_Q_D, 0x702b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWH_H_B, 0x702c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWH_W_H, 0x702c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWH_D_W, 0x702d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWH_Q_D, 0x702d8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_H_BU, 0x702e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_W_HU, 0x702e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_D_WU, 0x702f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_Q_DU, 0x702f8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWEV_H_BU, 0x70300000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWEV_W_HU, 0x70308000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWEV_D_WU, 0x70310000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWEV_Q_DU, 0x70318000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_H_BU, 0x70320000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_W_HU, 0x70328000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_D_WU, 0x70330000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_Q_DU, 0x70338000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWOD_H_BU, 0x70340000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWOD_W_HU, 0x70348000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWOD_D_WU, 0x70350000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWOD_Q_DU, 0x70358000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_H_BU, 0x70360000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_W_HU, 0x70368000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_D_WU, 0x70370000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_Q_DU, 0x70378000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWL_H_BU, 0x70380000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWL_W_HU, 0x70388000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWL_D_WU, 0x70390000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWL_Q_DU, 0x70398000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_H_BU, 0x703a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_W_HU, 0x703a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_D_WU, 0x703b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_Q_DU, 0x703b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWH_H_BU, 0x703c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWH_W_HU, 0x703c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWH_D_WU, 0x703d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUBWH_Q_DU, 0x703d8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_H_BU_B, 0x703e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_W_HU_H, 0x703e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_D_WU_W, 0x703f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWEV_Q_DU_D, 0x703f8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_H_BU_B, 0x70400000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_W_HU_H, 0x70408000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_D_WU_W, 0x70410000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWOD_Q_DU_D, 0x70418000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_H_BU_B, 0x70420000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_W_HU_H, 0x70428000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_D_WU_W, 0x70430000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWL_Q_DU_D, 0x70438000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_H_BU_B, 0x70440000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_W_HU_H, 0x70448000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_D_WU_W, 0x70450000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDWH_Q_DU_D, 0x70458000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADD_B, 0x70460000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADD_H, 0x70468000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADD_W, 0x70470000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADD_D, 0x70478000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_B, 0x70480000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_H, 0x70488000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_W, 0x70490000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_D, 0x70498000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADD_BU, 0x704a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADD_HU, 0x704a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADD_WU, 0x704b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADD_DU, 0x704b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_BU, 0x704c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_HU, 0x704c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_WU, 0x704d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_DU, 0x704d8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_BU_BU_B, 0x704e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_HU_HU_H, 0x704e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_WU_WU_W, 0x704f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_DU_DU_D, 0x704f8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_BU_B_BU, 0x70500000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_HU_H_HU, 0x70508000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_WU_W_WU, 0x70510000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_DU_D_DU, 0x70518000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_B_BU_BU, 0x70520000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_H_HU_HU, 0x70528000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_W_WU_WU, 0x70530000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSUB_D_DU_DU, 0x70538000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHADDW_H_B, 0x70540000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHADDW_W_H, 0x70548000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHADDW_D_W, 0x70550000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHADDW_Q_D, 0x70558000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHSUBW_H_B, 0x70560000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHSUBW_W_H, 0x70568000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHSUBW_D_W, 0x70570000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHSUBW_Q_D, 0x70578000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHADDW_HU_BU, 0x70580000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHADDW_WU_HU, 0x70588000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHADDW_DU_WU, 0x70590000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHADDW_QU_DU, 0x70598000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHSUBW_HU_BU, 0x705a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHSUBW_WU_HU, 0x705a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHSUBW_DU_WU, 0x705b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHSUBW_QU_DU, 0x705b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDA_B, 0x705c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDA_H, 0x705c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDA_W, 0x705d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADDA_D, 0x705d8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADDA_B, 0x705e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADDA_H, 0x705e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADDA_W, 0x705f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADDA_D, 0x705f8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VABSD_B, 0x70600000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VABSD_H, 0x70608000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VABSD_W, 0x70610000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VABSD_D, 0x70618000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VABSD_BU, 0x70620000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VABSD_HU, 0x70628000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VABSD_WU, 0x70630000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VABSD_DU, 0x70638000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVG_B, 0x70640000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVG_H, 0x70648000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVG_W, 0x70650000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVG_D, 0x70658000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVG_BU, 0x70660000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVG_HU, 0x70668000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVG_WU, 0x70670000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVG_DU, 0x70678000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVGR_B, 0x70680000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVGR_H, 0x70688000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVGR_W, 0x70690000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVGR_D, 0x70698000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVGR_BU, 0x706a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVGR_HU, 0x706a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVGR_WU, 0x706b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VAVGR_DU, 0x706b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHALFD_B, 0x706c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHALFD_H, 0x706c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHALFD_W, 0x706d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHALFD_D, 0x706d8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHALFD_BU, 0x706e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHALFD_HU, 0x706e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHALFD_WU, 0x706f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHALFD_DU, 0x706f8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAX_B, 0x70700000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAX_H, 0x70708000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAX_W, 0x70710000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAX_D, 0x70718000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMIN_B, 0x70720000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMIN_H, 0x70728000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMIN_W, 0x70730000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMIN_D, 0x70738000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAX_BU, 0x70740000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAX_HU, 0x70748000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAX_WU, 0x70750000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAX_DU, 0x70758000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMIN_BU, 0x70760000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMIN_HU, 0x70768000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMIN_WU, 0x70770000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMIN_DU, 0x70778000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAXA_B, 0x70780000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAXA_H, 0x70788000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAXA_W, 0x70790000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMAXA_D, 0x70798000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMINA_B, 0x707a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMINA_H, 0x707a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMINA_W, 0x707b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMINA_D, 0x707b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADW_H_B, 0x707c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADW_W_H, 0x707c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADW_D_W, 0x707d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADW_H_BU, 0x707e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADW_W_HU, 0x707e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSADW_D_WU, 0x707f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VACCSADW_H_B, 0x70800000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VACCSADW_W_H, 0x70808000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VACCSADW_D_W, 0x70810000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VACCSADW_H_BU, 0x70820000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VACCSADW_W_HU, 0x70828000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VACCSADW_D_WU, 0x70830000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUL_B, 0x70840000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUL_H, 0x70848000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUL_W, 0x70850000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUL_D, 0x70858000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_B, 0x70860000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_H, 0x70868000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_W, 0x70870000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_D, 0x70878000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_BU, 0x70880000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_HU, 0x70888000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_WU, 0x70890000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_DU, 0x70898000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_BU_B, 0x708a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_HU_H, 0x708a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_WU_W, 0x708b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMUH_DU_D, 0x708b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULXW_H_B, 0x708c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULXW_W_H, 0x708c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULXW_D_W, 0x708d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULXW_H_BU, 0x708e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULXW_W_HU, 0x708e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULXW_D_WU, 0x708f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_H_B, 0x70900000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_W_H, 0x70908000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_D_W, 0x70910000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_Q_D, 0x70918000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_H_B, 0x70920000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_W_H, 0x70928000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_D_W, 0x70930000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_Q_D, 0x70938000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_H_B, 0x70940000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_W_H, 0x70948000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_D_W, 0x70950000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_Q_D, 0x70958000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_H_B, 0x70960000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_W_H, 0x70968000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_D_W, 0x70970000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_Q_D, 0x70978000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_H_BU, 0x70980000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_W_HU, 0x70988000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_D_WU, 0x70990000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_Q_DU, 0x70998000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_H_BU, 0x709a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_W_HU, 0x709a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_D_WU, 0x709b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_Q_DU, 0x709b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_H_BU, 0x709c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_W_HU, 0x709c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_D_WU, 0x709d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_Q_DU, 0x709d8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_H_BU, 0x709e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_W_HU, 0x709e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_D_WU, 0x709f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_Q_DU, 0x709f8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_H_BU_B, 0x70a00000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_W_HU_H, 0x70a08000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_D_WU_W, 0x70a10000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWEV_Q_DU_D, 0x70a18000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_H_BU_B, 0x70a20000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_W_HU_H, 0x70a28000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_D_WU_W, 0x70a30000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWOD_Q_DU_D, 0x70a38000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_H_BU_B, 0x70a40000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_W_HU_H, 0x70a48000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_D_WU_W, 0x70a50000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWL_Q_DU_D, 0x70a58000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_H_BU_B, 0x70a60000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_W_HU_H, 0x70a68000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_D_WU_W, 0x70a70000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMULWH_Q_DU_D, 0x70a78000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADD_B, 0x70a80000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADD_H, 0x70a88000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADD_W, 0x70a90000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADD_D, 0x70a98000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMSUB_B, 0x70aa0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMSUB_H, 0x70aa8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMSUB_W, 0x70ab0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMSUB_D, 0x70ab8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_H_B, 0x70ac0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_W_H, 0x70ac8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_D_W, 0x70ad0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_Q_D, 0x70ad8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_H_B, 0x70ae0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_W_H, 0x70ae8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_D_W, 0x70af0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_Q_D, 0x70af8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_H_B, 0x70b00000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_W_H, 0x70b08000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_D_W, 0x70b10000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_Q_D, 0x70b18000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_H_B, 0x70b20000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_W_H, 0x70b28000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_D_W, 0x70b30000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_Q_D, 0x70b38000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_H_BU, 0x70b40000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_W_HU, 0x70b48000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_D_WU, 0x70b50000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_Q_DU, 0x70b58000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_H_BU, 0x70b60000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_W_HU, 0x70b68000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_D_WU, 0x70b70000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_Q_DU, 0x70b78000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_H_BU, 0x70b80000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_W_HU, 0x70b88000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_D_WU, 0x70b90000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_Q_DU, 0x70b98000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_H_BU, 0x70ba0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_W_HU, 0x70ba8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_D_WU, 0x70bb0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_Q_DU, 0x70bb8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_H_BU_B, 0x70bc0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_W_HU_H, 0x70bc8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_D_WU_W, 0x70bd0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWEV_Q_DU_D, 0x70bd8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_H_BU_B, 0x70be0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_W_HU_H, 0x70be8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_D_WU_W, 0x70bf0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWOD_Q_DU_D, 0x70bf8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_H_BU_B, 0x70c00000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_W_HU_H, 0x70c08000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_D_WU_W, 0x70c10000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWL_Q_DU_D, 0x70c18000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_H_BU_B, 0x70c20000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_W_HU_H, 0x70c28000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_D_WU_W, 0x70c30000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMADDWH_Q_DU_D, 0x70c38000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_H_B, 0x70c40000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_W_H, 0x70c48000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_D_W, 0x70c50000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_Q_D, 0x70c58000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_HU_BU, 0x70c60000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_WU_HU, 0x70c68000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_DU_WU, 0x70c70000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_QU_DU, 0x70c78000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_H_BU_B, 0x70c80000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_W_HU_H, 0x70c88000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_D_WU_W, 0x70c90000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2_Q_DU_D, 0x70c98000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_H_B, 0x70ca0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_W_H, 0x70ca8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_D_W, 0x70cb0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_Q_D, 0x70cb8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_H_BU, 0x70cc0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_W_HU, 0x70cc8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_D_WU, 0x70cd0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_Q_DU, 0x70cd8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_H_BU_B, 0x70ce0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_W_HU_H, 0x70ce8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_D_WU_W, 0x70cf0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2ADD_Q_DU_D, 0x70cf8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2SUB_H_B, 0x70d00000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2SUB_W_H, 0x70d08000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2SUB_D_W, 0x70d10000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2SUB_Q_D, 0x70d18000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2SUB_H_BU, 0x70d20000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2SUB_W_HU, 0x70d28000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2SUB_D_WU, 0x70d30000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP2SUB_Q_DU, 0x70d38000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4_W_B, 0x70d40000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4_D_H, 0x70d48000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4_Q_W, 0x70d50000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4_W_BU, 0x70d60000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4_D_HU, 0x70d68000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4_Q_WU, 0x70d70000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4_W_BU_B, 0x70d80000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4_D_HU_H, 0x70d88000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4_Q_WU_W, 0x70d90000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4ADD_W_B, 0x70da0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4ADD_D_H, 0x70da8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4ADD_Q_W, 0x70db0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4ADD_W_BU, 0x70dc0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4ADD_D_HU, 0x70dc8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4ADD_Q_WU, 0x70dd0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4ADD_W_BU_B, 0x70de0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4ADD_D_HU_H, 0x70de8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDP4ADD_Q_WU_W, 0x70df0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDIV_B, 0x70e00000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDIV_H, 0x70e08000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDIV_W, 0x70e10000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDIV_D, 0x70e18000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMOD_B, 0x70e20000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMOD_H, 0x70e28000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMOD_W, 0x70e30000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMOD_D, 0x70e38000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDIV_BU, 0x70e40000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDIV_HU, 0x70e48000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDIV_WU, 0x70e50000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VDIV_DU, 0x70e58000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMOD_BU, 0x70e60000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMOD_HU, 0x70e68000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMOD_WU, 0x70e70000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VMOD_DU, 0x70e78000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLL_B, 0x70e80000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLL_H, 0x70e88000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLL_W, 0x70e90000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSLL_D, 0x70e98000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRL_B, 0x70ea0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRL_H, 0x70ea8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRL_W, 0x70eb0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRL_D, 0x70eb8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRA_B, 0x70ec0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRA_H, 0x70ec8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRA_W, 0x70ed0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRA_D, 0x70ed8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VROTR_B, 0x70ee0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VROTR_H, 0x70ee8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VROTR_W, 0x70ef0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VROTR_D, 0x70ef8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRLR_B, 0x70f00000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRLR_H, 0x70f08000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRLR_W, 0x70f10000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRLR_D, 0x70f18000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRAR_B, 0x70f20000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRAR_H, 0x70f28000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRAR_W, 0x70f30000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRAR_D, 0x70f38000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRLN_B_H, 0x70f48000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRLN_H_W, 0x70f50000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRLN_W_D, 0x70f58000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRAN_B_H, 0x70f68000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRAN_H_W, 0x70f70000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRAN_W_D, 0x70f78000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRLRN_B_H, 0x70f88000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRLRN_H_W, 0x70f90000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRLRN_W_D, 0x70f98000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRARN_B_H, 0x70fa8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRARN_H_W, 0x70fb0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSRARN_W_D, 0x70fb8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLN_B_H, 0x70fc8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLN_H_W, 0x70fd0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLN_W_D, 0x70fd8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRAN_B_H, 0x70fe8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRAN_H_W, 0x70ff0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRAN_W_D, 0x70ff8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLRN_B_H, 0x71008000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLRN_H_W, 0x71010000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLRN_W_D, 0x71018000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRARN_B_H, 0x71028000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRARN_H_W, 0x71030000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRARN_W_D, 0x71038000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLN_BU_H, 0x71048000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLN_HU_W, 0x71050000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLN_WU_D, 0x71058000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRAN_BU_H, 0x71068000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRAN_HU_W, 0x71070000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRAN_WU_D, 0x71078000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLRN_BU_H, 0x71088000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLRN_HU_W, 0x71090000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRLRN_WU_D, 0x71098000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRARN_BU_H, 0x710a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRARN_HU_W, 0x710b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSSRARN_WU_D, 0x710b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITCLR_B, 0x710c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITCLR_H, 0x710c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITCLR_W, 0x710d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITCLR_D, 0x710d8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITSET_B, 0x710e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITSET_H, 0x710e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITSET_W, 0x710f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITSET_D, 0x710f8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITREV_B, 0x71100000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITREV_H, 0x71108000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITREV_W, 0x71110000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBITREV_D, 0x71118000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBSTRC12_B, 0x71120000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBSTRC12_H, 0x71128000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBSTRC12_W, 0x71130000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBSTRC12_D, 0x71138000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBSTRC21_B, 0x71140000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBSTRC21_H, 0x71148000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBSTRC21_W, 0x71150000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VBSTRC21_D, 0x71158000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPACKEV_B, 0x71160000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPACKEV_H, 0x71168000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPACKEV_W, 0x71170000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPACKEV_D, 0x71178000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPACKOD_B, 0x71180000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPACKOD_H, 0x71188000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPACKOD_W, 0x71190000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPACKOD_D, 0x71198000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VILVL_B, 0x711a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VILVL_H, 0x711a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VILVL_W, 0x711b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VILVL_D, 0x711b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VILVH_B, 0x711c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VILVH_H, 0x711c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VILVH_W, 0x711d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VILVH_D, 0x711d8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPICKEV_B, 0x711e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPICKEV_H, 0x711e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPICKEV_W, 0x711f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPICKEV_D, 0x711f8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPICKOD_B, 0x71200000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPICKOD_H, 0x71208000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPICKOD_W, 0x71210000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPICKOD_D, 0x71218000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VREPLVE_B, 0x71220000, {FPR_VD, FPR_VJ, GPR_RK}}, + {LISA_VREPLVE_H, 0x71228000, {FPR_VD, FPR_VJ, GPR_RK}}, + {LISA_VREPLVE_W, 0x71230000, {FPR_VD, FPR_VJ, GPR_RK}}, + {LISA_VREPLVE_D, 0x71238000, {FPR_VD, FPR_VJ, GPR_RK}}, + {LISA_VEXTRCOL_B, 0x71240000, {FPR_VD, FPR_VJ, GPR_RK}}, + {LISA_VEXTRCOL_H, 0x71248000, {FPR_VD, FPR_VJ, GPR_RK}}, + {LISA_VEXTRCOL_W, 0x71250000, {FPR_VD, FPR_VJ, GPR_RK}}, + {LISA_VEXTRCOL_D, 0x71258000, {FPR_VD, FPR_VJ, GPR_RK}}, + {LISA_VAND_V, 0x71260000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VOR_V, 0x71268000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VXOR_V, 0x71270000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VNOR_V, 0x71278000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VANDN_V, 0x71280000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VORN_V, 0x71288000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VRANDSIGN_B, 0x71290000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VRANDSIGN_H, 0x71298000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VRORSIGN_B, 0x712a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VRORSIGN_H, 0x712a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFRSTP_B, 0x712b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFRSTP_H, 0x712b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VCLRSTRR_V, 0x712c0000, {FPR_VD, FPR_VJ, GPR_RK}}, + {LISA_VCLRSTRV_V, 0x712c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VADD_Q, 0x712d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSUB_Q, 0x712d8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSIGNCOV_B, 0x712e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSIGNCOV_H, 0x712e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSIGNCOV_W, 0x712f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSIGNCOV_D, 0x712f8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFADD_S, 0x71308000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFADD_D, 0x71310000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFSUB_S, 0x71328000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFSUB_D, 0x71330000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFADDSUB_S, 0x71348000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFADDSUB_D, 0x71350000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFSUBADD_S, 0x71368000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFSUBADD_D, 0x71370000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFMUL_S, 0x71388000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFMUL_D, 0x71390000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFDIV_S, 0x713a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFDIV_D, 0x713b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFMAX_S, 0x713c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFMAX_D, 0x713d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFMIN_S, 0x713e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFMIN_D, 0x713f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFMAXA_S, 0x71408000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFMAXA_D, 0x71410000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFMINA_S, 0x71428000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFMINA_D, 0x71430000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFSCALEB_S, 0x71448000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFSCALEB_D, 0x71450000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFCVT_H_S, 0x71460000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFCVT_S_D, 0x71468000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFFINT_S_L, 0x71480000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFTINT_W_D, 0x71498000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFTINTRM_W_D, 0x714a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFTINTRP_W_D, 0x714a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFTINTRZ_W_D, 0x714b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VFTINTRNE_W_D, 0x714b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VHADD4_H_BU, 0x714e8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSHUF4_W, 0x714f0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSHUF2_D, 0x714f8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES128_ENC, 0x71500000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES128_DEC, 0x71508000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES192_ENC, 0x71510000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES192_DEC, 0x71518000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES256_ENC, 0x71520000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES256_DEC, 0x71528000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES_KG, 0x71530000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES_FR_ENC, 0x71538000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES_FR_DEC, 0x71540000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES_LR_ENC, 0x71548000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES_LR_DEC, 0x71550000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_AES_MC_ENC, 0x71558000, {FPR_VD, FPR_VJ}}, + {LISA_AES_MC_DEC, 0x71560000, {FPR_VD, FPR_VJ}}, + {LISA_AES_SB_ENC, 0x71568000, {FPR_VD, FPR_VJ}}, + {LISA_AES_SB_DEC, 0x71570000, {FPR_VD, FPR_VJ}}, + {LISA_AES_SR_ENC, 0x71578000, {FPR_VD, FPR_VJ}}, + {LISA_AES_SR_DEC, 0x71580000, {FPR_VD, FPR_VJ}}, + {LISA_MD5_MS, 0x71588000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_MD5_4R, 0x71590000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_SHA1_MS_1, 0x71598000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_SHA1_MS_2, 0x715a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_SHA1_HASH_4R, 0x715a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_SHA256_MS_1, 0x715b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_SHA256_MS_2, 0x715b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_SHA256_HASH_2R, 0x715c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_SHA512_MS_1, 0x715c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_SHA512_MS_2, 0x715d0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_SHA512_HASH_R_1, 0x715d8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_SHA512_HASH_R_2, 0x715e0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMUL_W, 0x71600000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMUL_D, 0x71608000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMUH_W, 0x71610000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMUH_D, 0x71618000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMULACC_W, 0x71620000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMULACC_D, 0x71628000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMUHACC_W, 0x71630000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMUHACC_D, 0x71638000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMULWL_H_B, 0x71640000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMULWL_W_H, 0x71648000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMULWL_D_W, 0x71650000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMULWL_Q_D, 0x71658000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMULWH_H_B, 0x71660000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMULWH_W_H, 0x71668000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMULWH_D_W, 0x71670000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMULWH_Q_D, 0x71678000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMADDWL_H_B, 0x71680000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMADDWL_W_H, 0x71688000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMADDWL_D_W, 0x71690000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMADDWL_Q_D, 0x71698000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMADDWH_H_B, 0x716a0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMADDWH_W_H, 0x716a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMADDWH_D_W, 0x716b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPMADDWH_Q_D, 0x716b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPDP2_Q_D, 0x716c0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VPDP2ADD_Q_D, 0x716c8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VCDP4_RE_D_H, 0x71700000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VCDP4_IM_D_H, 0x71708000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VCDP4ADD_RE_D_H, 0x71710000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VCDP4ADD_IM_D_H, 0x71718000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VCDP2_RE_Q_W, 0x71720000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VCDP2_IM_Q_W, 0x71728000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VCDP2ADD_RE_Q_W, 0x71730000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VCDP2ADD_IM_Q_W, 0x71738000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSIGNSEL_W, 0x71790000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSIGNSEL_D, 0x71798000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSHUF_H, 0x717a8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSHUF_W, 0x717b0000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSHUF_D, 0x717b8000, {FPR_VD, FPR_VJ, FPR_VK}}, + {LISA_VSEQI_B, 0x72800000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSEQI_H, 0x72808000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSEQI_W, 0x72810000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSEQI_D, 0x72818000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSLEI_B, 0x72820000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSLEI_H, 0x72828000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSLEI_W, 0x72830000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSLEI_D, 0x72838000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSLEI_BU, 0x72840000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSLEI_HU, 0x72848000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSLEI_WU, 0x72850000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSLEI_DU, 0x72858000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSLTI_B, 0x72860000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSLTI_H, 0x72868000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSLTI_W, 0x72870000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSLTI_D, 0x72878000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VSLTI_BU, 0x72880000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSLTI_HU, 0x72888000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSLTI_WU, 0x72890000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSLTI_DU, 0x72898000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VADDI_BU, 0x728a0000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VADDI_HU, 0x728a8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VADDI_WU, 0x728b0000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VADDI_DU, 0x728b8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSUBI_BU, 0x728c0000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSUBI_HU, 0x728c8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSUBI_WU, 0x728d0000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSUBI_DU, 0x728d8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VBSLL_V, 0x728e0000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VBSRL_V, 0x728e8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VMAXI_B, 0x72900000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VMAXI_H, 0x72908000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VMAXI_W, 0x72910000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VMAXI_D, 0x72918000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VMINI_B, 0x72920000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VMINI_H, 0x72928000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VMINI_W, 0x72930000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VMINI_D, 0x72938000, {FPR_VD, FPR_VJ, IMM_SI5}}, + {LISA_VMAXI_BU, 0x72940000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VMAXI_HU, 0x72948000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VMAXI_WU, 0x72950000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VMAXI_DU, 0x72958000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VMINI_BU, 0x72960000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VMINI_HU, 0x72968000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VMINI_WU, 0x72970000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VMINI_DU, 0x72978000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VRANDSIGNI_B, 0x72980000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VRANDSIGNI_H, 0x72988000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VRORSIGNI_B, 0x72990000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VRORSIGNI_H, 0x72998000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VFRSTPI_B, 0x729a0000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VFRSTPI_H, 0x729a8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VCLRSTRI_V, 0x729b0000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VMEPATMSK_V, 0x729b8000, {FPR_VD, IMM_MODE, IMM_UI5L}}, + {LISA_VCLO_B, 0x729c0000, {FPR_VD, FPR_VJ}}, + {LISA_VCLO_H, 0x729c0400, {FPR_VD, FPR_VJ}}, + {LISA_VCLO_W, 0x729c0800, {FPR_VD, FPR_VJ}}, + {LISA_VCLO_D, 0x729c0c00, {FPR_VD, FPR_VJ}}, + {LISA_VCLZ_B, 0x729c1000, {FPR_VD, FPR_VJ}}, + {LISA_VCLZ_H, 0x729c1400, {FPR_VD, FPR_VJ}}, + {LISA_VCLZ_W, 0x729c1800, {FPR_VD, FPR_VJ}}, + {LISA_VCLZ_D, 0x729c1c00, {FPR_VD, FPR_VJ}}, + {LISA_VPCNT_B, 0x729c2000, {FPR_VD, FPR_VJ}}, + {LISA_VPCNT_H, 0x729c2400, {FPR_VD, FPR_VJ}}, + {LISA_VPCNT_W, 0x729c2800, {FPR_VD, FPR_VJ}}, + {LISA_VPCNT_D, 0x729c2c00, {FPR_VD, FPR_VJ}}, + {LISA_VNEG_B, 0x729c3000, {FPR_VD, FPR_VJ}}, + {LISA_VNEG_H, 0x729c3400, {FPR_VD, FPR_VJ}}, + {LISA_VNEG_W, 0x729c3800, {FPR_VD, FPR_VJ}}, + {LISA_VNEG_D, 0x729c3c00, {FPR_VD, FPR_VJ}}, + {LISA_VMSKLTZ_B, 0x729c4000, {FPR_VD, FPR_VJ}}, + {LISA_VMSKLTZ_H, 0x729c4400, {FPR_VD, FPR_VJ}}, + {LISA_VMSKLTZ_W, 0x729c4800, {FPR_VD, FPR_VJ}}, + {LISA_VMSKLTZ_D, 0x729c4c00, {FPR_VD, FPR_VJ}}, + {LISA_VMSKGEZ_B, 0x729c5000, {FPR_VD, FPR_VJ}}, + {LISA_VMSKNZ_B, 0x729c6000, {FPR_VD, FPR_VJ}}, + {LISA_VMSKCOPY_B, 0x729c7000, {FPR_VD, FPR_VJ}}, + {LISA_VMSKFILL_B, 0x729c8000, {FPR_VD, FPR_VJ}}, + {LISA_VFRSTM_B, 0x729c9000, {FPR_VD, FPR_VJ}}, + {LISA_VFRSTM_H, 0x729c9400, {FPR_VD, FPR_VJ}}, + {LISA_VSETEQZ_V, 0x729c9800, {FCC_CD, FPR_VJ}}, + {LISA_VSETNEZ_V, 0x729c9c00, {FCC_CD, FPR_VJ}}, + {LISA_VSETANYEQZ_B, 0x729ca000, {FCC_CD, FPR_VJ}}, + {LISA_VSETANYEQZ_H, 0x729ca400, {FCC_CD, FPR_VJ}}, + {LISA_VSETANYEQZ_W, 0x729ca800, {FCC_CD, FPR_VJ}}, + {LISA_VSETANYEQZ_D, 0x729cac00, {FCC_CD, FPR_VJ}}, + {LISA_VSETALLNEZ_B, 0x729cb000, {FCC_CD, FPR_VJ}}, + {LISA_VSETALLNEZ_H, 0x729cb400, {FCC_CD, FPR_VJ}}, + {LISA_VSETALLNEZ_W, 0x729cb800, {FCC_CD, FPR_VJ}}, + {LISA_VSETALLNEZ_D, 0x729cbc00, {FCC_CD, FPR_VJ}}, + {LISA_VFLOGB_S, 0x729cc400, {FPR_VD, FPR_VJ}}, + {LISA_VFLOGB_D, 0x729cc800, {FPR_VD, FPR_VJ}}, + {LISA_VFCLASS_S, 0x729cd400, {FPR_VD, FPR_VJ}}, + {LISA_VFCLASS_D, 0x729cd800, {FPR_VD, FPR_VJ}}, + {LISA_VFSQRT_S, 0x729ce400, {FPR_VD, FPR_VJ}}, + {LISA_VFSQRT_D, 0x729ce800, {FPR_VD, FPR_VJ}}, + {LISA_VFRECIP_S, 0x729cf400, {FPR_VD, FPR_VJ}}, + {LISA_VFRECIP_D, 0x729cf800, {FPR_VD, FPR_VJ}}, + {LISA_VFRSQRT_S, 0x729d0400, {FPR_VD, FPR_VJ}}, + {LISA_VFRSQRT_D, 0x729d0800, {FPR_VD, FPR_VJ}}, + {LISA_VFRINT_S, 0x729d3400, {FPR_VD, FPR_VJ}}, + {LISA_VFRINT_D, 0x729d3800, {FPR_VD, FPR_VJ}}, + {LISA_VFRINTRM_S, 0x729d4400, {FPR_VD, FPR_VJ}}, + {LISA_VFRINTRM_D, 0x729d4800, {FPR_VD, FPR_VJ}}, + {LISA_VFRINTRP_S, 0x729d5400, {FPR_VD, FPR_VJ}}, + {LISA_VFRINTRP_D, 0x729d5800, {FPR_VD, FPR_VJ}}, + {LISA_VFRINTRZ_S, 0x729d6400, {FPR_VD, FPR_VJ}}, + {LISA_VFRINTRZ_D, 0x729d6800, {FPR_VD, FPR_VJ}}, + {LISA_VFRINTRNE_S, 0x729d7400, {FPR_VD, FPR_VJ}}, + {LISA_VFRINTRNE_D, 0x729d7800, {FPR_VD, FPR_VJ}}, + {LISA_VEXTL_W_B, 0x729d8400, {FPR_VD, FPR_VJ}}, + {LISA_VEXTL_D_B, 0x729d8800, {FPR_VD, FPR_VJ}}, + {LISA_VEXTL_D_H, 0x729d9400, {FPR_VD, FPR_VJ}}, + {LISA_VEXTL_W_BU, 0x729dac00, {FPR_VD, FPR_VJ}}, + {LISA_VEXTL_D_BU, 0x729db000, {FPR_VD, FPR_VJ}}, + {LISA_VEXTL_D_HU, 0x729dbc00, {FPR_VD, FPR_VJ}}, + {LISA_VHADD8_D_BU, 0x729dd000, {FPR_VD, FPR_VJ}}, + {LISA_VHMINPOS_W_HU, 0x729dd400, {FPR_VD, FPR_VJ}}, + {LISA_VHMINPOS_D_HU, 0x729dd800, {FPR_VD, FPR_VJ}}, + {LISA_VHMINPOS_Q_HU, 0x729ddc00, {FPR_VD, FPR_VJ}}, + {LISA_VCLRTAIL_B, 0x729de000, {FPR_VD, FPR_VJ}}, + {LISA_VCLRTAIL_H, 0x729de400, {FPR_VD, FPR_VJ}}, + {LISA_VFCVTL_S_H, 0x729de800, {FPR_VD, FPR_VJ}}, + {LISA_VFCVTH_S_H, 0x729dec00, {FPR_VD, FPR_VJ}}, + {LISA_VFCVTL_D_S, 0x729df000, {FPR_VD, FPR_VJ}}, + {LISA_VFCVTH_D_S, 0x729df400, {FPR_VD, FPR_VJ}}, + {LISA_VFFINT_S_W, 0x729e0000, {FPR_VD, FPR_VJ}}, + {LISA_VFFINT_S_WU, 0x729e0400, {FPR_VD, FPR_VJ}}, + {LISA_VFFINT_D_L, 0x729e0800, {FPR_VD, FPR_VJ}}, + {LISA_VFFINT_D_LU, 0x729e0c00, {FPR_VD, FPR_VJ}}, + {LISA_VFFINTL_D_W, 0x729e1000, {FPR_VD, FPR_VJ}}, + {LISA_VFFINTH_D_W, 0x729e1400, {FPR_VD, FPR_VJ}}, + {LISA_VFTINT_W_S, 0x729e3000, {FPR_VD, FPR_VJ}}, + {LISA_VFTINT_L_D, 0x729e3400, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRM_W_S, 0x729e3800, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRM_L_D, 0x729e3c00, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRP_W_S, 0x729e4000, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRP_L_D, 0x729e4400, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRZ_W_S, 0x729e4800, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRZ_L_D, 0x729e4c00, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRNE_W_S, 0x729e5000, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRNE_L_D, 0x729e5400, {FPR_VD, FPR_VJ}}, + {LISA_VFTINT_WU_S, 0x729e5800, {FPR_VD, FPR_VJ}}, + {LISA_VFTINT_LU_D, 0x729e5c00, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRZ_WU_S, 0x729e7000, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRZ_LU_D, 0x729e7400, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTL_L_S, 0x729e8000, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTH_L_S, 0x729e8400, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRML_L_S, 0x729e8800, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRMH_L_S, 0x729e8c00, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRPL_L_S, 0x729e9000, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRPH_L_S, 0x729e9400, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRZL_L_S, 0x729e9800, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRZH_L_S, 0x729e9c00, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRNEL_L_S, 0x729ea000, {FPR_VD, FPR_VJ}}, + {LISA_VFTINTRNEH_L_S, 0x729ea400, {FPR_VD, FPR_VJ}}, + {LISA_VEXTH_H_B, 0x729ee000, {FPR_VD, FPR_VJ}}, + {LISA_VEXTH_W_H, 0x729ee400, {FPR_VD, FPR_VJ}}, + {LISA_VEXTH_D_W, 0x729ee800, {FPR_VD, FPR_VJ}}, + {LISA_VEXTH_Q_D, 0x729eec00, {FPR_VD, FPR_VJ}}, + {LISA_VEXTH_HU_BU, 0x729ef000, {FPR_VD, FPR_VJ}}, + {LISA_VEXTH_WU_HU, 0x729ef400, {FPR_VD, FPR_VJ}}, + {LISA_VEXTH_DU_WU, 0x729ef800, {FPR_VD, FPR_VJ}}, + {LISA_VEXTH_QU_DU, 0x729efc00, {FPR_VD, FPR_VJ}}, + {LISA_VREPLGR2VR_B, 0x729f0000, {FPR_VD, GPR_RJ}}, + {LISA_VREPLGR2VR_H, 0x729f0400, {FPR_VD, GPR_RJ}}, + {LISA_VREPLGR2VR_W, 0x729f0800, {FPR_VD, GPR_RJ}}, + {LISA_VREPLGR2VR_D, 0x729f0c00, {FPR_VD, GPR_RJ}}, + {LISA_VROTRI_B, 0x72a02000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VROTRI_H, 0x72a04000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VROTRI_W, 0x72a08000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VROTRI_D, 0x72a10000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSRLRI_B, 0x72a42000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VSRLRI_H, 0x72a44000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSRLRI_W, 0x72a48000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSRLRI_D, 0x72a50000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSRARI_B, 0x72a82000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VSRARI_H, 0x72a84000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSRARI_W, 0x72a88000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSRARI_D, 0x72a90000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VINSGR2VR_B, 0x72eb8000, {FPR_VD, GPR_RJ, IMM_UI4}}, + {LISA_VINSGR2VR_H, 0x72ebc000, {FPR_VD, GPR_RJ, IMM_UI3}}, + {LISA_VINSGR2VR_W, 0x72ebe000, {FPR_VD, GPR_RJ, IMM_UI2}}, + {LISA_VINSGR2VR_D, 0x72ebf000, {FPR_VD, GPR_RJ, IMM_UI1}}, + {LISA_VPICKVE2GR_B, 0x72ef8000, {GPR_RD, FPR_VJ, IMM_UI4}}, + {LISA_VPICKVE2GR_H, 0x72efc000, {GPR_RD, FPR_VJ, IMM_UI3}}, + {LISA_VPICKVE2GR_W, 0x72efe000, {GPR_RD, FPR_VJ, IMM_UI2}}, + {LISA_VPICKVE2GR_D, 0x72eff000, {GPR_RD, FPR_VJ, IMM_UI1}}, + {LISA_VPICKVE2GR_BU, 0x72f38000, {GPR_RD, FPR_VJ, IMM_UI4}}, + {LISA_VPICKVE2GR_HU, 0x72f3c000, {GPR_RD, FPR_VJ, IMM_UI3}}, + {LISA_VPICKVE2GR_WU, 0x72f3e000, {GPR_RD, FPR_VJ, IMM_UI2}}, + {LISA_VPICKVE2GR_DU, 0x72f3f000, {GPR_RD, FPR_VJ, IMM_UI1}}, + {LISA_VREPLVEI_B, 0x72f78000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VREPLVEI_H, 0x72f7c000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VREPLVEI_W, 0x72f7e000, {FPR_VD, FPR_VJ, IMM_UI2}}, + {LISA_VREPLVEI_D, 0x72f7f000, {FPR_VD, FPR_VJ, IMM_UI1}}, + {LISA_VEXTRCOLI_B, 0x72fb8000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VEXTRCOLI_H, 0x72fbc000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VEXTRCOLI_W, 0x72fbe000, {FPR_VD, FPR_VJ, IMM_UI2}}, + {LISA_VEXTRCOLI_D, 0x72fbf000, {FPR_VD, FPR_VJ, IMM_UI1}}, + {LISA_VSLLWIL_H_B, 0x73082000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VSLLWIL_W_H, 0x73084000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSLLWIL_D_W, 0x73088000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VEXTL_Q_D, 0x73090000, {FPR_VD, FPR_VJ}}, + {LISA_VSLLWIL_HU_BU, 0x730c2000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VSLLWIL_WU_HU, 0x730c4000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSLLWIL_DU_WU, 0x730c8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VEXTL_QU_DU, 0x730d0000, {FPR_VD, FPR_VJ}}, + {LISA_VBITCLRI_B, 0x73102000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VBITCLRI_H, 0x73104000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VBITCLRI_W, 0x73108000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VBITCLRI_D, 0x73110000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VBITSETI_B, 0x73142000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VBITSETI_H, 0x73144000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VBITSETI_W, 0x73148000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VBITSETI_D, 0x73150000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VBITREVI_B, 0x73182000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VBITREVI_H, 0x73184000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VBITREVI_W, 0x73188000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VBITREVI_D, 0x73190000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VBSTRC12I_B, 0x731c2000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VBSTRC12I_H, 0x731c4000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VBSTRC12I_W, 0x731c8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VBSTRC12I_D, 0x731d0000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VBSTRC21I_B, 0x73202000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VBSTRC21I_H, 0x73204000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VBSTRC21I_W, 0x73208000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VBSTRC21I_D, 0x73210000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSAT_B, 0x73242000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VSAT_H, 0x73244000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSAT_W, 0x73248000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSAT_D, 0x73250000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSAT_BU, 0x73282000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VSAT_HU, 0x73284000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSAT_WU, 0x73288000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSAT_DU, 0x73290000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSLLI_B, 0x732c2000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VSLLI_H, 0x732c4000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSLLI_W, 0x732c8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSLLI_D, 0x732d0000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSRLI_B, 0x73302000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VSRLI_H, 0x73304000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSRLI_W, 0x73308000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSRLI_D, 0x73310000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSRAI_B, 0x73342000, {FPR_VD, FPR_VJ, IMM_UI3}}, + {LISA_VSRAI_H, 0x73344000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSRAI_W, 0x73348000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSRAI_D, 0x73350000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSRLRNENI_B_H, 0x73384000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSRLRNENI_H_W, 0x73388000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSRLRNENI_W_D, 0x73390000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSRLRNENI_D_Q, 0x733a0000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSRARNENI_B_H, 0x733c4000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSRARNENI_H_W, 0x733c8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSRARNENI_W_D, 0x733d0000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSRARNENI_D_Q, 0x733e0000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSRLNI_B_H, 0x73404000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSRLNI_H_W, 0x73408000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSRLNI_W_D, 0x73410000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSRLNI_D_Q, 0x73420000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSRLRNI_B_H, 0x73444000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSRLRNI_H_W, 0x73448000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSRLRNI_W_D, 0x73450000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSRLRNI_D_Q, 0x73460000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRLNI_B_H, 0x73484000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRLNI_H_W, 0x73488000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRLNI_W_D, 0x73490000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRLNI_D_Q, 0x734a0000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRLNI_BU_H, 0x734c4000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRLNI_HU_W, 0x734c8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRLNI_WU_D, 0x734d0000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRLNI_DU_Q, 0x734e0000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRLRNI_B_H, 0x73504000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRLRNI_H_W, 0x73508000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRLRNI_W_D, 0x73510000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRLRNI_D_Q, 0x73520000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRLRNI_BU_H, 0x73544000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRLRNI_HU_W, 0x73548000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRLRNI_WU_D, 0x73550000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRLRNI_DU_Q, 0x73560000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSRANI_B_H, 0x73584000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSRANI_H_W, 0x73588000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSRANI_W_D, 0x73590000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSRANI_D_Q, 0x735a0000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSRARNI_B_H, 0x735c4000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSRARNI_H_W, 0x735c8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSRARNI_W_D, 0x735d0000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSRARNI_D_Q, 0x735e0000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRANI_B_H, 0x73604000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRANI_H_W, 0x73608000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRANI_W_D, 0x73610000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRANI_D_Q, 0x73620000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRANI_BU_H, 0x73644000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRANI_HU_W, 0x73648000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRANI_WU_D, 0x73650000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRANI_DU_Q, 0x73660000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRARNI_B_H, 0x73684000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRARNI_H_W, 0x73688000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRARNI_W_D, 0x73690000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRARNI_D_Q, 0x736a0000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRARNI_BU_H, 0x736c4000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRARNI_HU_W, 0x736c8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRARNI_WU_D, 0x736d0000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRARNI_DU_Q, 0x736e0000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRLRNENI_B_H, 0x73704000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRLRNENI_H_W, 0x73708000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRLRNENI_W_D, 0x73710000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRLRNENI_D_Q, 0x73720000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRLRNENI_BU_H, 0x73744000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRLRNENI_HU_W, 0x73748000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRLRNENI_WU_D, 0x73750000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRLRNENI_DU_Q, 0x73760000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRARNENI_B_H, 0x73784000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRARNENI_H_W, 0x73788000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRARNENI_W_D, 0x73790000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRARNENI_D_Q, 0x737a0000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VSSRARNENI_BU_H, 0x737c4000, {FPR_VD, FPR_VJ, IMM_UI4}}, + {LISA_VSSRARNENI_HU_W, 0x737c8000, {FPR_VD, FPR_VJ, IMM_UI5L}}, + {LISA_VSSRARNENI_WU_D, 0x737d0000, {FPR_VD, FPR_VJ, IMM_UI6}}, + {LISA_VSSRARNENI_DU_Q, 0x737e0000, {FPR_VD, FPR_VJ, IMM_UI7}}, + {LISA_VEXTRINS_D, 0x73800000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VEXTRINS_W, 0x73840000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VEXTRINS_H, 0x73880000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VEXTRINS_B, 0x738c0000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSHUF4I_B, 0x73900000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSHUF4I_H, 0x73940000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSHUF4I_W, 0x73980000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSHUF4I_D, 0x739c0000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSHUFI1_B, 0x73a00000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSHUFI2_B, 0x73a40000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSHUFI3_B, 0x73a80000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSHUFI4_B, 0x73ac0000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSHUFI1_H, 0x73b00000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSHUFI2_H, 0x73b40000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSELI_H, 0x73b80000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSELI_W, 0x73bc0000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VSELI_D, 0x73c00000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VBITSELI_B, 0x73c40000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VBITMVZI_B, 0x73c80000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VBITMVNZI_B, 0x73cc0000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VANDI_B, 0x73d00000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VORI_B, 0x73d40000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VXORI_B, 0x73d80000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VNORI_B, 0x73dc0000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_VLDI, 0x73e00000, {FPR_VD, IMM_I13}}, + {LISA_VPERMI_W, 0x73e40000, {FPR_VD, FPR_VJ, IMM_UI8}}, + {LISA_XVSEQ_B, 0x74000000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSEQ_H, 0x74008000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSEQ_W, 0x74010000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSEQ_D, 0x74018000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLE_B, 0x74020000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLE_H, 0x74028000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLE_W, 0x74030000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLE_D, 0x74038000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLE_BU, 0x74040000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLE_HU, 0x74048000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLE_WU, 0x74050000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLE_DU, 0x74058000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLT_B, 0x74060000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLT_H, 0x74068000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLT_W, 0x74070000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLT_D, 0x74078000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLT_BU, 0x74080000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLT_HU, 0x74088000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLT_WU, 0x74090000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLT_DU, 0x74098000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADD_B, 0x740a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADD_H, 0x740a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADD_W, 0x740b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADD_D, 0x740b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUB_B, 0x740c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUB_H, 0x740c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUB_W, 0x740d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUB_D, 0x740d8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDW_H_H_B, 0x740e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDW_W_W_H, 0x740e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDW_D_D_W, 0x740f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDW_H_H_BU, 0x74100000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDW_W_W_HU, 0x74108000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDW_D_D_WU, 0x74110000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBW_H_H_B, 0x74120000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBW_W_W_H, 0x74128000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBW_D_D_W, 0x74130000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBW_H_H_BU, 0x74140000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBW_W_W_HU, 0x74148000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBW_D_D_WU, 0x74150000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADDW_H_H_B, 0x74160000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADDW_W_W_H, 0x74168000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADDW_D_D_W, 0x74170000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADDW_HU_HU_BU, 0x74180000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADDW_WU_WU_HU, 0x74188000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADDW_DU_DU_WU, 0x74190000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUBW_H_H_B, 0x741a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUBW_W_W_H, 0x741a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUBW_D_D_W, 0x741b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUBW_HU_HU_BU, 0x741c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUBW_WU_WU_HU, 0x741c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUBW_DU_DU_WU, 0x741d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_H_B, 0x741e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_W_H, 0x741e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_D_W, 0x741f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_Q_D, 0x741f8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWEV_H_B, 0x74200000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWEV_W_H, 0x74208000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWEV_D_W, 0x74210000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWEV_Q_D, 0x74218000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_H_B, 0x74220000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_W_H, 0x74228000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_D_W, 0x74230000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_Q_D, 0x74238000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWOD_H_B, 0x74240000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWOD_W_H, 0x74248000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWOD_D_W, 0x74250000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWOD_Q_D, 0x74258000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_H_B, 0x74260000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_W_H, 0x74268000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_D_W, 0x74270000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_Q_D, 0x74278000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWL_H_B, 0x74280000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWL_W_H, 0x74288000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWL_D_W, 0x74290000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWL_Q_D, 0x74298000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_H_B, 0x742a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_W_H, 0x742a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_D_W, 0x742b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_Q_D, 0x742b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWH_H_B, 0x742c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWH_W_H, 0x742c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWH_D_W, 0x742d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWH_Q_D, 0x742d8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_H_BU, 0x742e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_W_HU, 0x742e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_D_WU, 0x742f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_Q_DU, 0x742f8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWEV_H_BU, 0x74300000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWEV_W_HU, 0x74308000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWEV_D_WU, 0x74310000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWEV_Q_DU, 0x74318000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_H_BU, 0x74320000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_W_HU, 0x74328000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_D_WU, 0x74330000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_Q_DU, 0x74338000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWOD_H_BU, 0x74340000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWOD_W_HU, 0x74348000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWOD_D_WU, 0x74350000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWOD_Q_DU, 0x74358000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_H_BU, 0x74360000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_W_HU, 0x74368000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_D_WU, 0x74370000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_Q_DU, 0x74378000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWL_H_BU, 0x74380000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWL_W_HU, 0x74388000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWL_D_WU, 0x74390000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWL_Q_DU, 0x74398000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_H_BU, 0x743a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_W_HU, 0x743a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_D_WU, 0x743b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_Q_DU, 0x743b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWH_H_BU, 0x743c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWH_W_HU, 0x743c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWH_D_WU, 0x743d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUBWH_Q_DU, 0x743d8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_H_BU_B, 0x743e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_W_HU_H, 0x743e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_D_WU_W, 0x743f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWEV_Q_DU_D, 0x743f8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_H_BU_B, 0x74400000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_W_HU_H, 0x74408000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_D_WU_W, 0x74410000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWOD_Q_DU_D, 0x74418000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_H_BU_B, 0x74420000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_W_HU_H, 0x74428000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_D_WU_W, 0x74430000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWL_Q_DU_D, 0x74438000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_H_BU_B, 0x74440000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_W_HU_H, 0x74448000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_D_WU_W, 0x74450000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDWH_Q_DU_D, 0x74458000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADD_B, 0x74460000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADD_H, 0x74468000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADD_W, 0x74470000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADD_D, 0x74478000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_B, 0x74480000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_H, 0x74488000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_W, 0x74490000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_D, 0x74498000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADD_BU, 0x744a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADD_HU, 0x744a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADD_WU, 0x744b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADD_DU, 0x744b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_BU, 0x744c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_HU, 0x744c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_WU, 0x744d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_DU, 0x744d8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_BU_BU_B, 0x744e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_HU_HU_H, 0x744e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_WU_WU_W, 0x744f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_DU_DU_D, 0x744f8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_BU_B_BU, 0x74500000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_HU_H_HU, 0x74508000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_WU_W_WU, 0x74510000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_DU_D_DU, 0x74518000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_B_BU_BU, 0x74520000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_H_HU_HU, 0x74528000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_W_WU_WU, 0x74530000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSUB_D_DU_DU, 0x74538000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHADDW_H_B, 0x74540000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHADDW_W_H, 0x74548000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHADDW_D_W, 0x74550000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHADDW_Q_D, 0x74558000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHSUBW_H_B, 0x74560000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHSUBW_W_H, 0x74568000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHSUBW_D_W, 0x74570000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHSUBW_Q_D, 0x74578000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHADDW_HU_BU, 0x74580000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHADDW_WU_HU, 0x74588000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHADDW_DU_WU, 0x74590000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHADDW_QU_DU, 0x74598000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHSUBW_HU_BU, 0x745a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHSUBW_WU_HU, 0x745a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHSUBW_DU_WU, 0x745b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHSUBW_QU_DU, 0x745b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDA_B, 0x745c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDA_H, 0x745c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDA_W, 0x745d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADDA_D, 0x745d8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADDA_B, 0x745e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADDA_H, 0x745e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADDA_W, 0x745f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADDA_D, 0x745f8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVABSD_B, 0x74600000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVABSD_H, 0x74608000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVABSD_W, 0x74610000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVABSD_D, 0x74618000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVABSD_BU, 0x74620000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVABSD_HU, 0x74628000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVABSD_WU, 0x74630000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVABSD_DU, 0x74638000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVG_B, 0x74640000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVG_H, 0x74648000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVG_W, 0x74650000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVG_D, 0x74658000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVG_BU, 0x74660000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVG_HU, 0x74668000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVG_WU, 0x74670000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVG_DU, 0x74678000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVGR_B, 0x74680000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVGR_H, 0x74688000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVGR_W, 0x74690000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVGR_D, 0x74698000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVGR_BU, 0x746a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVGR_HU, 0x746a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVGR_WU, 0x746b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVAVGR_DU, 0x746b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHALFD_B, 0x746c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHALFD_H, 0x746c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHALFD_W, 0x746d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHALFD_D, 0x746d8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHALFD_BU, 0x746e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHALFD_HU, 0x746e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHALFD_WU, 0x746f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHALFD_DU, 0x746f8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAX_B, 0x74700000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAX_H, 0x74708000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAX_W, 0x74710000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAX_D, 0x74718000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMIN_B, 0x74720000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMIN_H, 0x74728000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMIN_W, 0x74730000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMIN_D, 0x74738000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAX_BU, 0x74740000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAX_HU, 0x74748000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAX_WU, 0x74750000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAX_DU, 0x74758000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMIN_BU, 0x74760000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMIN_HU, 0x74768000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMIN_WU, 0x74770000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMIN_DU, 0x74778000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAXA_B, 0x74780000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAXA_H, 0x74788000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAXA_W, 0x74790000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMAXA_D, 0x74798000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMINA_B, 0x747a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMINA_H, 0x747a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMINA_W, 0x747b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMINA_D, 0x747b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADW_H_B, 0x747c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADW_W_H, 0x747c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADW_D_W, 0x747d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADW_H_BU, 0x747e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADW_W_HU, 0x747e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSADW_D_WU, 0x747f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVACCSADW_H_B, 0x74800000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVACCSADW_W_H, 0x74808000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVACCSADW_D_W, 0x74810000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVACCSADW_H_BU, 0x74820000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVACCSADW_W_HU, 0x74828000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVACCSADW_D_WU, 0x74830000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUL_B, 0x74840000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUL_H, 0x74848000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUL_W, 0x74850000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUL_D, 0x74858000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_B, 0x74860000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_H, 0x74868000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_W, 0x74870000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_D, 0x74878000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_BU, 0x74880000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_HU, 0x74888000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_WU, 0x74890000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_DU, 0x74898000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_BU_B, 0x748a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_HU_H, 0x748a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_WU_W, 0x748b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMUH_DU_D, 0x748b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULXW_H_B, 0x748c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULXW_W_H, 0x748c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULXW_D_W, 0x748d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULXW_H_BU, 0x748e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULXW_W_HU, 0x748e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULXW_D_WU, 0x748f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_H_B, 0x74900000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_W_H, 0x74908000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_D_W, 0x74910000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_Q_D, 0x74918000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_H_B, 0x74920000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_W_H, 0x74928000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_D_W, 0x74930000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_Q_D, 0x74938000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_H_B, 0x74940000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_W_H, 0x74948000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_D_W, 0x74950000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_Q_D, 0x74958000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_H_B, 0x74960000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_W_H, 0x74968000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_D_W, 0x74970000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_Q_D, 0x74978000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_H_BU, 0x74980000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_W_HU, 0x74988000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_D_WU, 0x74990000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_Q_DU, 0x74998000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_H_BU, 0x749a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_W_HU, 0x749a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_D_WU, 0x749b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_Q_DU, 0x749b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_H_BU, 0x749c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_W_HU, 0x749c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_D_WU, 0x749d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_Q_DU, 0x749d8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_H_BU, 0x749e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_W_HU, 0x749e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_D_WU, 0x749f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_Q_DU, 0x749f8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_H_BU_B, 0x74a00000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_W_HU_H, 0x74a08000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_D_WU_W, 0x74a10000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWEV_Q_DU_D, 0x74a18000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_H_BU_B, 0x74a20000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_W_HU_H, 0x74a28000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_D_WU_W, 0x74a30000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWOD_Q_DU_D, 0x74a38000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_H_BU_B, 0x74a40000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_W_HU_H, 0x74a48000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_D_WU_W, 0x74a50000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWL_Q_DU_D, 0x74a58000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_H_BU_B, 0x74a60000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_W_HU_H, 0x74a68000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_D_WU_W, 0x74a70000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMULWH_Q_DU_D, 0x74a78000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADD_B, 0x74a80000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADD_H, 0x74a88000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADD_W, 0x74a90000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADD_D, 0x74a98000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMSUB_B, 0x74aa0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMSUB_H, 0x74aa8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMSUB_W, 0x74ab0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMSUB_D, 0x74ab8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_H_B, 0x74ac0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_W_H, 0x74ac8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_D_W, 0x74ad0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_Q_D, 0x74ad8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_H_B, 0x74ae0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_W_H, 0x74ae8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_D_W, 0x74af0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_Q_D, 0x74af8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_H_B, 0x74b00000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_W_H, 0x74b08000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_D_W, 0x74b10000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_Q_D, 0x74b18000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_H_B, 0x74b20000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_W_H, 0x74b28000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_D_W, 0x74b30000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_Q_D, 0x74b38000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_H_BU, 0x74b40000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_W_HU, 0x74b48000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_D_WU, 0x74b50000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_Q_DU, 0x74b58000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_H_BU, 0x74b60000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_W_HU, 0x74b68000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_D_WU, 0x74b70000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_Q_DU, 0x74b78000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_H_BU, 0x74b80000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_W_HU, 0x74b88000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_D_WU, 0x74b90000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_Q_DU, 0x74b98000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_H_BU, 0x74ba0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_W_HU, 0x74ba8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_D_WU, 0x74bb0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_Q_DU, 0x74bb8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_H_BU_B, 0x74bc0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_W_HU_H, 0x74bc8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_D_WU_W, 0x74bd0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWEV_Q_DU_D, 0x74bd8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_H_BU_B, 0x74be0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_W_HU_H, 0x74be8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_D_WU_W, 0x74bf0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWOD_Q_DU_D, 0x74bf8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_H_BU_B, 0x74c00000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_W_HU_H, 0x74c08000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_D_WU_W, 0x74c10000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWL_Q_DU_D, 0x74c18000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_H_BU_B, 0x74c20000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_W_HU_H, 0x74c28000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_D_WU_W, 0x74c30000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMADDWH_Q_DU_D, 0x74c38000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_H_B, 0x74c40000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_W_H, 0x74c48000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_D_W, 0x74c50000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_Q_D, 0x74c58000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_HU_BU, 0x74c60000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_WU_HU, 0x74c68000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_DU_WU, 0x74c70000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_QU_DU, 0x74c78000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_H_BU_B, 0x74c80000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_W_HU_H, 0x74c88000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_D_WU_W, 0x74c90000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2_Q_DU_D, 0x74c98000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_H_B, 0x74ca0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_W_H, 0x74ca8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_D_W, 0x74cb0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_Q_D, 0x74cb8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_H_BU, 0x74cc0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_W_HU, 0x74cc8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_D_WU, 0x74cd0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_Q_DU, 0x74cd8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_H_BU_B, 0x74ce0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_W_HU_H, 0x74ce8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_D_WU_W, 0x74cf0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2ADD_Q_DU_D, 0x74cf8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2SUB_H_B, 0x74d00000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2SUB_W_H, 0x74d08000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2SUB_D_W, 0x74d10000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2SUB_Q_D, 0x74d18000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2SUB_H_BU, 0x74d20000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2SUB_W_HU, 0x74d28000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2SUB_D_WU, 0x74d30000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP2SUB_Q_DU, 0x74d38000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4_W_B, 0x74d40000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4_D_H, 0x74d48000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4_Q_W, 0x74d50000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4_W_BU, 0x74d60000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4_D_HU, 0x74d68000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4_Q_WU, 0x74d70000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4_W_BU_B, 0x74d80000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4_D_HU_H, 0x74d88000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4_Q_WU_W, 0x74d90000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4ADD_W_B, 0x74da0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4ADD_D_H, 0x74da8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4ADD_Q_W, 0x74db0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4ADD_W_BU, 0x74dc0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4ADD_D_HU, 0x74dc8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4ADD_Q_WU, 0x74dd0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4ADD_W_BU_B, 0x74de0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4ADD_D_HU_H, 0x74de8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDP4ADD_Q_WU_W, 0x74df0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDIV_B, 0x74e00000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDIV_H, 0x74e08000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDIV_W, 0x74e10000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDIV_D, 0x74e18000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMOD_B, 0x74e20000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMOD_H, 0x74e28000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMOD_W, 0x74e30000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMOD_D, 0x74e38000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDIV_BU, 0x74e40000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDIV_HU, 0x74e48000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDIV_WU, 0x74e50000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVDIV_DU, 0x74e58000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMOD_BU, 0x74e60000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMOD_HU, 0x74e68000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMOD_WU, 0x74e70000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVMOD_DU, 0x74e78000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLL_B, 0x74e80000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLL_H, 0x74e88000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLL_W, 0x74e90000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSLL_D, 0x74e98000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRL_B, 0x74ea0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRL_H, 0x74ea8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRL_W, 0x74eb0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRL_D, 0x74eb8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRA_B, 0x74ec0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRA_H, 0x74ec8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRA_W, 0x74ed0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRA_D, 0x74ed8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVROTR_B, 0x74ee0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVROTR_H, 0x74ee8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVROTR_W, 0x74ef0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVROTR_D, 0x74ef8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRLR_B, 0x74f00000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRLR_H, 0x74f08000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRLR_W, 0x74f10000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRLR_D, 0x74f18000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRAR_B, 0x74f20000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRAR_H, 0x74f28000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRAR_W, 0x74f30000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRAR_D, 0x74f38000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRLN_B_H, 0x74f48000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRLN_H_W, 0x74f50000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRLN_W_D, 0x74f58000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRAN_B_H, 0x74f68000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRAN_H_W, 0x74f70000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRAN_W_D, 0x74f78000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRLRN_B_H, 0x74f88000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRLRN_H_W, 0x74f90000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRLRN_W_D, 0x74f98000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRARN_B_H, 0x74fa8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRARN_H_W, 0x74fb0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSRARN_W_D, 0x74fb8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLN_B_H, 0x74fc8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLN_H_W, 0x74fd0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLN_W_D, 0x74fd8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRAN_B_H, 0x74fe8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRAN_H_W, 0x74ff0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRAN_W_D, 0x74ff8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLRN_B_H, 0x75008000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLRN_H_W, 0x75010000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLRN_W_D, 0x75018000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRARN_B_H, 0x75028000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRARN_H_W, 0x75030000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRARN_W_D, 0x75038000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLN_BU_H, 0x75048000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLN_HU_W, 0x75050000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLN_WU_D, 0x75058000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRAN_BU_H, 0x75068000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRAN_HU_W, 0x75070000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRAN_WU_D, 0x75078000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLRN_BU_H, 0x75088000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLRN_HU_W, 0x75090000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRLRN_WU_D, 0x75098000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRARN_BU_H, 0x750a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRARN_HU_W, 0x750b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSSRARN_WU_D, 0x750b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITCLR_B, 0x750c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITCLR_H, 0x750c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITCLR_W, 0x750d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITCLR_D, 0x750d8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITSET_B, 0x750e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITSET_H, 0x750e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITSET_W, 0x750f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITSET_D, 0x750f8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITREV_B, 0x75100000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITREV_H, 0x75108000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITREV_W, 0x75110000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBITREV_D, 0x75118000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBSTRC12_B, 0x75120000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBSTRC12_H, 0x75128000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBSTRC12_W, 0x75130000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBSTRC12_D, 0x75138000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBSTRC21_B, 0x75140000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBSTRC21_H, 0x75148000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBSTRC21_W, 0x75150000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVBSTRC21_D, 0x75158000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPACKEV_B, 0x75160000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPACKEV_H, 0x75168000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPACKEV_W, 0x75170000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPACKEV_D, 0x75178000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPACKOD_B, 0x75180000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPACKOD_H, 0x75188000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPACKOD_W, 0x75190000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPACKOD_D, 0x75198000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVILVL_B, 0x751a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVILVL_H, 0x751a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVILVL_W, 0x751b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVILVL_D, 0x751b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVILVH_B, 0x751c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVILVH_H, 0x751c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVILVH_W, 0x751d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVILVH_D, 0x751d8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPICKEV_B, 0x751e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPICKEV_H, 0x751e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPICKEV_W, 0x751f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPICKEV_D, 0x751f8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPICKOD_B, 0x75200000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPICKOD_H, 0x75208000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPICKOD_W, 0x75210000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPICKOD_D, 0x75218000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVREPLVE_B, 0x75220000, {FPR_XD, FPR_XJ, GPR_RK}}, + {LISA_XVREPLVE_H, 0x75228000, {FPR_XD, FPR_XJ, GPR_RK}}, + {LISA_XVREPLVE_W, 0x75230000, {FPR_XD, FPR_XJ, GPR_RK}}, + {LISA_XVREPLVE_D, 0x75238000, {FPR_XD, FPR_XJ, GPR_RK}}, + {LISA_XVEXTRCOL_B, 0x75240000, {FPR_XD, FPR_XJ, GPR_RK}}, + {LISA_XVEXTRCOL_H, 0x75248000, {FPR_XD, FPR_XJ, GPR_RK}}, + {LISA_XVEXTRCOL_W, 0x75250000, {FPR_XD, FPR_XJ, GPR_RK}}, + {LISA_XVEXTRCOL_D, 0x75258000, {FPR_XD, FPR_XJ, GPR_RK}}, + {LISA_XVAND_V, 0x75260000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVOR_V, 0x75268000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVXOR_V, 0x75270000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVNOR_V, 0x75278000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVANDN_V, 0x75280000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVORN_V, 0x75288000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVRANDSIGN_B, 0x75290000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVRANDSIGN_H, 0x75298000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVRORSIGN_B, 0x752a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVRORSIGN_H, 0x752a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFRSTP_B, 0x752b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFRSTP_H, 0x752b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVCLRSTRR_V, 0x752c0000, {FPR_XD, FPR_XJ, GPR_RK}}, + {LISA_XVCLRSTRV_V, 0x752c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVADD_Q, 0x752d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSUB_Q, 0x752d8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSIGNCOV_B, 0x752e0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSIGNCOV_H, 0x752e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSIGNCOV_W, 0x752f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSIGNCOV_D, 0x752f8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFADD_S, 0x75308000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFADD_D, 0x75310000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFSUB_S, 0x75328000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFSUB_D, 0x75330000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFADDSUB_S, 0x75348000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFADDSUB_D, 0x75350000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFSUBADD_S, 0x75368000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFSUBADD_D, 0x75370000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFMUL_S, 0x75388000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFMUL_D, 0x75390000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFDIV_S, 0x753a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFDIV_D, 0x753b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFMAX_S, 0x753c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFMAX_D, 0x753d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFMIN_S, 0x753e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFMIN_D, 0x753f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFMAXA_S, 0x75408000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFMAXA_D, 0x75410000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFMINA_S, 0x75428000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFMINA_D, 0x75430000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFSCALEB_S, 0x75448000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFSCALEB_D, 0x75450000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFCVT_H_S, 0x75460000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFCVT_S_D, 0x75468000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFFINT_S_L, 0x75480000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFTINT_W_D, 0x75498000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFTINTRM_W_D, 0x754a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFTINTRP_W_D, 0x754a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFTINTRZ_W_D, 0x754b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVFTINTRNE_W_D, 0x754b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVHADD4_H_BU, 0x754e8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSHUF4_W, 0x754f0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSHUF2_D, 0x754f8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMUL_W, 0x75600000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMUL_D, 0x75608000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMUH_W, 0x75610000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMUH_D, 0x75618000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMULACC_W, 0x75620000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMULACC_D, 0x75628000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMUHACC_W, 0x75630000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMUHACC_D, 0x75638000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMULWL_H_B, 0x75640000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMULWL_W_H, 0x75648000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMULWL_D_W, 0x75650000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMULWL_Q_D, 0x75658000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMULWH_H_B, 0x75660000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMULWH_W_H, 0x75668000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMULWH_D_W, 0x75670000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMULWH_Q_D, 0x75678000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMADDWL_H_B, 0x75680000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMADDWL_W_H, 0x75688000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMADDWL_D_W, 0x75690000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMADDWL_Q_D, 0x75698000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMADDWH_H_B, 0x756a0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMADDWH_W_H, 0x756a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMADDWH_D_W, 0x756b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPMADDWH_Q_D, 0x756b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPDP2_Q_D, 0x756c0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPDP2ADD_Q_D, 0x756c8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVCDP4_RE_D_H, 0x75700000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVCDP4_IM_D_H, 0x75708000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVCDP4ADD_RE_D_H, 0x75710000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVCDP4ADD_IM_D_H, 0x75718000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVCDP2_RE_Q_W, 0x75720000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVCDP2_IM_Q_W, 0x75728000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVCDP2ADD_RE_Q_W, 0x75730000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVCDP2ADD_IM_Q_W, 0x75738000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSIGNSEL_W, 0x75790000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSIGNSEL_D, 0x75798000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSHUF_H, 0x757a8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSHUF_W, 0x757b0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSHUF_D, 0x757b8000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVPERM_W, 0x757d0000, {FPR_XD, FPR_XJ, FPR_XK}}, + {LISA_XVSEQI_B, 0x76800000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSEQI_H, 0x76808000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSEQI_W, 0x76810000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSEQI_D, 0x76818000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSLEI_B, 0x76820000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSLEI_H, 0x76828000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSLEI_W, 0x76830000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSLEI_D, 0x76838000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSLEI_BU, 0x76840000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSLEI_HU, 0x76848000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSLEI_WU, 0x76850000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSLEI_DU, 0x76858000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSLTI_B, 0x76860000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSLTI_H, 0x76868000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSLTI_W, 0x76870000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSLTI_D, 0x76878000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVSLTI_BU, 0x76880000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSLTI_HU, 0x76888000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSLTI_WU, 0x76890000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSLTI_DU, 0x76898000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVADDI_BU, 0x768a0000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVADDI_HU, 0x768a8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVADDI_WU, 0x768b0000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVADDI_DU, 0x768b8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSUBI_BU, 0x768c0000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSUBI_HU, 0x768c8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSUBI_WU, 0x768d0000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSUBI_DU, 0x768d8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVBSLL_V, 0x768e0000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVBSRL_V, 0x768e8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVMAXI_B, 0x76900000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVMAXI_H, 0x76908000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVMAXI_W, 0x76910000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVMAXI_D, 0x76918000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVMINI_B, 0x76920000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVMINI_H, 0x76928000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVMINI_W, 0x76930000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVMINI_D, 0x76938000, {FPR_XD, FPR_XJ, IMM_SI5}}, + {LISA_XVMAXI_BU, 0x76940000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVMAXI_HU, 0x76948000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVMAXI_WU, 0x76950000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVMAXI_DU, 0x76958000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVMINI_BU, 0x76960000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVMINI_HU, 0x76968000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVMINI_WU, 0x76970000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVMINI_DU, 0x76978000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVRANDSIGNI_B, 0x76980000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVRANDSIGNI_H, 0x76988000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVRORSIGNI_B, 0x76990000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVRORSIGNI_H, 0x76998000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVFRSTPI_B, 0x769a0000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVFRSTPI_H, 0x769a8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVCLRSTRI_V, 0x769b0000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVMEPATMSK_V, 0x769b8000, {FPR_XD, IMM_MODE, IMM_UI5L}}, + {LISA_XVCLO_B, 0x769c0000, {FPR_XD, FPR_XJ}}, + {LISA_XVCLO_H, 0x769c0400, {FPR_XD, FPR_XJ}}, + {LISA_XVCLO_W, 0x769c0800, {FPR_XD, FPR_XJ}}, + {LISA_XVCLO_D, 0x769c0c00, {FPR_XD, FPR_XJ}}, + {LISA_XVCLZ_B, 0x769c1000, {FPR_XD, FPR_XJ}}, + {LISA_XVCLZ_H, 0x769c1400, {FPR_XD, FPR_XJ}}, + {LISA_XVCLZ_W, 0x769c1800, {FPR_XD, FPR_XJ}}, + {LISA_XVCLZ_D, 0x769c1c00, {FPR_XD, FPR_XJ}}, + {LISA_XVPCNT_B, 0x769c2000, {FPR_XD, FPR_XJ}}, + {LISA_XVPCNT_H, 0x769c2400, {FPR_XD, FPR_XJ}}, + {LISA_XVPCNT_W, 0x769c2800, {FPR_XD, FPR_XJ}}, + {LISA_XVPCNT_D, 0x769c2c00, {FPR_XD, FPR_XJ}}, + {LISA_XVNEG_B, 0x769c3000, {FPR_XD, FPR_XJ}}, + {LISA_XVNEG_H, 0x769c3400, {FPR_XD, FPR_XJ}}, + {LISA_XVNEG_W, 0x769c3800, {FPR_XD, FPR_XJ}}, + {LISA_XVNEG_D, 0x769c3c00, {FPR_XD, FPR_XJ}}, + {LISA_XVMSKLTZ_B, 0x769c4000, {FPR_XD, FPR_XJ}}, + {LISA_XVMSKLTZ_H, 0x769c4400, {FPR_XD, FPR_XJ}}, + {LISA_XVMSKLTZ_W, 0x769c4800, {FPR_XD, FPR_XJ}}, + {LISA_XVMSKLTZ_D, 0x769c4c00, {FPR_XD, FPR_XJ}}, + {LISA_XVMSKGEZ_B, 0x769c5000, {FPR_XD, FPR_XJ}}, + {LISA_XVMSKNZ_B, 0x769c6000, {FPR_XD, FPR_XJ}}, + {LISA_XVMSKCOPY_B, 0x769c7000, {FPR_XD, FPR_XJ}}, + {LISA_XVMSKFILL_B, 0x769c8000, {FPR_XD, FPR_XJ}}, + {LISA_XVFRSTM_B, 0x769c9000, {FPR_XD, FPR_XJ}}, + {LISA_XVFRSTM_H, 0x769c9400, {FPR_XD, FPR_XJ}}, + {LISA_XVSETEQZ_V, 0x769c9800, {FCC_CD, FPR_XJ}}, + {LISA_XVSETNEZ_V, 0x769c9c00, {FCC_CD, FPR_XJ}}, + {LISA_XVSETANYEQZ_B, 0x769ca000, {FCC_CD, FPR_XJ}}, + {LISA_XVSETANYEQZ_H, 0x769ca400, {FCC_CD, FPR_XJ}}, + {LISA_XVSETANYEQZ_W, 0x769ca800, {FCC_CD, FPR_XJ}}, + {LISA_XVSETANYEQZ_D, 0x769cac00, {FCC_CD, FPR_XJ}}, + {LISA_XVSETALLNEZ_B, 0x769cb000, {FCC_CD, FPR_XJ}}, + {LISA_XVSETALLNEZ_H, 0x769cb400, {FCC_CD, FPR_XJ}}, + {LISA_XVSETALLNEZ_W, 0x769cb800, {FCC_CD, FPR_XJ}}, + {LISA_XVSETALLNEZ_D, 0x769cbc00, {FCC_CD, FPR_XJ}}, + {LISA_XVFLOGB_S, 0x769cc400, {FPR_XD, FPR_XJ}}, + {LISA_XVFLOGB_D, 0x769cc800, {FPR_XD, FPR_XJ}}, + {LISA_XVFCLASS_S, 0x769cd400, {FPR_XD, FPR_XJ}}, + {LISA_XVFCLASS_D, 0x769cd800, {FPR_XD, FPR_XJ}}, + {LISA_XVFSQRT_S, 0x769ce400, {FPR_XD, FPR_XJ}}, + {LISA_XVFSQRT_D, 0x769ce800, {FPR_XD, FPR_XJ}}, + {LISA_XVFRECIP_S, 0x769cf400, {FPR_XD, FPR_XJ}}, + {LISA_XVFRECIP_D, 0x769cf800, {FPR_XD, FPR_XJ}}, + {LISA_XVFRSQRT_S, 0x769d0400, {FPR_XD, FPR_XJ}}, + {LISA_XVFRSQRT_D, 0x769d0800, {FPR_XD, FPR_XJ}}, + {LISA_XVFRINT_S, 0x769d3400, {FPR_XD, FPR_XJ}}, + {LISA_XVFRINT_D, 0x769d3800, {FPR_XD, FPR_XJ}}, + {LISA_XVFRINTRM_S, 0x769d4400, {FPR_XD, FPR_XJ}}, + {LISA_XVFRINTRM_D, 0x769d4800, {FPR_XD, FPR_XJ}}, + {LISA_XVFRINTRP_S, 0x769d5400, {FPR_XD, FPR_XJ}}, + {LISA_XVFRINTRP_D, 0x769d5800, {FPR_XD, FPR_XJ}}, + {LISA_XVFRINTRZ_S, 0x769d6400, {FPR_XD, FPR_XJ}}, + {LISA_XVFRINTRZ_D, 0x769d6800, {FPR_XD, FPR_XJ}}, + {LISA_XVFRINTRNE_S, 0x769d7400, {FPR_XD, FPR_XJ}}, + {LISA_XVFRINTRNE_D, 0x769d7800, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTL_W_B, 0x769d8400, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTL_D_B, 0x769d8800, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTL_D_H, 0x769d9400, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTL_W_BU, 0x769dac00, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTL_D_BU, 0x769db000, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTL_D_HU, 0x769dbc00, {FPR_XD, FPR_XJ}}, + {LISA_XVHADD8_D_BU, 0x769dd000, {FPR_XD, FPR_XJ}}, + {LISA_XVHMINPOS_W_HU, 0x769dd400, {FPR_XD, FPR_XJ}}, + {LISA_XVHMINPOS_D_HU, 0x769dd800, {FPR_XD, FPR_XJ}}, + {LISA_XVHMINPOS_Q_HU, 0x769ddc00, {FPR_XD, FPR_XJ}}, + {LISA_XVCLRTAIL_B, 0x769de000, {FPR_XD, FPR_XJ}}, + {LISA_XVCLRTAIL_H, 0x769de400, {FPR_XD, FPR_XJ}}, + {LISA_XVFCVTL_S_H, 0x769de800, {FPR_XD, FPR_XJ}}, + {LISA_XVFCVTH_S_H, 0x769dec00, {FPR_XD, FPR_XJ}}, + {LISA_XVFCVTL_D_S, 0x769df000, {FPR_XD, FPR_XJ}}, + {LISA_XVFCVTH_D_S, 0x769df400, {FPR_XD, FPR_XJ}}, + {LISA_XVFFINT_S_W, 0x769e0000, {FPR_XD, FPR_XJ}}, + {LISA_XVFFINT_S_WU, 0x769e0400, {FPR_XD, FPR_XJ}}, + {LISA_XVFFINT_D_L, 0x769e0800, {FPR_XD, FPR_XJ}}, + {LISA_XVFFINT_D_LU, 0x769e0c00, {FPR_XD, FPR_XJ}}, + {LISA_XVFFINTL_D_W, 0x769e1000, {FPR_XD, FPR_XJ}}, + {LISA_XVFFINTH_D_W, 0x769e1400, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINT_W_S, 0x769e3000, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINT_L_D, 0x769e3400, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRM_W_S, 0x769e3800, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRM_L_D, 0x769e3c00, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRP_W_S, 0x769e4000, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRP_L_D, 0x769e4400, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRZ_W_S, 0x769e4800, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRZ_L_D, 0x769e4c00, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRNE_W_S, 0x769e5000, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRNE_L_D, 0x769e5400, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINT_WU_S, 0x769e5800, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINT_LU_D, 0x769e5c00, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRZ_WU_S, 0x769e7000, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRZ_LU_D, 0x769e7400, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTL_L_S, 0x769e8000, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTH_L_S, 0x769e8400, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRML_L_S, 0x769e8800, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRMH_L_S, 0x769e8c00, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRPL_L_S, 0x769e9000, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRPH_L_S, 0x769e9400, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRZL_L_S, 0x769e9800, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRZH_L_S, 0x769e9c00, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRNEL_L_S, 0x769ea000, {FPR_XD, FPR_XJ}}, + {LISA_XVFTINTRNEH_L_S, 0x769ea400, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTH_H_B, 0x769ee000, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTH_W_H, 0x769ee400, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTH_D_W, 0x769ee800, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTH_Q_D, 0x769eec00, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTH_HU_BU, 0x769ef000, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTH_WU_HU, 0x769ef400, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTH_DU_WU, 0x769ef800, {FPR_XD, FPR_XJ}}, + {LISA_XVEXTH_QU_DU, 0x769efc00, {FPR_XD, FPR_XJ}}, + {LISA_XVREPLGR2VR_B, 0x769f0000, {FPR_XD, GPR_RJ}}, + {LISA_XVREPLGR2VR_H, 0x769f0400, {FPR_XD, GPR_RJ}}, + {LISA_XVREPLGR2VR_W, 0x769f0800, {FPR_XD, GPR_RJ}}, + {LISA_XVREPLGR2VR_D, 0x769f0c00, {FPR_XD, GPR_RJ}}, + {LISA_VEXT2XV_H_B, 0x769f1000, {FPR_XD, FPR_XJ}}, + {LISA_VEXT2XV_W_B, 0x769f1400, {FPR_XD, FPR_XJ}}, + {LISA_VEXT2XV_D_B, 0x769f1800, {FPR_XD, FPR_XJ}}, + {LISA_VEXT2XV_W_H, 0x769f1c00, {FPR_XD, FPR_XJ}}, + {LISA_VEXT2XV_D_H, 0x769f2000, {FPR_XD, FPR_XJ}}, + {LISA_VEXT2XV_D_W, 0x769f2400, {FPR_XD, FPR_XJ}}, + {LISA_VEXT2XV_HU_BU, 0x769f2800, {FPR_XD, FPR_XJ}}, + {LISA_VEXT2XV_WU_BU, 0x769f2c00, {FPR_XD, FPR_XJ}}, + {LISA_VEXT2XV_DU_BU, 0x769f3000, {FPR_XD, FPR_XJ}}, + {LISA_VEXT2XV_WU_HU, 0x769f3400, {FPR_XD, FPR_XJ}}, + {LISA_VEXT2XV_DU_HU, 0x769f3800, {FPR_XD, FPR_XJ}}, + {LISA_VEXT2XV_DU_WU, 0x769f3c00, {FPR_XD, FPR_XJ}}, + {LISA_XVHSELI_D, 0x769f8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVROTRI_B, 0x76a02000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVROTRI_H, 0x76a04000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVROTRI_W, 0x76a08000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVROTRI_D, 0x76a10000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSRLRI_B, 0x76a42000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVSRLRI_H, 0x76a44000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSRLRI_W, 0x76a48000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSRLRI_D, 0x76a50000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSRARI_B, 0x76a82000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVSRARI_H, 0x76a84000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSRARI_W, 0x76a88000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSRARI_D, 0x76a90000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVINSGR2VR_W, 0x76ebc000, {FPR_XD, GPR_RJ, IMM_UI3}}, + {LISA_XVINSGR2VR_D, 0x76ebe000, {FPR_XD, GPR_RJ, IMM_UI2}}, + {LISA_XVPICKVE2GR_W, 0x76efc000, {GPR_RD, FPR_XJ, IMM_UI3}}, + {LISA_XVPICKVE2GR_D, 0x76efe000, {GPR_RD, FPR_XJ, IMM_UI2}}, + {LISA_XVPICKVE2GR_WU, 0x76f3c000, {GPR_RD, FPR_XJ, IMM_UI3}}, + {LISA_XVPICKVE2GR_DU, 0x76f3e000, {GPR_RD, FPR_XJ, IMM_UI2}}, + {LISA_XVREPL128VEI_B, 0x76f78000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVREPL128VEI_H, 0x76f7c000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVREPL128VEI_W, 0x76f7e000, {FPR_XD, FPR_XJ, IMM_UI2}}, + {LISA_XVREPL128VEI_D, 0x76f7f000, {FPR_XD, FPR_XJ, IMM_UI1}}, + {LISA_XVEXTRCOLI_B, 0x76fb8000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVEXTRCOLI_H, 0x76fbc000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVEXTRCOLI_W, 0x76fbe000, {FPR_XD, FPR_XJ, IMM_UI2}}, + {LISA_XVEXTRCOLI_D, 0x76fbf000, {FPR_XD, FPR_XJ, IMM_UI1}}, + {LISA_XVINSVE0_W, 0x76ffc000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVINSVE0_D, 0x76ffe000, {FPR_XD, FPR_XJ, IMM_UI2}}, + {LISA_XVPICKVE_W, 0x7703c000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVPICKVE_D, 0x7703e000, {FPR_XD, FPR_XJ, IMM_UI2}}, + {LISA_XVREPLVE0_B, 0x77070000, {FPR_XD, FPR_XJ}}, + {LISA_XVREPLVE0_H, 0x77078000, {FPR_XD, FPR_XJ}}, + {LISA_XVREPLVE0_W, 0x7707c000, {FPR_XD, FPR_XJ}}, + {LISA_XVREPLVE0_D, 0x7707e000, {FPR_XD, FPR_XJ}}, + {LISA_XVREPLVE0_Q, 0x7707f000, {FPR_XD, FPR_XJ}}, + {LISA_XVSLLWIL_H_B, 0x77082000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVSLLWIL_W_H, 0x77084000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSLLWIL_D_W, 0x77088000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVEXTL_Q_D, 0x77090000, {FPR_XD, FPR_XJ}}, + {LISA_XVSLLWIL_HU_BU, 0x770c2000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVSLLWIL_WU_HU, 0x770c4000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSLLWIL_DU_WU, 0x770c8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVEXTL_QU_DU, 0x770d0000, {FPR_XD, FPR_XJ}}, + {LISA_XVBITCLRI_B, 0x77102000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVBITCLRI_H, 0x77104000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVBITCLRI_W, 0x77108000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVBITCLRI_D, 0x77110000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVBITSETI_B, 0x77142000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVBITSETI_H, 0x77144000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVBITSETI_W, 0x77148000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVBITSETI_D, 0x77150000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVBITREVI_B, 0x77182000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVBITREVI_H, 0x77184000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVBITREVI_W, 0x77188000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVBITREVI_D, 0x77190000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVBSTRC12I_B, 0x771c2000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVBSTRC12I_H, 0x771c4000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVBSTRC12I_W, 0x771c8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVBSTRC12I_D, 0x771d0000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVBSTRC21I_B, 0x77202000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVBSTRC21I_H, 0x77204000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVBSTRC21I_W, 0x77208000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVBSTRC21I_D, 0x77210000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSAT_B, 0x77242000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVSAT_H, 0x77244000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSAT_W, 0x77248000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSAT_D, 0x77250000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSAT_BU, 0x77282000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVSAT_HU, 0x77284000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSAT_WU, 0x77288000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSAT_DU, 0x77290000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSLLI_B, 0x772c2000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVSLLI_H, 0x772c4000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSLLI_W, 0x772c8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSLLI_D, 0x772d0000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSRLI_B, 0x77302000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVSRLI_H, 0x77304000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSRLI_W, 0x77308000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSRLI_D, 0x77310000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSRAI_B, 0x77342000, {FPR_XD, FPR_XJ, IMM_UI3}}, + {LISA_XVSRAI_H, 0x77344000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSRAI_W, 0x77348000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSRAI_D, 0x77350000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSRLRNENI_B_H, 0x77384000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSRLRNENI_H_W, 0x77388000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSRLRNENI_W_D, 0x77390000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSRLRNENI_D_Q, 0x773a0000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSRARNENI_B_H, 0x773c4000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSRARNENI_H_W, 0x773c8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSRARNENI_W_D, 0x773d0000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSRARNENI_D_Q, 0x773e0000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSRLNI_B_H, 0x77404000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSRLNI_H_W, 0x77408000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSRLNI_W_D, 0x77410000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSRLNI_D_Q, 0x77420000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSRLRNI_B_H, 0x77444000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSRLRNI_H_W, 0x77448000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSRLRNI_W_D, 0x77450000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSRLRNI_D_Q, 0x77460000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRLNI_B_H, 0x77484000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRLNI_H_W, 0x77488000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRLNI_W_D, 0x77490000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRLNI_D_Q, 0x774a0000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRLNI_BU_H, 0x774c4000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRLNI_HU_W, 0x774c8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRLNI_WU_D, 0x774d0000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRLNI_DU_Q, 0x774e0000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRLRNI_B_H, 0x77504000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRLRNI_H_W, 0x77508000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRLRNI_W_D, 0x77510000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRLRNI_D_Q, 0x77520000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRLRNI_BU_H, 0x77544000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRLRNI_HU_W, 0x77548000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRLRNI_WU_D, 0x77550000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRLRNI_DU_Q, 0x77560000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSRANI_B_H, 0x77584000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSRANI_H_W, 0x77588000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSRANI_W_D, 0x77590000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSRANI_D_Q, 0x775a0000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSRARNI_B_H, 0x775c4000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSRARNI_H_W, 0x775c8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSRARNI_W_D, 0x775d0000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSRARNI_D_Q, 0x775e0000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRANI_B_H, 0x77604000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRANI_H_W, 0x77608000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRANI_W_D, 0x77610000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRANI_D_Q, 0x77620000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRANI_BU_H, 0x77644000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRANI_HU_W, 0x77648000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRANI_WU_D, 0x77650000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRANI_DU_Q, 0x77660000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRARNI_B_H, 0x77684000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRARNI_H_W, 0x77688000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRARNI_W_D, 0x77690000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRARNI_D_Q, 0x776a0000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRARNI_BU_H, 0x776c4000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRARNI_HU_W, 0x776c8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRARNI_WU_D, 0x776d0000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRARNI_DU_Q, 0x776e0000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRLRNENI_B_H, 0x77704000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRLRNENI_H_W, 0x77708000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRLRNENI_W_D, 0x77710000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRLRNENI_D_Q, 0x77720000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRLRNENI_BU_H, 0x77744000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRLRNENI_HU_W, 0x77748000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRLRNENI_WU_D, 0x77750000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRLRNENI_DU_Q, 0x77760000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRARNENI_B_H, 0x77784000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRARNENI_H_W, 0x77788000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRARNENI_W_D, 0x77790000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRARNENI_D_Q, 0x777a0000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVSSRARNENI_BU_H, 0x777c4000, {FPR_XD, FPR_XJ, IMM_UI4}}, + {LISA_XVSSRARNENI_HU_W, 0x777c8000, {FPR_XD, FPR_XJ, IMM_UI5L}}, + {LISA_XVSSRARNENI_WU_D, 0x777d0000, {FPR_XD, FPR_XJ, IMM_UI6}}, + {LISA_XVSSRARNENI_DU_Q, 0x777e0000, {FPR_XD, FPR_XJ, IMM_UI7}}, + {LISA_XVEXTRINS_D, 0x77800000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVEXTRINS_W, 0x77840000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVEXTRINS_H, 0x77880000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVEXTRINS_B, 0x778c0000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSHUF4I_B, 0x77900000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSHUF4I_H, 0x77940000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSHUF4I_W, 0x77980000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSHUF4I_D, 0x779c0000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSHUFI1_B, 0x77a00000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSHUFI2_B, 0x77a40000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSHUFI3_B, 0x77a80000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSHUFI4_B, 0x77ac0000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSHUFI1_H, 0x77b00000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSHUFI2_H, 0x77b40000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSELI_H, 0x77b80000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSELI_W, 0x77bc0000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVSELI_D, 0x77c00000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVBITSELI_B, 0x77c40000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVBITMVZI_B, 0x77c80000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVBITMVNZI_B, 0x77cc0000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVANDI_B, 0x77d00000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVORI_B, 0x77d40000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVXORI_B, 0x77d80000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVNORI_B, 0x77dc0000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVLDI, 0x77e00000, {FPR_XD, IMM_I13}}, + {LISA_XVPERMI_W, 0x77e40000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVPERMI_D, 0x77e80000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_XVPERMI_Q, 0x77ec0000, {FPR_XD, FPR_XJ, IMM_UI8}}, + {LISA_ENDING, 0x0, {}}, +}; + +static bool is_la_sign_opnd[] = { + 0,//OPD_INVALID + 0,//OPD_CA + 0,//OPD_CD + 0,//OPD_CJ + 0,//OPD_CODE + 0,//OPD_CONDF + 0,//OPD_CONDH + 0,//OPD_CONDL + 0,//OPD_CSR + 0,//OPD_FA + 0,//OPD_FCSRH + 0,//OPD_FCSRL + 0,//OPD_FD + 0,//OPD_FJ + 0,//OPD_FK + 0,//OPD_HINTL + 0,//OPD_HINTS + 1,//OPD_I13 + 0,//OPD_IDXS + 0,//OPD_IDXM + 0,//OPD_IDXL + 0,//OPD_IDXLL + 0,//OPD_LEVEL + 0,//OPD_LSBD + 0,//OPD_LSBW + 0,//OPD_MODE + 0,//OPD_MSBD + 0,//OPD_MSBW + 1,//OPD_OFFS + 1,//OPD_OFFL + 1,//OPD_OFFLL + 0,//OPD_OPCACHE + 0,//OPD_OPX86 + 0,//OPD_PTR + 0,//OPD_RD + 0,//OPD_RJ + 0,//OPD_RK + 0,//OPD_SA2 + 0,//OPD_SA3 + 0,//OPD_SD + 0,//OPD_SEQ + 1,//OPD_SI10 + 1,//OPD_SI11 + 1,//OPD_SI12 + 1,//OPD_SI14 + 1,//OPD_SI16 + 1,//OPD_SI20 + 1,//OPD_SI5 + 1,//OPD_SI8 + 1,//OPD_SI9 + 0,//OPD_SJ + 0,//OPD_UI1 + 0,//OPD_UI12 + 0,//OPD_UI2 + 0,//OPD_UI3 + 0,//OPD_UI4 + 0,//OPD_UI5H + 0,//OPD_UI5L + 0,//OPD_UI6 + 0,//OPD_UI7 + 0,//OPD_UI8 + 0,//OPD_VA + 0,//OPD_VD + 0,//OPD_VJ + 0,//OPD_VK + 0,//OPD_XA + 0,//OPD_XD + 0,//OPD_XJ + 0,//OPD_XK +}; + +LA_OPCODE get_ins_op(uint32_t insn) +{ + switch ((insn >> 26) & 0x3f) { + case 0x0: + switch ((insn >> 22) & 0xf) { + case 0x0: + switch ((insn >> 18) & 0xf) { + case 0x0: + switch ((insn >> 15) & 0x7) { + case 0x0: + switch ((insn >> 10) & 0x1f) { + case 0x2: + switch ((insn >> 2) & 0x7) { + case 0x0: return LISA_GR2SCR; + } + break; + case 0x3: + switch ((insn >> 7) & 0x7) { + case 0x0: return LISA_SCR2GR; + } + break; + case 0x4: return LISA_CLO_W; + case 0x5: return LISA_CLZ_W; + case 0x6: return LISA_CTO_W; + case 0x7: return LISA_CTZ_W; + case 0x8: return LISA_CLO_D; + case 0x9: return LISA_CLZ_D; + case 0xa: return LISA_CTO_D; + case 0xb: return LISA_CTZ_D; + case 0xc: return LISA_REVB_2H; + case 0xd: return LISA_REVB_4H; + case 0xe: return LISA_REVB_2W; + case 0xf: return LISA_REVB_D; + case 0x10: return LISA_REVH_2W; + case 0x11: return LISA_REVH_D; + case 0x12: return LISA_BITREV_4B; + case 0x13: return LISA_BITREV_8B; + case 0x14: return LISA_BITREV_W; + case 0x15: return LISA_BITREV_D; + case 0x16: return LISA_EXT_W_H; + case 0x17: return LISA_EXT_W_B; + case 0x18: return LISA_RDTIMEL_W; + case 0x19: return LISA_RDTIMEH_W; + case 0x1a: return LISA_RDTIME_D; + case 0x1b: return LISA_CPUCFG; + case 0x1e: return LISA_X86LOOPE; + case 0x1f: return LISA_X86LOOPNE; + } + break; + case 0x1: + switch (insn & 0x00007c1f) { + case 0x00000000: return LISA_X86INC_B; + case 0x00000001: return LISA_X86INC_H; + case 0x00000002: return LISA_X86INC_W; + case 0x00000003: return LISA_X86INC_D; + case 0x00000004: return LISA_X86DEC_B; + case 0x00000005: return LISA_X86DEC_H; + case 0x00000006: return LISA_X86DEC_W; + case 0x00000007: return LISA_X86DEC_D; + case 0x00000008: + switch ((insn >> 5) & 0x1f) { + case 0x0: return LISA_X86SETTM; + case 0x1: return LISA_X86CLRTM; + } + break; + case 0x00000009: + switch ((insn >> 5) & 0x1f) { + case 0x0: return LISA_X86INCTOP; + case 0x1: return LISA_X86DECTOP; + } + break; + } + break; + case 0x2: + switch (insn & 0x0000001f) { + case 0x00000000: return LISA_ASRTLE_D; + } + break; + case 0x3: + switch (insn & 0x0000001f) { + case 0x00000000: return LISA_ASRTGT_D; + } + break; + } + break; + case 0x1: + switch ((insn >> 17) & 0x1) { + case 0x0: return LISA_ALSL_W; + case 0x1: return LISA_ALSL_WU; + } + break; + case 0x2: + switch ((insn >> 17) & 0x1) { + case 0x0: return LISA_BYTEPICK_W; + } + break; + case 0x3: return LISA_BYTEPICK_D; + case 0x4: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_ADD_W; + case 0x1: return LISA_ADD_D; + case 0x2: return LISA_SUB_W; + case 0x3: return LISA_SUB_D; + case 0x4: return LISA_SLT; + case 0x5: return LISA_SLTU; + case 0x6: return LISA_MASKEQZ; + case 0x7: return LISA_MASKNEZ; + } + break; + case 0x5: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_NOR; + case 0x1: return LISA_AND; + case 0x2: return LISA_OR; + case 0x3: return LISA_XOR; + case 0x4: return LISA_ORN; + case 0x5: return LISA_ANDN; + case 0x6: return LISA_SLL_W; + case 0x7: return LISA_SRL_W; + } + break; + case 0x6: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_SRA_W; + case 0x1: return LISA_SLL_D; + case 0x2: return LISA_SRL_D; + case 0x3: return LISA_SRA_D; + case 0x6: return LISA_ROTR_W; + case 0x7: return LISA_ROTR_D; + } + break; + case 0x7: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_MUL_W; + case 0x1: return LISA_MULH_W; + case 0x2: return LISA_MULH_WU; + case 0x3: return LISA_MUL_D; + case 0x4: return LISA_MULH_D; + case 0x5: return LISA_MULH_DU; + case 0x6: return LISA_MULW_D_W; + case 0x7: return LISA_MULW_D_WU; + } + break; + case 0x8: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_DIV_W; + case 0x1: return LISA_MOD_W; + case 0x2: return LISA_DIV_WU; + case 0x3: return LISA_MOD_WU; + case 0x4: return LISA_DIV_D; + case 0x5: return LISA_MOD_D; + case 0x6: return LISA_DIV_DU; + case 0x7: return LISA_MOD_DU; + } + break; + case 0x9: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_CRC_W_B_W; + case 0x1: return LISA_CRC_W_H_W; + case 0x2: return LISA_CRC_W_W_W; + case 0x3: return LISA_CRC_W_D_W; + case 0x4: return LISA_CRCC_W_B_W; + case 0x5: return LISA_CRCC_W_H_W; + case 0x6: return LISA_CRCC_W_W_W; + case 0x7: return LISA_CRCC_W_D_W; + } + break; + case 0xa: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_BREAK; + case 0x6: return LISA_SYSCALL; + } + break; + case 0xb: + switch ((insn >> 17) & 0x1) { + case 0x0: return LISA_ALSL_D; + } + break; + case 0xc: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_ADC_B; + case 0x1: return LISA_ADC_H; + case 0x2: return LISA_ADC_W; + case 0x3: return LISA_ADC_D; + case 0x4: return LISA_SBC_B; + case 0x5: return LISA_SBC_H; + case 0x6: return LISA_SBC_W; + case 0x7: return LISA_SBC_D; + } + break; + case 0xd: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_RCR_B; + case 0x1: return LISA_RCR_H; + case 0x2: return LISA_RCR_W; + case 0x3: return LISA_RCR_D; + case 0x5: + switch (insn & 0x000043e0) { + case 0x00000000: return LISA_SETX86J; + } + break; + } + break; + case 0xf: + switch (insn & 0x0003801f) { + case 0x00028000: return LISA_X86MUL_B; + case 0x00028001: return LISA_X86MUL_H; + case 0x00028002: return LISA_X86MUL_W; + case 0x00028003: return LISA_X86MUL_D; + case 0x00028004: return LISA_X86MUL_BU; + case 0x00028005: return LISA_X86MUL_HU; + case 0x00028006: return LISA_X86MUL_WU; + case 0x00028007: return LISA_X86MUL_DU; + case 0x00030000: return LISA_X86ADD_WU; + case 0x00030001: return LISA_X86ADD_DU; + case 0x00030002: return LISA_X86SUB_WU; + case 0x00030003: return LISA_X86SUB_DU; + case 0x00030004: return LISA_X86ADD_B; + case 0x00030005: return LISA_X86ADD_H; + case 0x00030006: return LISA_X86ADD_W; + case 0x00030007: return LISA_X86ADD_D; + case 0x00030008: return LISA_X86SUB_B; + case 0x00030009: return LISA_X86SUB_H; + case 0x0003000a: return LISA_X86SUB_W; + case 0x0003000b: return LISA_X86SUB_D; + case 0x0003000c: return LISA_X86ADC_B; + case 0x0003000d: return LISA_X86ADC_H; + case 0x0003000e: return LISA_X86ADC_W; + case 0x0003000f: return LISA_X86ADC_D; + case 0x00030010: return LISA_X86SBC_B; + case 0x00030011: return LISA_X86SBC_H; + case 0x00030012: return LISA_X86SBC_W; + case 0x00030013: return LISA_X86SBC_D; + case 0x00030014: return LISA_X86SLL_B; + case 0x00030015: return LISA_X86SLL_H; + case 0x00030016: return LISA_X86SLL_W; + case 0x00030017: return LISA_X86SLL_D; + case 0x00030018: return LISA_X86SRL_B; + case 0x00030019: return LISA_X86SRL_H; + case 0x0003001a: return LISA_X86SRL_W; + case 0x0003001b: return LISA_X86SRL_D; + case 0x0003001c: return LISA_X86SRA_B; + case 0x0003001d: return LISA_X86SRA_H; + case 0x0003001e: return LISA_X86SRA_W; + case 0x0003001f: return LISA_X86SRA_D; + case 0x00038000: return LISA_X86ROTR_B; + case 0x00038001: return LISA_X86ROTR_H; + case 0x00038002: return LISA_X86ROTR_D; + case 0x00038003: return LISA_X86ROTR_W; + case 0x00038004: return LISA_X86ROTL_B; + case 0x00038005: return LISA_X86ROTL_H; + case 0x00038006: return LISA_X86ROTL_W; + case 0x00038007: return LISA_X86ROTL_D; + case 0x00038008: return LISA_X86RCR_B; + case 0x00038009: return LISA_X86RCR_H; + case 0x0003800a: return LISA_X86RCR_W; + case 0x0003800b: return LISA_X86RCR_D; + case 0x0003800c: return LISA_X86RCL_B; + case 0x0003800d: return LISA_X86RCL_H; + case 0x0003800e: return LISA_X86RCL_W; + case 0x0003800f: return LISA_X86RCL_D; + case 0x00038010: return LISA_X86AND_B; + case 0x00038011: return LISA_X86AND_H; + case 0x00038012: return LISA_X86AND_W; + case 0x00038013: return LISA_X86AND_D; + case 0x00038014: return LISA_X86OR_B; + case 0x00038015: return LISA_X86OR_H; + case 0x00038016: return LISA_X86OR_W; + case 0x00038017: return LISA_X86OR_D; + case 0x00038018: return LISA_X86XOR_B; + case 0x00038019: return LISA_X86XOR_H; + case 0x0003801a: return LISA_X86XOR_W; + case 0x0003801b: return LISA_X86XOR_D; + } + break; + } + break; + case 0x1: + switch ((insn >> 21) & 0x1) { + case 0x0: + switch ((insn >> 18) & 0x7) { + case 0x0: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x1: return LISA_SLLI_W; + } + break; + case 0x1: return LISA_SLLI_D; + } + break; + case 0x1: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x1: return LISA_SRLI_W; + } + break; + case 0x1: return LISA_SRLI_D; + } + break; + case 0x2: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x1: return LISA_SRAI_W; + } + break; + case 0x1: return LISA_SRAI_D; + } + break; + case 0x3: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_ROTRI_B; + } + break; + case 0x1: return LISA_ROTRI_H; + } + break; + case 0x1: return LISA_ROTRI_W; + } + break; + case 0x1: return LISA_ROTRI_D; + } + break; + case 0x4: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_RCRI_B; + } + break; + case 0x1: return LISA_RCRI_H; + } + break; + case 0x1: return LISA_RCRI_W; + } + break; + case 0x1: return LISA_RCRI_D; + } + break; + case 0x5: + switch (insn & 0x0003001f) { + case 0x00000000: + switch ((insn >> 13) & 0x7) { + case 0x1: return LISA_X86SLLI_B; + } + break; + case 0x00000001: + switch ((insn >> 14) & 0x3) { + case 0x1: return LISA_X86SLLI_H; + } + break; + case 0x00000002: + switch ((insn >> 15) & 0x1) { + case 0x1: return LISA_X86SLLI_W; + } + break; + case 0x00000004: + switch ((insn >> 13) & 0x7) { + case 0x1: return LISA_X86SRLI_B; + } + break; + case 0x00000005: + switch ((insn >> 14) & 0x3) { + case 0x1: return LISA_X86SRLI_H; + } + break; + case 0x00000006: + switch ((insn >> 15) & 0x1) { + case 0x1: return LISA_X86SRLI_W; + } + break; + case 0x00000008: + switch ((insn >> 13) & 0x7) { + case 0x1: return LISA_X86SRAI_B; + } + break; + case 0x00000009: + switch ((insn >> 14) & 0x3) { + case 0x1: return LISA_X86SRAI_H; + } + break; + case 0x0000000a: + switch ((insn >> 15) & 0x1) { + case 0x1: return LISA_X86SRAI_W; + } + break; + case 0x0000000c: + switch ((insn >> 13) & 0x7) { + case 0x1: return LISA_X86ROTRI_B; + } + break; + case 0x0000000d: + switch ((insn >> 14) & 0x3) { + case 0x1: return LISA_X86ROTRI_H; + } + break; + case 0x0000000e: + switch ((insn >> 15) & 0x1) { + case 0x1: return LISA_X86ROTRI_W; + } + break; + case 0x00000010: + switch ((insn >> 13) & 0x7) { + case 0x1: return LISA_X86RCRI_B; + } + break; + case 0x00000011: + switch ((insn >> 14) & 0x3) { + case 0x1: return LISA_X86RCRI_H; + } + break; + case 0x00000012: + switch ((insn >> 15) & 0x1) { + case 0x1: return LISA_X86RCRI_W; + } + break; + case 0x00000014: + switch ((insn >> 13) & 0x7) { + case 0x1: return LISA_X86ROTLI_B; + } + break; + case 0x00000015: + switch ((insn >> 14) & 0x3) { + case 0x1: return LISA_X86ROTLI_H; + } + break; + case 0x00000016: + switch ((insn >> 15) & 0x1) { + case 0x1: return LISA_X86ROTLI_W; + } + break; + case 0x00000018: + switch ((insn >> 13) & 0x7) { + case 0x1: return LISA_X86RCLI_B; + } + break; + case 0x00000019: + switch ((insn >> 14) & 0x3) { + case 0x1: return LISA_X86RCLI_H; + } + break; + case 0x0000001a: + switch ((insn >> 15) & 0x1) { + case 0x1: return LISA_X86RCLI_W; + } + break; + case 0x00010003: return LISA_X86SLLI_D; + case 0x00010007: return LISA_X86SRLI_D; + case 0x0001000b: return LISA_X86SRAI_D; + case 0x0001000f: return LISA_X86ROTRI_D; + case 0x00010013: return LISA_X86RCRI_D; + case 0x00010017: return LISA_X86ROTLI_D; + case 0x0001001b: return LISA_X86RCLI_D; + } + break; + case 0x7: + switch ((insn >> 5) & 0x1f) { + case 0x0: return LISA_X86MFFLAG; + case 0x1: return LISA_X86MTFLAG; + } + break; + } + break; + case 0x1: + switch ((insn >> 15) & 0x1) { + case 0x0: return LISA_BSTRINS_W; + case 0x1: return LISA_BSTRPICK_W; + } + break; + } + break; + case 0x2: return LISA_BSTRINS_D; + case 0x3: return LISA_BSTRPICK_D; + case 0x4: + switch ((insn >> 15) & 0x7f) { + case 0x1: return LISA_FADD_S; + case 0x2: return LISA_FADD_D; + case 0x5: return LISA_FSUB_S; + case 0x6: return LISA_FSUB_D; + case 0x9: return LISA_FMUL_S; + case 0xa: return LISA_FMUL_D; + case 0xd: return LISA_FDIV_S; + case 0xe: return LISA_FDIV_D; + case 0x11: return LISA_FMAX_S; + case 0x12: return LISA_FMAX_D; + case 0x15: return LISA_FMIN_S; + case 0x16: return LISA_FMIN_D; + case 0x19: return LISA_FMAXA_S; + case 0x1a: return LISA_FMAXA_D; + case 0x1d: return LISA_FMINA_S; + case 0x1e: return LISA_FMINA_D; + case 0x21: return LISA_FSCALEB_S; + case 0x22: return LISA_FSCALEB_D; + case 0x25: return LISA_FCOPYSIGN_S; + case 0x26: return LISA_FCOPYSIGN_D; + case 0x28: + switch ((insn >> 10) & 0x1f) { + case 0x1: return LISA_FABS_S; + case 0x2: return LISA_FABS_D; + case 0x5: return LISA_FNEG_S; + case 0x6: return LISA_FNEG_D; + case 0x9: return LISA_FLOGB_S; + case 0xa: return LISA_FLOGB_D; + case 0xd: return LISA_FCLASS_S; + case 0xe: return LISA_FCLASS_D; + case 0x11: return LISA_FSQRT_S; + case 0x12: return LISA_FSQRT_D; + case 0x15: return LISA_FRECIP_S; + case 0x16: return LISA_FRECIP_D; + case 0x19: return LISA_FRSQRT_S; + case 0x1a: return LISA_FRSQRT_D; + } + break; + case 0x29: + switch ((insn >> 10) & 0x1f) { + case 0x5: return LISA_FMOV_S; + case 0x6: return LISA_FMOV_D; + case 0x9: return LISA_MOVGR2FR_W; + case 0xa: return LISA_MOVGR2FR_D; + case 0xb: return LISA_MOVGR2FRH_W; + case 0xd: return LISA_MOVFR2GR_S; + case 0xe: return LISA_MOVFR2GR_D; + case 0xf: return LISA_MOVFRH2GR_S; + case 0x10: return LISA_MOVGR2FCSR; + case 0x12: return LISA_MOVFCSR2GR; + case 0x14: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_MOVFR2CF; + } + break; + case 0x15: + switch ((insn >> 8) & 0x3) { + case 0x0: return LISA_MOVCF2FR; + } + break; + case 0x16: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_MOVGR2CF; + } + break; + case 0x17: + switch ((insn >> 8) & 0x3) { + case 0x0: return LISA_MOVCF2GR; + } + break; + case 0x18: return LISA_FCVT_LD_D; + case 0x19: return LISA_FCVT_UD_D; + } + break; + case 0x2a: return LISA_FCVT_D_LD; + case 0x32: + switch ((insn >> 10) & 0x1f) { + case 0x6: return LISA_FCVT_S_D; + case 0x9: return LISA_FCVT_D_S; + } + break; + case 0x34: + switch ((insn >> 10) & 0x1f) { + case 0x1: return LISA_FTINTRM_W_S; + case 0x2: return LISA_FTINTRM_W_D; + case 0x9: return LISA_FTINTRM_L_S; + case 0xa: return LISA_FTINTRM_L_D; + case 0x11: return LISA_FTINTRP_W_S; + case 0x12: return LISA_FTINTRP_W_D; + case 0x19: return LISA_FTINTRP_L_S; + case 0x1a: return LISA_FTINTRP_L_D; + } + break; + case 0x35: + switch ((insn >> 10) & 0x1f) { + case 0x1: return LISA_FTINTRZ_W_S; + case 0x2: return LISA_FTINTRZ_W_D; + case 0x9: return LISA_FTINTRZ_L_S; + case 0xa: return LISA_FTINTRZ_L_D; + case 0x11: return LISA_FTINTRNE_W_S; + case 0x12: return LISA_FTINTRNE_W_D; + case 0x19: return LISA_FTINTRNE_L_S; + case 0x1a: return LISA_FTINTRNE_L_D; + } + break; + case 0x36: + switch ((insn >> 10) & 0x1f) { + case 0x1: return LISA_FTINT_W_S; + case 0x2: return LISA_FTINT_W_D; + case 0x9: return LISA_FTINT_L_S; + case 0xa: return LISA_FTINT_L_D; + } + break; + case 0x3a: + switch ((insn >> 10) & 0x1f) { + case 0x4: return LISA_FFINT_S_W; + case 0x6: return LISA_FFINT_S_L; + case 0x8: return LISA_FFINT_D_W; + case 0xa: return LISA_FFINT_D_L; + } + break; + case 0x3c: + switch ((insn >> 10) & 0x1f) { + case 0x11: return LISA_FRINT_S; + case 0x12: return LISA_FRINT_D; + } + break; + } + break; + case 0x8: return LISA_SLTI; + case 0x9: return LISA_SLTUI; + case 0xa: return LISA_ADDI_W; + case 0xb: return LISA_ADDI_D; + case 0xc: return LISA_LU52I_D; + case 0xd: return LISA_ANDI; + case 0xe: return LISA_ORI; + case 0xf: return LISA_XORI; + } + break; + case 0x2: + switch ((insn >> 20) & 0x3f) { + case 0x1: return LISA_FMADD_S; + case 0x2: return LISA_FMADD_D; + case 0x5: return LISA_FMSUB_S; + case 0x6: return LISA_FMSUB_D; + case 0x9: return LISA_FNMADD_S; + case 0xa: return LISA_FNMADD_D; + case 0xd: return LISA_FNMSUB_S; + case 0xe: return LISA_FNMSUB_D; + case 0x11: return LISA_VFMADD_S; + case 0x12: return LISA_VFMADD_D; + case 0x15: return LISA_VFMSUB_S; + case 0x16: return LISA_VFMSUB_D; + case 0x19: return LISA_VFNMADD_S; + case 0x1a: return LISA_VFNMADD_D; + case 0x1d: return LISA_VFNMSUB_S; + case 0x1e: return LISA_VFNMSUB_D; + case 0x21: return LISA_XVFMADD_S; + case 0x22: return LISA_XVFMADD_D; + case 0x25: return LISA_XVFMSUB_S; + case 0x26: return LISA_XVFMSUB_D; + case 0x29: return LISA_XVFNMADD_S; + case 0x2a: return LISA_XVFNMADD_D; + case 0x2d: return LISA_XVFNMSUB_S; + case 0x2e: return LISA_XVFNMSUB_D; + } + break; + case 0x3: + switch ((insn >> 20) & 0x3f) { + case 0x1: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_FCMP_COND_S; + } + break; + case 0x2: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_FCMP_COND_D; + } + break; + case 0x5: return LISA_VFCMP_COND_S; + case 0x6: return LISA_VFCMP_COND_D; + case 0x9: return LISA_XVFCMP_COND_S; + case 0xa: return LISA_XVFCMP_COND_D; + case 0x10: + switch ((insn >> 18) & 0x3) { + case 0x0: return LISA_FSEL; + } + break; + case 0x11: return LISA_VBITSEL_V; + case 0x12: return LISA_XVBITSEL_V; + case 0x15: return LISA_VSHUF_B; + case 0x16: return LISA_XVSHUF_B; + case 0x19: return LISA_VEXTR_V; + case 0x1a: return LISA_XVEXTR_V; + case 0x29: return LISA_VFMADDSUB_S; + case 0x2a: return LISA_VFMADDSUB_D; + case 0x2d: return LISA_VFMSUBADD_S; + case 0x2e: return LISA_VFMSUBADD_D; + case 0x31: return LISA_XVFMADDSUB_S; + case 0x32: return LISA_XVFMADDSUB_D; + case 0x35: return LISA_XVFMSUBADD_S; + case 0x36: return LISA_XVFMSUBADD_D; + } + break; + case 0x4: return LISA_ADDU16I_D; + case 0x5: + switch ((insn >> 25) & 0x1) { + case 0x0: return LISA_LU12I_W; + case 0x1: return LISA_LU32I_D; + } + break; + case 0x6: + switch ((insn >> 25) & 0x1) { + case 0x0: return LISA_PCADDI; + case 0x1: return LISA_PCALAU12I; + } + break; + case 0x7: + switch ((insn >> 25) & 0x1) { + case 0x0: return LISA_PCADDU12I; + case 0x1: return LISA_PCADDU18I; + } + break; + case 0x8: + switch ((insn >> 24) & 0x3) { + case 0x0: return LISA_LL_W; + case 0x1: return LISA_SC_W; + case 0x2: return LISA_LL_D; + case 0x3: return LISA_SC_D; + } + break; + case 0x9: + switch ((insn >> 24) & 0x3) { + case 0x0: return LISA_LDPTR_W; + case 0x1: return LISA_STPTR_W; + case 0x2: return LISA_LDPTR_D; + case 0x3: return LISA_STPTR_D; + } + break; + case 0xa: + switch ((insn >> 22) & 0xf) { + case 0x0: return LISA_LD_B; + case 0x1: return LISA_LD_H; + case 0x2: return LISA_LD_W; + case 0x3: return LISA_LD_D; + case 0x4: return LISA_ST_B; + case 0x5: return LISA_ST_H; + case 0x6: return LISA_ST_W; + case 0x7: return LISA_ST_D; + case 0x8: return LISA_LD_BU; + case 0x9: return LISA_LD_HU; + case 0xa: return LISA_LD_WU; + case 0xb: return LISA_PRELD; + case 0xc: return LISA_FLD_S; + case 0xd: return LISA_FST_S; + case 0xe: return LISA_FLD_D; + case 0xf: return LISA_FST_D; + } + break; + case 0xb: + switch ((insn >> 22) & 0xf) { + case 0x0: return LISA_VLD; + case 0x1: return LISA_VST; + case 0x2: return LISA_XVLD; + case 0x3: return LISA_XVST; + } + break; + case 0xc: + switch ((insn >> 23) & 0x7) { + case 0x0: + switch ((insn >> 21) & 0x3) { + case 0x0: + switch ((insn >> 19) & 0x3) { + case 0x2: return LISA_VLDREPL_D; + } + break; + case 0x1: + switch ((insn >> 20) & 0x1) { + case 0x0: return LISA_VLDREPL_W; + } + break; + case 0x2: return LISA_VLDREPL_H; + } + break; + case 0x1: + switch ((insn >> 22) & 0x1) { + case 0x0: return LISA_VLDREPL_B; + } + break; + case 0x2: + switch ((insn >> 21) & 0x3) { + case 0x0: + switch ((insn >> 19) & 0x3) { + case 0x2: return LISA_VSTELM_D; + } + break; + case 0x1: + switch ((insn >> 20) & 0x1) { + case 0x0: return LISA_VSTELM_W; + } + break; + case 0x2: return LISA_VSTELM_H; + } + break; + case 0x3: + switch ((insn >> 22) & 0x1) { + case 0x0: return LISA_VSTELM_B; + } + break; + case 0x4: + switch ((insn >> 21) & 0x3) { + case 0x0: + switch ((insn >> 19) & 0x3) { + case 0x2: return LISA_XVLDREPL_D; + } + break; + case 0x1: + switch ((insn >> 20) & 0x1) { + case 0x0: return LISA_XVLDREPL_W; + } + break; + case 0x2: return LISA_XVLDREPL_H; + } + break; + case 0x5: + switch ((insn >> 22) & 0x1) { + case 0x0: return LISA_XVLDREPL_B; + } + break; + case 0x6: + switch ((insn >> 22) & 0x1) { + case 0x0: + switch ((insn >> 21) & 0x1) { + case 0x0: + switch ((insn >> 20) & 0x1) { + case 0x1: return LISA_XVSTELM_D; + } + break; + case 0x1: return LISA_XVSTELM_W; + } + break; + case 0x1: return LISA_XVSTELM_H; + } + break; + case 0x7: return LISA_XVSTELM_B; + } + break; + case 0xe: + switch ((insn >> 15) & 0x7ff) { + case 0x0: return LISA_LDX_B; + case 0x8: return LISA_LDX_H; + case 0x10: return LISA_LDX_W; + case 0x18: return LISA_LDX_D; + case 0x20: return LISA_STX_B; + case 0x28: return LISA_STX_H; + case 0x30: return LISA_STX_W; + case 0x38: return LISA_STX_D; + case 0x40: return LISA_LDX_BU; + case 0x48: return LISA_LDX_HU; + case 0x50: return LISA_LDX_WU; + case 0x58: return LISA_PRELDX; + case 0x60: return LISA_FLDX_S; + case 0x68: return LISA_FLDX_D; + case 0x70: return LISA_FSTX_S; + case 0x78: return LISA_FSTX_D; + case 0x80: return LISA_VLDX; + case 0x88: return LISA_VSTX; + case 0x90: return LISA_XVLDX; + case 0x98: return LISA_XVSTX; + case 0xc0: return LISA_AMSWAP_W; + case 0xc1: return LISA_AMSWAP_D; + case 0xc2: return LISA_AMADD_W; + case 0xc3: return LISA_AMADD_D; + case 0xc4: return LISA_AMAND_W; + case 0xc5: return LISA_AMAND_D; + case 0xc6: return LISA_AMOR_W; + case 0xc7: return LISA_AMOR_D; + case 0xc8: return LISA_AMXOR_W; + case 0xc9: return LISA_AMXOR_D; + case 0xca: return LISA_AMMAX_W; + case 0xcb: return LISA_AMMAX_D; + case 0xcc: return LISA_AMMIN_W; + case 0xcd: return LISA_AMMIN_D; + case 0xce: return LISA_AMMAX_WU; + case 0xcf: return LISA_AMMAX_DU; + case 0xd0: return LISA_AMMIN_WU; + case 0xd1: return LISA_AMMIN_DU; + case 0xd2: return LISA_AMSWAP_DB_W; + case 0xd3: return LISA_AMSWAP_DB_D; + case 0xd4: return LISA_AMADD_DB_W; + case 0xd5: return LISA_AMADD_DB_D; + case 0xd6: return LISA_AMAND_DB_W; + case 0xd7: return LISA_AMAND_DB_D; + case 0xd8: return LISA_AMOR_DB_W; + case 0xd9: return LISA_AMOR_DB_D; + case 0xda: return LISA_AMXOR_DB_W; + case 0xdb: return LISA_AMXOR_DB_D; + case 0xdc: return LISA_AMMAX_DB_W; + case 0xdd: return LISA_AMMAX_DB_D; + case 0xde: return LISA_AMMIN_DB_W; + case 0xdf: return LISA_AMMIN_DB_D; + case 0xe0: return LISA_AMMAX_DB_WU; + case 0xe1: return LISA_AMMAX_DB_DU; + case 0xe2: return LISA_AMMIN_DB_WU; + case 0xe3: return LISA_AMMIN_DB_DU; + case 0xe4: return LISA_DBAR; + case 0xe5: return LISA_IBAR; + case 0xe8: return LISA_FLDGT_S; + case 0xe9: return LISA_FLDGT_D; + case 0xea: return LISA_FLDLE_S; + case 0xeb: return LISA_FLDLE_D; + case 0xec: return LISA_FSTGT_S; + case 0xed: return LISA_FSTGT_D; + case 0xee: return LISA_FSTLE_S; + case 0xef: return LISA_FSTLE_D; + case 0xf0: return LISA_LDGT_B; + case 0xf1: return LISA_LDGT_H; + case 0xf2: return LISA_LDGT_W; + case 0xf3: return LISA_LDGT_D; + case 0xf4: return LISA_LDLE_B; + case 0xf5: return LISA_LDLE_H; + case 0xf6: return LISA_LDLE_W; + case 0xf7: return LISA_LDLE_D; + case 0xf8: return LISA_STGT_B; + case 0xf9: return LISA_STGT_H; + case 0xfa: return LISA_STGT_W; + case 0xfb: return LISA_STGT_D; + case 0xfc: return LISA_STLE_B; + case 0xfd: return LISA_STLE_H; + case 0xfe: return LISA_STLE_W; + case 0xff: return LISA_STLE_D; + } + break; + case 0x10: return LISA_BEQZ; + case 0x11: return LISA_BNEZ; + case 0x12: + switch ((insn >> 8) & 0x3) { + case 0x0: return LISA_BCEQZ; + case 0x1: return LISA_BCNEZ; + } + break; + case 0x13: return LISA_JIRL; + case 0x14: return LISA_B; + case 0x15: return LISA_BL; + case 0x16: return LISA_BEQ; + case 0x17: return LISA_BNE; + case 0x18: return LISA_BLT; + case 0x19: return LISA_BGE; + case 0x1a: return LISA_BLTU; + case 0x1b: return LISA_BGEU; + case 0x1c: + switch ((insn >> 18) & 0xff) { + case 0x0: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSEQ_B; + case 0x1: return LISA_VSEQ_H; + case 0x2: return LISA_VSEQ_W; + case 0x3: return LISA_VSEQ_D; + case 0x4: return LISA_VSLE_B; + case 0x5: return LISA_VSLE_H; + case 0x6: return LISA_VSLE_W; + case 0x7: return LISA_VSLE_D; + } + break; + case 0x1: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSLE_BU; + case 0x1: return LISA_VSLE_HU; + case 0x2: return LISA_VSLE_WU; + case 0x3: return LISA_VSLE_DU; + case 0x4: return LISA_VSLT_B; + case 0x5: return LISA_VSLT_H; + case 0x6: return LISA_VSLT_W; + case 0x7: return LISA_VSLT_D; + } + break; + case 0x2: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSLT_BU; + case 0x1: return LISA_VSLT_HU; + case 0x2: return LISA_VSLT_WU; + case 0x3: return LISA_VSLT_DU; + case 0x4: return LISA_VADD_B; + case 0x5: return LISA_VADD_H; + case 0x6: return LISA_VADD_W; + case 0x7: return LISA_VADD_D; + } + break; + case 0x3: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSUB_B; + case 0x1: return LISA_VSUB_H; + case 0x2: return LISA_VSUB_W; + case 0x3: return LISA_VSUB_D; + } + break; + case 0x7: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_VADDWEV_H_B; + case 0x5: return LISA_VADDWEV_W_H; + case 0x6: return LISA_VADDWEV_D_W; + case 0x7: return LISA_VADDWEV_Q_D; + } + break; + case 0x8: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSUBWEV_H_B; + case 0x1: return LISA_VSUBWEV_W_H; + case 0x2: return LISA_VSUBWEV_D_W; + case 0x3: return LISA_VSUBWEV_Q_D; + case 0x4: return LISA_VADDWOD_H_B; + case 0x5: return LISA_VADDWOD_W_H; + case 0x6: return LISA_VADDWOD_D_W; + case 0x7: return LISA_VADDWOD_Q_D; + } + break; + case 0x9: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSUBWOD_H_B; + case 0x1: return LISA_VSUBWOD_W_H; + case 0x2: return LISA_VSUBWOD_D_W; + case 0x3: return LISA_VSUBWOD_Q_D; + } + break; + case 0xb: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_VADDWEV_H_BU; + case 0x5: return LISA_VADDWEV_W_HU; + case 0x6: return LISA_VADDWEV_D_WU; + case 0x7: return LISA_VADDWEV_Q_DU; + } + break; + case 0xc: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSUBWEV_H_BU; + case 0x1: return LISA_VSUBWEV_W_HU; + case 0x2: return LISA_VSUBWEV_D_WU; + case 0x3: return LISA_VSUBWEV_Q_DU; + case 0x4: return LISA_VADDWOD_H_BU; + case 0x5: return LISA_VADDWOD_W_HU; + case 0x6: return LISA_VADDWOD_D_WU; + case 0x7: return LISA_VADDWOD_Q_DU; + } + break; + case 0xd: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSUBWOD_H_BU; + case 0x1: return LISA_VSUBWOD_W_HU; + case 0x2: return LISA_VSUBWOD_D_WU; + case 0x3: return LISA_VSUBWOD_Q_DU; + } + break; + case 0xf: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_VADDWEV_H_BU_B; + case 0x5: return LISA_VADDWEV_W_HU_H; + case 0x6: return LISA_VADDWEV_D_WU_W; + case 0x7: return LISA_VADDWEV_Q_DU_D; + } + break; + case 0x10: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VADDWOD_H_BU_B; + case 0x1: return LISA_VADDWOD_W_HU_H; + case 0x2: return LISA_VADDWOD_D_WU_W; + case 0x3: return LISA_VADDWOD_Q_DU_D; + } + break; + case 0x11: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_VSADD_B; + case 0x5: return LISA_VSADD_H; + case 0x6: return LISA_VSADD_W; + case 0x7: return LISA_VSADD_D; + } + break; + case 0x12: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSSUB_B; + case 0x1: return LISA_VSSUB_H; + case 0x2: return LISA_VSSUB_W; + case 0x3: return LISA_VSSUB_D; + case 0x4: return LISA_VSADD_BU; + case 0x5: return LISA_VSADD_HU; + case 0x6: return LISA_VSADD_WU; + case 0x7: return LISA_VSADD_DU; + } + break; + case 0x13: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSSUB_BU; + case 0x1: return LISA_VSSUB_HU; + case 0x2: return LISA_VSSUB_WU; + case 0x3: return LISA_VSSUB_DU; + } + break; + case 0x15: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VHADDW_H_B; + case 0x1: return LISA_VHADDW_W_H; + case 0x2: return LISA_VHADDW_D_W; + case 0x3: return LISA_VHADDW_Q_D; + case 0x4: return LISA_VHSUBW_H_B; + case 0x5: return LISA_VHSUBW_W_H; + case 0x6: return LISA_VHSUBW_D_W; + case 0x7: return LISA_VHSUBW_Q_D; + } + break; + case 0x16: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VHADDW_HU_BU; + case 0x1: return LISA_VHADDW_WU_HU; + case 0x2: return LISA_VHADDW_DU_WU; + case 0x3: return LISA_VHADDW_QU_DU; + case 0x4: return LISA_VHSUBW_HU_BU; + case 0x5: return LISA_VHSUBW_WU_HU; + case 0x6: return LISA_VHSUBW_DU_WU; + case 0x7: return LISA_VHSUBW_QU_DU; + } + break; + case 0x17: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VADDA_B; + case 0x1: return LISA_VADDA_H; + case 0x2: return LISA_VADDA_W; + case 0x3: return LISA_VADDA_D; + } + break; + case 0x18: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VABSD_B; + case 0x1: return LISA_VABSD_H; + case 0x2: return LISA_VABSD_W; + case 0x3: return LISA_VABSD_D; + case 0x4: return LISA_VABSD_BU; + case 0x5: return LISA_VABSD_HU; + case 0x6: return LISA_VABSD_WU; + case 0x7: return LISA_VABSD_DU; + } + break; + case 0x19: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VAVG_B; + case 0x1: return LISA_VAVG_H; + case 0x2: return LISA_VAVG_W; + case 0x3: return LISA_VAVG_D; + case 0x4: return LISA_VAVG_BU; + case 0x5: return LISA_VAVG_HU; + case 0x6: return LISA_VAVG_WU; + case 0x7: return LISA_VAVG_DU; + } + break; + case 0x1a: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VAVGR_B; + case 0x1: return LISA_VAVGR_H; + case 0x2: return LISA_VAVGR_W; + case 0x3: return LISA_VAVGR_D; + case 0x4: return LISA_VAVGR_BU; + case 0x5: return LISA_VAVGR_HU; + case 0x6: return LISA_VAVGR_WU; + case 0x7: return LISA_VAVGR_DU; + } + break; + case 0x1c: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMAX_B; + case 0x1: return LISA_VMAX_H; + case 0x2: return LISA_VMAX_W; + case 0x3: return LISA_VMAX_D; + case 0x4: return LISA_VMIN_B; + case 0x5: return LISA_VMIN_H; + case 0x6: return LISA_VMIN_W; + case 0x7: return LISA_VMIN_D; + } + break; + case 0x1d: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMAX_BU; + case 0x1: return LISA_VMAX_HU; + case 0x2: return LISA_VMAX_WU; + case 0x3: return LISA_VMAX_DU; + case 0x4: return LISA_VMIN_BU; + case 0x5: return LISA_VMIN_HU; + case 0x6: return LISA_VMIN_WU; + case 0x7: return LISA_VMIN_DU; + } + break; + case 0x21: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMUL_B; + case 0x1: return LISA_VMUL_H; + case 0x2: return LISA_VMUL_W; + case 0x3: return LISA_VMUL_D; + case 0x4: return LISA_VMUH_B; + case 0x5: return LISA_VMUH_H; + case 0x6: return LISA_VMUH_W; + case 0x7: return LISA_VMUH_D; + } + break; + case 0x22: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMUH_BU; + case 0x1: return LISA_VMUH_HU; + case 0x2: return LISA_VMUH_WU; + case 0x3: return LISA_VMUH_DU; + } + break; + case 0x24: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMULWEV_H_B; + case 0x1: return LISA_VMULWEV_W_H; + case 0x2: return LISA_VMULWEV_D_W; + case 0x3: return LISA_VMULWEV_Q_D; + case 0x4: return LISA_VMULWOD_H_B; + case 0x5: return LISA_VMULWOD_W_H; + case 0x6: return LISA_VMULWOD_D_W; + case 0x7: return LISA_VMULWOD_Q_D; + } + break; + case 0x26: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMULWEV_H_BU; + case 0x1: return LISA_VMULWEV_W_HU; + case 0x2: return LISA_VMULWEV_D_WU; + case 0x3: return LISA_VMULWEV_Q_DU; + case 0x4: return LISA_VMULWOD_H_BU; + case 0x5: return LISA_VMULWOD_W_HU; + case 0x6: return LISA_VMULWOD_D_WU; + case 0x7: return LISA_VMULWOD_Q_DU; + } + break; + case 0x28: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMULWEV_H_BU_B; + case 0x1: return LISA_VMULWEV_W_HU_H; + case 0x2: return LISA_VMULWEV_D_WU_W; + case 0x3: return LISA_VMULWEV_Q_DU_D; + case 0x4: return LISA_VMULWOD_H_BU_B; + case 0x5: return LISA_VMULWOD_W_HU_H; + case 0x6: return LISA_VMULWOD_D_WU_W; + case 0x7: return LISA_VMULWOD_Q_DU_D; + } + break; + case 0x2a: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMADD_B; + case 0x1: return LISA_VMADD_H; + case 0x2: return LISA_VMADD_W; + case 0x3: return LISA_VMADD_D; + case 0x4: return LISA_VMSUB_B; + case 0x5: return LISA_VMSUB_H; + case 0x6: return LISA_VMSUB_W; + case 0x7: return LISA_VMSUB_D; + } + break; + case 0x2b: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMADDWEV_H_B; + case 0x1: return LISA_VMADDWEV_W_H; + case 0x2: return LISA_VMADDWEV_D_W; + case 0x3: return LISA_VMADDWEV_Q_D; + case 0x4: return LISA_VMADDWOD_H_B; + case 0x5: return LISA_VMADDWOD_W_H; + case 0x6: return LISA_VMADDWOD_D_W; + case 0x7: return LISA_VMADDWOD_Q_D; + } + break; + case 0x2d: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMADDWEV_H_BU; + case 0x1: return LISA_VMADDWEV_W_HU; + case 0x2: return LISA_VMADDWEV_D_WU; + case 0x3: return LISA_VMADDWEV_Q_DU; + case 0x4: return LISA_VMADDWOD_H_BU; + case 0x5: return LISA_VMADDWOD_W_HU; + case 0x6: return LISA_VMADDWOD_D_WU; + case 0x7: return LISA_VMADDWOD_Q_DU; + } + break; + case 0x2f: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMADDWEV_H_BU_B; + case 0x1: return LISA_VMADDWEV_W_HU_H; + case 0x2: return LISA_VMADDWEV_D_WU_W; + case 0x3: return LISA_VMADDWEV_Q_DU_D; + case 0x4: return LISA_VMADDWOD_H_BU_B; + case 0x5: return LISA_VMADDWOD_W_HU_H; + case 0x6: return LISA_VMADDWOD_D_WU_W; + case 0x7: return LISA_VMADDWOD_Q_DU_D; + } + break; + case 0x38: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VDIV_B; + case 0x1: return LISA_VDIV_H; + case 0x2: return LISA_VDIV_W; + case 0x3: return LISA_VDIV_D; + case 0x4: return LISA_VMOD_B; + case 0x5: return LISA_VMOD_H; + case 0x6: return LISA_VMOD_W; + case 0x7: return LISA_VMOD_D; + } + break; + case 0x39: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VDIV_BU; + case 0x1: return LISA_VDIV_HU; + case 0x2: return LISA_VDIV_WU; + case 0x3: return LISA_VDIV_DU; + case 0x4: return LISA_VMOD_BU; + case 0x5: return LISA_VMOD_HU; + case 0x6: return LISA_VMOD_WU; + case 0x7: return LISA_VMOD_DU; + } + break; + case 0x3a: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSLL_B; + case 0x1: return LISA_VSLL_H; + case 0x2: return LISA_VSLL_W; + case 0x3: return LISA_VSLL_D; + case 0x4: return LISA_VSRL_B; + case 0x5: return LISA_VSRL_H; + case 0x6: return LISA_VSRL_W; + case 0x7: return LISA_VSRL_D; + } + break; + case 0x3b: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSRA_B; + case 0x1: return LISA_VSRA_H; + case 0x2: return LISA_VSRA_W; + case 0x3: return LISA_VSRA_D; + case 0x4: return LISA_VROTR_B; + case 0x5: return LISA_VROTR_H; + case 0x6: return LISA_VROTR_W; + case 0x7: return LISA_VROTR_D; + } + break; + case 0x3c: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSRLR_B; + case 0x1: return LISA_VSRLR_H; + case 0x2: return LISA_VSRLR_W; + case 0x3: return LISA_VSRLR_D; + case 0x4: return LISA_VSRAR_B; + case 0x5: return LISA_VSRAR_H; + case 0x6: return LISA_VSRAR_W; + case 0x7: return LISA_VSRAR_D; + } + break; + case 0x3d: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_VSRLN_B_H; + case 0x2: return LISA_VSRLN_H_W; + case 0x3: return LISA_VSRLN_W_D; + case 0x5: return LISA_VSRAN_B_H; + case 0x6: return LISA_VSRAN_H_W; + case 0x7: return LISA_VSRAN_W_D; + } + break; + case 0x3e: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_VSRLRN_B_H; + case 0x2: return LISA_VSRLRN_H_W; + case 0x3: return LISA_VSRLRN_W_D; + case 0x5: return LISA_VSRARN_B_H; + case 0x6: return LISA_VSRARN_H_W; + case 0x7: return LISA_VSRARN_W_D; + } + break; + case 0x3f: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_VSSRLN_B_H; + case 0x2: return LISA_VSSRLN_H_W; + case 0x3: return LISA_VSSRLN_W_D; + case 0x5: return LISA_VSSRAN_B_H; + case 0x6: return LISA_VSSRAN_H_W; + case 0x7: return LISA_VSSRAN_W_D; + } + break; + case 0x40: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_VSSRLRN_B_H; + case 0x2: return LISA_VSSRLRN_H_W; + case 0x3: return LISA_VSSRLRN_W_D; + case 0x5: return LISA_VSSRARN_B_H; + case 0x6: return LISA_VSSRARN_H_W; + case 0x7: return LISA_VSSRARN_W_D; + } + break; + case 0x41: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_VSSRLN_BU_H; + case 0x2: return LISA_VSSRLN_HU_W; + case 0x3: return LISA_VSSRLN_WU_D; + case 0x5: return LISA_VSSRAN_BU_H; + case 0x6: return LISA_VSSRAN_HU_W; + case 0x7: return LISA_VSSRAN_WU_D; + } + break; + case 0x42: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_VSSRLRN_BU_H; + case 0x2: return LISA_VSSRLRN_HU_W; + case 0x3: return LISA_VSSRLRN_WU_D; + case 0x5: return LISA_VSSRARN_BU_H; + case 0x6: return LISA_VSSRARN_HU_W; + case 0x7: return LISA_VSSRARN_WU_D; + } + break; + case 0x43: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VBITCLR_B; + case 0x1: return LISA_VBITCLR_H; + case 0x2: return LISA_VBITCLR_W; + case 0x3: return LISA_VBITCLR_D; + case 0x4: return LISA_VBITSET_B; + case 0x5: return LISA_VBITSET_H; + case 0x6: return LISA_VBITSET_W; + case 0x7: return LISA_VBITSET_D; + } + break; + case 0x44: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VBITREV_B; + case 0x1: return LISA_VBITREV_H; + case 0x2: return LISA_VBITREV_W; + case 0x3: return LISA_VBITREV_D; + } + break; + case 0x45: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_VPACKEV_B; + case 0x5: return LISA_VPACKEV_H; + case 0x6: return LISA_VPACKEV_W; + case 0x7: return LISA_VPACKEV_D; + } + break; + case 0x46: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VPACKOD_B; + case 0x1: return LISA_VPACKOD_H; + case 0x2: return LISA_VPACKOD_W; + case 0x3: return LISA_VPACKOD_D; + case 0x4: return LISA_VILVL_B; + case 0x5: return LISA_VILVL_H; + case 0x6: return LISA_VILVL_W; + case 0x7: return LISA_VILVL_D; + } + break; + case 0x47: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VILVH_B; + case 0x1: return LISA_VILVH_H; + case 0x2: return LISA_VILVH_W; + case 0x3: return LISA_VILVH_D; + case 0x4: return LISA_VPICKEV_B; + case 0x5: return LISA_VPICKEV_H; + case 0x6: return LISA_VPICKEV_W; + case 0x7: return LISA_VPICKEV_D; + } + break; + case 0x48: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VPICKOD_B; + case 0x1: return LISA_VPICKOD_H; + case 0x2: return LISA_VPICKOD_W; + case 0x3: return LISA_VPICKOD_D; + case 0x4: return LISA_VREPLVE_B; + case 0x5: return LISA_VREPLVE_H; + case 0x6: return LISA_VREPLVE_W; + case 0x7: return LISA_VREPLVE_D; + } + break; + case 0x49: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_VAND_V; + case 0x5: return LISA_VOR_V; + case 0x6: return LISA_VXOR_V; + case 0x7: return LISA_VNOR_V; + } + break; + case 0x4a: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VANDN_V; + case 0x1: return LISA_VORN_V; + case 0x6: return LISA_VFRSTP_B; + case 0x7: return LISA_VFRSTP_H; + } + break; + case 0x4b: + switch ((insn >> 15) & 0x7) { + case 0x2: return LISA_VADD_Q; + case 0x3: return LISA_VSUB_Q; + case 0x4: return LISA_VSIGNCOV_B; + case 0x5: return LISA_VSIGNCOV_H; + case 0x6: return LISA_VSIGNCOV_W; + case 0x7: return LISA_VSIGNCOV_D; + } + break; + case 0x4c: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_VFADD_S; + case 0x2: return LISA_VFADD_D; + case 0x5: return LISA_VFSUB_S; + case 0x6: return LISA_VFSUB_D; + } + break; + case 0x4e: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_VFMUL_S; + case 0x2: return LISA_VFMUL_D; + case 0x5: return LISA_VFDIV_S; + case 0x6: return LISA_VFDIV_D; + } + break; + case 0x4f: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_VFMAX_S; + case 0x2: return LISA_VFMAX_D; + case 0x5: return LISA_VFMIN_S; + case 0x6: return LISA_VFMIN_D; + } + break; + case 0x50: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_VFMAXA_S; + case 0x2: return LISA_VFMAXA_D; + case 0x5: return LISA_VFMINA_S; + case 0x6: return LISA_VFMINA_D; + } + break; + case 0x51: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_VFSCALEB_S; + case 0x2: return LISA_VFSCALEB_D; + case 0x4: return LISA_VFCVT_H_S; + case 0x5: return LISA_VFCVT_S_D; + } + break; + case 0x52: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VFFINT_S_L; + case 0x3: return LISA_VFTINT_W_D; + case 0x4: return LISA_VFTINTRM_W_D; + case 0x5: return LISA_VFTINTRP_W_D; + case 0x6: return LISA_VFTINTRZ_W_D; + case 0x7: return LISA_VFTINTRNE_W_D; + } + break; + case 0x5e: + switch ((insn >> 15) & 0x7) { + case 0x5: return LISA_VSHUF_H; + case 0x6: return LISA_VSHUF_W; + case 0x7: return LISA_VSHUF_D; + } + break; + case 0xa0: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSEQI_B; + case 0x1: return LISA_VSEQI_H; + case 0x2: return LISA_VSEQI_W; + case 0x3: return LISA_VSEQI_D; + case 0x4: return LISA_VSLEI_B; + case 0x5: return LISA_VSLEI_H; + case 0x6: return LISA_VSLEI_W; + case 0x7: return LISA_VSLEI_D; + } + break; + case 0xa1: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSLEI_BU; + case 0x1: return LISA_VSLEI_HU; + case 0x2: return LISA_VSLEI_WU; + case 0x3: return LISA_VSLEI_DU; + case 0x4: return LISA_VSLTI_B; + case 0x5: return LISA_VSLTI_H; + case 0x6: return LISA_VSLTI_W; + case 0x7: return LISA_VSLTI_D; + } + break; + case 0xa2: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSLTI_BU; + case 0x1: return LISA_VSLTI_HU; + case 0x2: return LISA_VSLTI_WU; + case 0x3: return LISA_VSLTI_DU; + case 0x4: return LISA_VADDI_BU; + case 0x5: return LISA_VADDI_HU; + case 0x6: return LISA_VADDI_WU; + case 0x7: return LISA_VADDI_DU; + } + break; + case 0xa3: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VSUBI_BU; + case 0x1: return LISA_VSUBI_HU; + case 0x2: return LISA_VSUBI_WU; + case 0x3: return LISA_VSUBI_DU; + case 0x4: return LISA_VBSLL_V; + case 0x5: return LISA_VBSRL_V; + } + break; + case 0xa4: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMAXI_B; + case 0x1: return LISA_VMAXI_H; + case 0x2: return LISA_VMAXI_W; + case 0x3: return LISA_VMAXI_D; + case 0x4: return LISA_VMINI_B; + case 0x5: return LISA_VMINI_H; + case 0x6: return LISA_VMINI_W; + case 0x7: return LISA_VMINI_D; + } + break; + case 0xa5: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_VMAXI_BU; + case 0x1: return LISA_VMAXI_HU; + case 0x2: return LISA_VMAXI_WU; + case 0x3: return LISA_VMAXI_DU; + case 0x4: return LISA_VMINI_BU; + case 0x5: return LISA_VMINI_HU; + case 0x6: return LISA_VMINI_WU; + case 0x7: return LISA_VMINI_DU; + } + break; + case 0xa6: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_VFRSTPI_B; + case 0x5: return LISA_VFRSTPI_H; + case 0x6: return LISA_VCLRSTRI_V; + case 0x7: return LISA_VMEPATMSK_V; + } + break; + case 0xa7: + switch ((insn >> 10) & 0xff) { + case 0x0: return LISA_VCLO_B; + case 0x1: return LISA_VCLO_H; + case 0x2: return LISA_VCLO_W; + case 0x3: return LISA_VCLO_D; + case 0x4: return LISA_VCLZ_B; + case 0x5: return LISA_VCLZ_H; + case 0x6: return LISA_VCLZ_W; + case 0x7: return LISA_VCLZ_D; + case 0x8: return LISA_VPCNT_B; + case 0x9: return LISA_VPCNT_H; + case 0xa: return LISA_VPCNT_W; + case 0xb: return LISA_VPCNT_D; + case 0xc: return LISA_VNEG_B; + case 0xd: return LISA_VNEG_H; + case 0xe: return LISA_VNEG_W; + case 0xf: return LISA_VNEG_D; + case 0x10: return LISA_VMSKLTZ_B; + case 0x11: return LISA_VMSKLTZ_H; + case 0x12: return LISA_VMSKLTZ_W; + case 0x13: return LISA_VMSKLTZ_D; + case 0x14: return LISA_VMSKGEZ_B; + case 0x18: return LISA_VMSKNZ_B; + case 0x1c: return LISA_VMSKCOPY_B; + case 0x20: return LISA_VMSKFILL_B; + case 0x24: return LISA_VFRSTM_B; + case 0x25: return LISA_VFRSTM_H; + case 0x26: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_VSETEQZ_V; + } + break; + case 0x27: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_VSETNEZ_V; + } + break; + case 0x28: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_VSETANYEQZ_B; + } + break; + case 0x29: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_VSETANYEQZ_H; + } + break; + case 0x2a: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_VSETANYEQZ_W; + } + break; + case 0x2b: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_VSETANYEQZ_D; + } + break; + case 0x2c: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_VSETALLNEZ_B; + } + break; + case 0x2d: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_VSETALLNEZ_H; + } + break; + case 0x2e: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_VSETALLNEZ_W; + } + break; + case 0x2f: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_VSETALLNEZ_D; + } + break; + case 0x31: return LISA_VFLOGB_S; + case 0x32: return LISA_VFLOGB_D; + case 0x35: return LISA_VFCLASS_S; + case 0x36: return LISA_VFCLASS_D; + case 0x39: return LISA_VFSQRT_S; + case 0x3a: return LISA_VFSQRT_D; + case 0x3d: return LISA_VFRECIP_S; + case 0x3e: return LISA_VFRECIP_D; + case 0x41: return LISA_VFRSQRT_S; + case 0x42: return LISA_VFRSQRT_D; + case 0x4d: return LISA_VFRINT_S; + case 0x4e: return LISA_VFRINT_D; + case 0x51: return LISA_VFRINTRM_S; + case 0x52: return LISA_VFRINTRM_D; + case 0x55: return LISA_VFRINTRP_S; + case 0x56: return LISA_VFRINTRP_D; + case 0x59: return LISA_VFRINTRZ_S; + case 0x5a: return LISA_VFRINTRZ_D; + case 0x5d: return LISA_VFRINTRNE_S; + case 0x5e: return LISA_VFRINTRNE_D; + case 0x61: return LISA_VEXTL_W_B; + case 0x62: return LISA_VEXTL_D_B; + case 0x65: return LISA_VEXTL_D_H; + case 0x6b: return LISA_VEXTL_W_BU; + case 0x6c: return LISA_VEXTL_D_BU; + case 0x6f: return LISA_VEXTL_D_HU; + case 0x74: return LISA_VHADD8_D_BU; + case 0x75: return LISA_VHMINPOS_W_HU; + case 0x76: return LISA_VHMINPOS_D_HU; + case 0x77: return LISA_VHMINPOS_Q_HU; + case 0x78: return LISA_VCLRTAIL_B; + case 0x79: return LISA_VCLRTAIL_H; + case 0x7a: return LISA_VFCVTL_S_H; + case 0x7b: return LISA_VFCVTH_S_H; + case 0x7c: return LISA_VFCVTL_D_S; + case 0x7d: return LISA_VFCVTH_D_S; + case 0x80: return LISA_VFFINT_S_W; + case 0x81: return LISA_VFFINT_S_WU; + case 0x82: return LISA_VFFINT_D_L; + case 0x83: return LISA_VFFINT_D_LU; + case 0x84: return LISA_VFFINTL_D_W; + case 0x85: return LISA_VFFINTH_D_W; + case 0x8c: return LISA_VFTINT_W_S; + case 0x8d: return LISA_VFTINT_L_D; + case 0x8e: return LISA_VFTINTRM_W_S; + case 0x8f: return LISA_VFTINTRM_L_D; + case 0x90: return LISA_VFTINTRP_W_S; + case 0x91: return LISA_VFTINTRP_L_D; + case 0x92: return LISA_VFTINTRZ_W_S; + case 0x93: return LISA_VFTINTRZ_L_D; + case 0x94: return LISA_VFTINTRNE_W_S; + case 0x95: return LISA_VFTINTRNE_L_D; + case 0x96: return LISA_VFTINT_WU_S; + case 0x97: return LISA_VFTINT_LU_D; + case 0x9c: return LISA_VFTINTRZ_WU_S; + case 0x9d: return LISA_VFTINTRZ_LU_D; + case 0xa0: return LISA_VFTINTL_L_S; + case 0xa1: return LISA_VFTINTH_L_S; + case 0xa2: return LISA_VFTINTRML_L_S; + case 0xa3: return LISA_VFTINTRMH_L_S; + case 0xa4: return LISA_VFTINTRPL_L_S; + case 0xa5: return LISA_VFTINTRPH_L_S; + case 0xa6: return LISA_VFTINTRZL_L_S; + case 0xa7: return LISA_VFTINTRZH_L_S; + case 0xa8: return LISA_VFTINTRNEL_L_S; + case 0xa9: return LISA_VFTINTRNEH_L_S; + case 0xb8: return LISA_VEXTH_H_B; + case 0xb9: return LISA_VEXTH_W_H; + case 0xba: return LISA_VEXTH_D_W; + case 0xbb: return LISA_VEXTH_Q_D; + case 0xbc: return LISA_VEXTH_HU_BU; + case 0xbd: return LISA_VEXTH_WU_HU; + case 0xbe: return LISA_VEXTH_DU_WU; + case 0xbf: return LISA_VEXTH_QU_DU; + case 0xc0: return LISA_VREPLGR2VR_B; + case 0xc1: return LISA_VREPLGR2VR_H; + case 0xc2: return LISA_VREPLGR2VR_W; + case 0xc3: return LISA_VREPLGR2VR_D; + } + break; + case 0xa8: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VROTRI_B; + } + break; + case 0x1: return LISA_VROTRI_H; + } + break; + case 0x1: return LISA_VROTRI_W; + } + break; + case 0x1: return LISA_VROTRI_D; + } + break; + case 0xa9: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VSRLRI_B; + } + break; + case 0x1: return LISA_VSRLRI_H; + } + break; + case 0x1: return LISA_VSRLRI_W; + } + break; + case 0x1: return LISA_VSRLRI_D; + } + break; + case 0xaa: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VSRARI_B; + } + break; + case 0x1: return LISA_VSRARI_H; + } + break; + case 0x1: return LISA_VSRARI_W; + } + break; + case 0x1: return LISA_VSRARI_D; + } + break; + case 0xba: + switch ((insn >> 14) & 0xf) { + case 0xe: return LISA_VINSGR2VR_B; + case 0xf: + switch ((insn >> 13) & 0x1) { + case 0x0: return LISA_VINSGR2VR_H; + case 0x1: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_VINSGR2VR_W; + case 0x1: + switch ((insn >> 11) & 0x1) { + case 0x0: return LISA_VINSGR2VR_D; + } + break; + } + break; + } + break; + } + break; + case 0xbb: + switch ((insn >> 14) & 0xf) { + case 0xe: return LISA_VPICKVE2GR_B; + case 0xf: + switch ((insn >> 13) & 0x1) { + case 0x0: return LISA_VPICKVE2GR_H; + case 0x1: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_VPICKVE2GR_W; + case 0x1: + switch ((insn >> 11) & 0x1) { + case 0x0: return LISA_VPICKVE2GR_D; + } + break; + } + break; + } + break; + } + break; + case 0xbc: + switch ((insn >> 14) & 0xf) { + case 0xe: return LISA_VPICKVE2GR_BU; + case 0xf: + switch ((insn >> 13) & 0x1) { + case 0x0: return LISA_VPICKVE2GR_HU; + case 0x1: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_VPICKVE2GR_WU; + case 0x1: + switch ((insn >> 11) & 0x1) { + case 0x0: return LISA_VPICKVE2GR_DU; + } + break; + } + break; + } + break; + } + break; + case 0xbd: + switch ((insn >> 14) & 0xf) { + case 0xe: return LISA_VREPLVEI_B; + case 0xf: + switch ((insn >> 13) & 0x1) { + case 0x0: return LISA_VREPLVEI_H; + case 0x1: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_VREPLVEI_W; + case 0x1: + switch ((insn >> 11) & 0x1) { + case 0x0: return LISA_VREPLVEI_D; + } + break; + } + break; + } + break; + } + break; + case 0xbe: + switch ((insn >> 14) & 0xf) { + case 0xe: return LISA_VEXTRCOLI_B; + case 0xf: + switch ((insn >> 13) & 0x1) { + case 0x0: return LISA_VEXTRCOLI_H; + case 0x1: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_VEXTRCOLI_W; + case 0x1: + switch ((insn >> 11) & 0x1) { + case 0x0: return LISA_VEXTRCOLI_D; + } + break; + } + break; + } + break; + } + break; + case 0xc2: + switch ((insn >> 15) & 0x7) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VSLLWIL_H_B; + } + break; + case 0x1: return LISA_VSLLWIL_W_H; + } + break; + case 0x1: return LISA_VSLLWIL_D_W; + case 0x2: + switch ((insn >> 10) & 0x1f) { + case 0x0: return LISA_VEXTL_Q_D; + } + break; + } + break; + case 0xc3: + switch ((insn >> 15) & 0x7) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VSLLWIL_HU_BU; + } + break; + case 0x1: return LISA_VSLLWIL_WU_HU; + } + break; + case 0x1: return LISA_VSLLWIL_DU_WU; + case 0x2: + switch ((insn >> 10) & 0x1f) { + case 0x0: return LISA_VEXTL_QU_DU; + } + break; + } + break; + case 0xc4: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VBITCLRI_B; + } + break; + case 0x1: return LISA_VBITCLRI_H; + } + break; + case 0x1: return LISA_VBITCLRI_W; + } + break; + case 0x1: return LISA_VBITCLRI_D; + } + break; + case 0xc5: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VBITSETI_B; + } + break; + case 0x1: return LISA_VBITSETI_H; + } + break; + case 0x1: return LISA_VBITSETI_W; + } + break; + case 0x1: return LISA_VBITSETI_D; + } + break; + case 0xc6: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VBITREVI_B; + } + break; + case 0x1: return LISA_VBITREVI_H; + } + break; + case 0x1: return LISA_VBITREVI_W; + } + break; + case 0x1: return LISA_VBITREVI_D; + } + break; + case 0xc7: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VBSTRC12I_B; + } + break; + case 0x1: return LISA_VBSTRC12I_H; + } + break; + case 0x1: return LISA_VBSTRC12I_W; + } + break; + case 0x1: return LISA_VBSTRC12I_D; + } + break; + case 0xc8: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VBSTRC21I_B; + } + break; + case 0x1: return LISA_VBSTRC21I_H; + } + break; + case 0x1: return LISA_VBSTRC21I_W; + } + break; + case 0x1: return LISA_VBSTRC21I_D; + } + break; + case 0xc9: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VSAT_B; + } + break; + case 0x1: return LISA_VSAT_H; + } + break; + case 0x1: return LISA_VSAT_W; + } + break; + case 0x1: return LISA_VSAT_D; + } + break; + case 0xca: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VSAT_BU; + } + break; + case 0x1: return LISA_VSAT_HU; + } + break; + case 0x1: return LISA_VSAT_WU; + } + break; + case 0x1: return LISA_VSAT_DU; + } + break; + case 0xcb: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VSLLI_B; + } + break; + case 0x1: return LISA_VSLLI_H; + } + break; + case 0x1: return LISA_VSLLI_W; + } + break; + case 0x1: return LISA_VSLLI_D; + } + break; + case 0xcc: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VSRLI_B; + } + break; + case 0x1: return LISA_VSRLI_H; + } + break; + case 0x1: return LISA_VSRLI_W; + } + break; + case 0x1: return LISA_VSRLI_D; + } + break; + case 0xcd: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_VSRAI_B; + } + break; + case 0x1: return LISA_VSRAI_H; + } + break; + case 0x1: return LISA_VSRAI_W; + } + break; + case 0x1: return LISA_VSRAI_D; + } + break; + case 0xce: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSRLRNENI_B_H; + } + break; + case 0x1: return LISA_VSRLRNENI_H_W; + } + break; + case 0x1: return LISA_VSRLRNENI_W_D; + } + break; + case 0x1: return LISA_VSRLRNENI_D_Q; + } + break; + case 0xcf: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSRARNENI_B_H; + } + break; + case 0x1: return LISA_VSRARNENI_H_W; + } + break; + case 0x1: return LISA_VSRARNENI_W_D; + } + break; + case 0x1: return LISA_VSRARNENI_D_Q; + } + break; + case 0xd0: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSRLNI_B_H; + } + break; + case 0x1: return LISA_VSRLNI_H_W; + } + break; + case 0x1: return LISA_VSRLNI_W_D; + } + break; + case 0x1: return LISA_VSRLNI_D_Q; + } + break; + case 0xd1: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSRLRNI_B_H; + } + break; + case 0x1: return LISA_VSRLRNI_H_W; + } + break; + case 0x1: return LISA_VSRLRNI_W_D; + } + break; + case 0x1: return LISA_VSRLRNI_D_Q; + } + break; + case 0xd2: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRLNI_B_H; + } + break; + case 0x1: return LISA_VSSRLNI_H_W; + } + break; + case 0x1: return LISA_VSSRLNI_W_D; + } + break; + case 0x1: return LISA_VSSRLNI_D_Q; + } + break; + case 0xd3: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRLNI_BU_H; + } + break; + case 0x1: return LISA_VSSRLNI_HU_W; + } + break; + case 0x1: return LISA_VSSRLNI_WU_D; + } + break; + case 0x1: return LISA_VSSRLNI_DU_Q; + } + break; + case 0xd4: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRLRNI_B_H; + } + break; + case 0x1: return LISA_VSSRLRNI_H_W; + } + break; + case 0x1: return LISA_VSSRLRNI_W_D; + } + break; + case 0x1: return LISA_VSSRLRNI_D_Q; + } + break; + case 0xd5: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRLRNI_BU_H; + } + break; + case 0x1: return LISA_VSSRLRNI_HU_W; + } + break; + case 0x1: return LISA_VSSRLRNI_WU_D; + } + break; + case 0x1: return LISA_VSSRLRNI_DU_Q; + } + break; + case 0xd6: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSRANI_B_H; + } + break; + case 0x1: return LISA_VSRANI_H_W; + } + break; + case 0x1: return LISA_VSRANI_W_D; + } + break; + case 0x1: return LISA_VSRANI_D_Q; + } + break; + case 0xd7: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSRARNI_B_H; + } + break; + case 0x1: return LISA_VSRARNI_H_W; + } + break; + case 0x1: return LISA_VSRARNI_W_D; + } + break; + case 0x1: return LISA_VSRARNI_D_Q; + } + break; + case 0xd8: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRANI_B_H; + } + break; + case 0x1: return LISA_VSSRANI_H_W; + } + break; + case 0x1: return LISA_VSSRANI_W_D; + } + break; + case 0x1: return LISA_VSSRANI_D_Q; + } + break; + case 0xd9: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRANI_BU_H; + } + break; + case 0x1: return LISA_VSSRANI_HU_W; + } + break; + case 0x1: return LISA_VSSRANI_WU_D; + } + break; + case 0x1: return LISA_VSSRANI_DU_Q; + } + break; + case 0xda: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRARNI_B_H; + } + break; + case 0x1: return LISA_VSSRARNI_H_W; + } + break; + case 0x1: return LISA_VSSRARNI_W_D; + } + break; + case 0x1: return LISA_VSSRARNI_D_Q; + } + break; + case 0xdb: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRARNI_BU_H; + } + break; + case 0x1: return LISA_VSSRARNI_HU_W; + } + break; + case 0x1: return LISA_VSSRARNI_WU_D; + } + break; + case 0x1: return LISA_VSSRARNI_DU_Q; + } + break; + case 0xdc: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRLRNENI_B_H; + } + break; + case 0x1: return LISA_VSSRLRNENI_H_W; + } + break; + case 0x1: return LISA_VSSRLRNENI_W_D; + } + break; + case 0x1: return LISA_VSSRLRNENI_D_Q; + } + break; + case 0xdd: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRLRNENI_BU_H; + } + break; + case 0x1: return LISA_VSSRLRNENI_HU_W; + } + break; + case 0x1: return LISA_VSSRLRNENI_WU_D; + } + break; + case 0x1: return LISA_VSSRLRNENI_DU_Q; + } + break; + case 0xde: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRARNENI_B_H; + } + break; + case 0x1: return LISA_VSSRARNENI_H_W; + } + break; + case 0x1: return LISA_VSSRARNENI_W_D; + } + break; + case 0x1: return LISA_VSSRARNENI_D_Q; + } + break; + case 0xdf: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_VSSRARNENI_BU_H; + } + break; + case 0x1: return LISA_VSSRARNENI_HU_W; + } + break; + case 0x1: return LISA_VSSRARNENI_WU_D; + } + break; + case 0x1: return LISA_VSSRARNENI_DU_Q; + } + break; + case 0xe0: return LISA_VEXTRINS_D; + case 0xe1: return LISA_VEXTRINS_W; + case 0xe2: return LISA_VEXTRINS_H; + case 0xe3: return LISA_VEXTRINS_B; + case 0xe4: return LISA_VSHUF4I_B; + case 0xe5: return LISA_VSHUF4I_H; + case 0xe6: return LISA_VSHUF4I_W; + case 0xe7: return LISA_VSHUF4I_D; + case 0xe8: return LISA_VSHUFI1_B; + case 0xe9: return LISA_VSHUFI2_B; + case 0xea: return LISA_VSHUFI3_B; + case 0xeb: return LISA_VSHUFI4_B; + case 0xec: return LISA_VSHUFI1_H; + case 0xed: return LISA_VSHUFI2_H; + case 0xee: return LISA_VSELI_H; + case 0xef: return LISA_VSELI_W; + case 0xf0: return LISA_VSELI_D; + case 0xf1: return LISA_VBITSELI_B; + case 0xf2: return LISA_VBITMVZI_B; + case 0xf3: return LISA_VBITMVNZI_B; + case 0xf4: return LISA_VANDI_B; + case 0xf5: return LISA_VORI_B; + case 0xf6: return LISA_VXORI_B; + case 0xf7: return LISA_VNORI_B; + case 0xf8: return LISA_VLDI; + case 0xf9: return LISA_VPERMI_W; + } + break; + case 0x1d: + switch ((insn >> 18) & 0xff) { + case 0x0: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSEQ_B; + case 0x1: return LISA_XVSEQ_H; + case 0x2: return LISA_XVSEQ_W; + case 0x3: return LISA_XVSEQ_D; + case 0x4: return LISA_XVSLE_B; + case 0x5: return LISA_XVSLE_H; + case 0x6: return LISA_XVSLE_W; + case 0x7: return LISA_XVSLE_D; + } + break; + case 0x1: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSLE_BU; + case 0x1: return LISA_XVSLE_HU; + case 0x2: return LISA_XVSLE_WU; + case 0x3: return LISA_XVSLE_DU; + case 0x4: return LISA_XVSLT_B; + case 0x5: return LISA_XVSLT_H; + case 0x6: return LISA_XVSLT_W; + case 0x7: return LISA_XVSLT_D; + } + break; + case 0x2: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSLT_BU; + case 0x1: return LISA_XVSLT_HU; + case 0x2: return LISA_XVSLT_WU; + case 0x3: return LISA_XVSLT_DU; + case 0x4: return LISA_XVADD_B; + case 0x5: return LISA_XVADD_H; + case 0x6: return LISA_XVADD_W; + case 0x7: return LISA_XVADD_D; + } + break; + case 0x3: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSUB_B; + case 0x1: return LISA_XVSUB_H; + case 0x2: return LISA_XVSUB_W; + case 0x3: return LISA_XVSUB_D; + } + break; + case 0x7: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_XVADDWEV_H_B; + case 0x5: return LISA_XVADDWEV_W_H; + case 0x6: return LISA_XVADDWEV_D_W; + case 0x7: return LISA_XVADDWEV_Q_D; + } + break; + case 0x8: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSUBWEV_H_B; + case 0x1: return LISA_XVSUBWEV_W_H; + case 0x2: return LISA_XVSUBWEV_D_W; + case 0x3: return LISA_XVSUBWEV_Q_D; + case 0x4: return LISA_XVADDWOD_H_B; + case 0x5: return LISA_XVADDWOD_W_H; + case 0x6: return LISA_XVADDWOD_D_W; + case 0x7: return LISA_XVADDWOD_Q_D; + } + break; + case 0x9: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSUBWOD_H_B; + case 0x1: return LISA_XVSUBWOD_W_H; + case 0x2: return LISA_XVSUBWOD_D_W; + case 0x3: return LISA_XVSUBWOD_Q_D; + } + break; + case 0xb: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_XVADDWEV_H_BU; + case 0x5: return LISA_XVADDWEV_W_HU; + case 0x6: return LISA_XVADDWEV_D_WU; + case 0x7: return LISA_XVADDWEV_Q_DU; + } + break; + case 0xc: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSUBWEV_H_BU; + case 0x1: return LISA_XVSUBWEV_W_HU; + case 0x2: return LISA_XVSUBWEV_D_WU; + case 0x3: return LISA_XVSUBWEV_Q_DU; + case 0x4: return LISA_XVADDWOD_H_BU; + case 0x5: return LISA_XVADDWOD_W_HU; + case 0x6: return LISA_XVADDWOD_D_WU; + case 0x7: return LISA_XVADDWOD_Q_DU; + } + break; + case 0xd: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSUBWOD_H_BU; + case 0x1: return LISA_XVSUBWOD_W_HU; + case 0x2: return LISA_XVSUBWOD_D_WU; + case 0x3: return LISA_XVSUBWOD_Q_DU; + } + break; + case 0xf: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_XVADDWEV_H_BU_B; + case 0x5: return LISA_XVADDWEV_W_HU_H; + case 0x6: return LISA_XVADDWEV_D_WU_W; + case 0x7: return LISA_XVADDWEV_Q_DU_D; + } + break; + case 0x10: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVADDWOD_H_BU_B; + case 0x1: return LISA_XVADDWOD_W_HU_H; + case 0x2: return LISA_XVADDWOD_D_WU_W; + case 0x3: return LISA_XVADDWOD_Q_DU_D; + } + break; + case 0x11: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_XVSADD_B; + case 0x5: return LISA_XVSADD_H; + case 0x6: return LISA_XVSADD_W; + case 0x7: return LISA_XVSADD_D; + } + break; + case 0x12: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSSUB_B; + case 0x1: return LISA_XVSSUB_H; + case 0x2: return LISA_XVSSUB_W; + case 0x3: return LISA_XVSSUB_D; + case 0x4: return LISA_XVSADD_BU; + case 0x5: return LISA_XVSADD_HU; + case 0x6: return LISA_XVSADD_WU; + case 0x7: return LISA_XVSADD_DU; + } + break; + case 0x13: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSSUB_BU; + case 0x1: return LISA_XVSSUB_HU; + case 0x2: return LISA_XVSSUB_WU; + case 0x3: return LISA_XVSSUB_DU; + } + break; + case 0x15: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVHADDW_H_B; + case 0x1: return LISA_XVHADDW_W_H; + case 0x2: return LISA_XVHADDW_D_W; + case 0x3: return LISA_XVHADDW_Q_D; + case 0x4: return LISA_XVHSUBW_H_B; + case 0x5: return LISA_XVHSUBW_W_H; + case 0x6: return LISA_XVHSUBW_D_W; + case 0x7: return LISA_XVHSUBW_Q_D; + } + break; + case 0x16: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVHADDW_HU_BU; + case 0x1: return LISA_XVHADDW_WU_HU; + case 0x2: return LISA_XVHADDW_DU_WU; + case 0x3: return LISA_XVHADDW_QU_DU; + case 0x4: return LISA_XVHSUBW_HU_BU; + case 0x5: return LISA_XVHSUBW_WU_HU; + case 0x6: return LISA_XVHSUBW_DU_WU; + case 0x7: return LISA_XVHSUBW_QU_DU; + } + break; + case 0x17: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVADDA_B; + case 0x1: return LISA_XVADDA_H; + case 0x2: return LISA_XVADDA_W; + case 0x3: return LISA_XVADDA_D; + } + break; + case 0x18: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVABSD_B; + case 0x1: return LISA_XVABSD_H; + case 0x2: return LISA_XVABSD_W; + case 0x3: return LISA_XVABSD_D; + case 0x4: return LISA_XVABSD_BU; + case 0x5: return LISA_XVABSD_HU; + case 0x6: return LISA_XVABSD_WU; + case 0x7: return LISA_XVABSD_DU; + } + break; + case 0x19: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVAVG_B; + case 0x1: return LISA_XVAVG_H; + case 0x2: return LISA_XVAVG_W; + case 0x3: return LISA_XVAVG_D; + case 0x4: return LISA_XVAVG_BU; + case 0x5: return LISA_XVAVG_HU; + case 0x6: return LISA_XVAVG_WU; + case 0x7: return LISA_XVAVG_DU; + } + break; + case 0x1a: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVAVGR_B; + case 0x1: return LISA_XVAVGR_H; + case 0x2: return LISA_XVAVGR_W; + case 0x3: return LISA_XVAVGR_D; + case 0x4: return LISA_XVAVGR_BU; + case 0x5: return LISA_XVAVGR_HU; + case 0x6: return LISA_XVAVGR_WU; + case 0x7: return LISA_XVAVGR_DU; + } + break; + case 0x1c: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMAX_B; + case 0x1: return LISA_XVMAX_H; + case 0x2: return LISA_XVMAX_W; + case 0x3: return LISA_XVMAX_D; + case 0x4: return LISA_XVMIN_B; + case 0x5: return LISA_XVMIN_H; + case 0x6: return LISA_XVMIN_W; + case 0x7: return LISA_XVMIN_D; + } + break; + case 0x1d: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMAX_BU; + case 0x1: return LISA_XVMAX_HU; + case 0x2: return LISA_XVMAX_WU; + case 0x3: return LISA_XVMAX_DU; + case 0x4: return LISA_XVMIN_BU; + case 0x5: return LISA_XVMIN_HU; + case 0x6: return LISA_XVMIN_WU; + case 0x7: return LISA_XVMIN_DU; + } + break; + case 0x21: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMUL_B; + case 0x1: return LISA_XVMUL_H; + case 0x2: return LISA_XVMUL_W; + case 0x3: return LISA_XVMUL_D; + case 0x4: return LISA_XVMUH_B; + case 0x5: return LISA_XVMUH_H; + case 0x6: return LISA_XVMUH_W; + case 0x7: return LISA_XVMUH_D; + } + break; + case 0x22: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMUH_BU; + case 0x1: return LISA_XVMUH_HU; + case 0x2: return LISA_XVMUH_WU; + case 0x3: return LISA_XVMUH_DU; + } + break; + case 0x24: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMULWEV_H_B; + case 0x1: return LISA_XVMULWEV_W_H; + case 0x2: return LISA_XVMULWEV_D_W; + case 0x3: return LISA_XVMULWEV_Q_D; + case 0x4: return LISA_XVMULWOD_H_B; + case 0x5: return LISA_XVMULWOD_W_H; + case 0x6: return LISA_XVMULWOD_D_W; + case 0x7: return LISA_XVMULWOD_Q_D; + } + break; + case 0x26: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMULWEV_H_BU; + case 0x1: return LISA_XVMULWEV_W_HU; + case 0x2: return LISA_XVMULWEV_D_WU; + case 0x3: return LISA_XVMULWEV_Q_DU; + case 0x4: return LISA_XVMULWOD_H_BU; + case 0x5: return LISA_XVMULWOD_W_HU; + case 0x6: return LISA_XVMULWOD_D_WU; + case 0x7: return LISA_XVMULWOD_Q_DU; + } + break; + case 0x2a: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMADD_B; + case 0x1: return LISA_XVMADD_H; + case 0x2: return LISA_XVMADD_W; + case 0x3: return LISA_XVMADD_D; + case 0x4: return LISA_XVMSUB_B; + case 0x5: return LISA_XVMSUB_H; + case 0x6: return LISA_XVMSUB_W; + case 0x7: return LISA_XVMSUB_D; + } + break; + case 0x2b: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMADDWEV_H_B; + case 0x1: return LISA_XVMADDWEV_W_H; + case 0x2: return LISA_XVMADDWEV_D_W; + case 0x3: return LISA_XVMADDWEV_Q_D; + case 0x4: return LISA_XVMADDWOD_H_B; + case 0x5: return LISA_XVMADDWOD_W_H; + case 0x6: return LISA_XVMADDWOD_D_W; + case 0x7: return LISA_XVMADDWOD_Q_D; + } + break; + case 0x2d: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMADDWEV_H_BU; + case 0x1: return LISA_XVMADDWEV_W_HU; + case 0x2: return LISA_XVMADDWEV_D_WU; + case 0x3: return LISA_XVMADDWEV_Q_DU; + case 0x4: return LISA_XVMADDWOD_H_BU; + case 0x5: return LISA_XVMADDWOD_W_HU; + case 0x6: return LISA_XVMADDWOD_D_WU; + case 0x7: return LISA_XVMADDWOD_Q_DU; + } + break; + case 0x2f: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMADDWEV_H_BU_B; + case 0x1: return LISA_XVMADDWEV_W_HU_H; + case 0x2: return LISA_XVMADDWEV_D_WU_W; + case 0x3: return LISA_XVMADDWEV_Q_DU_D; + case 0x4: return LISA_XVMADDWOD_H_BU_B; + case 0x5: return LISA_XVMADDWOD_W_HU_H; + case 0x6: return LISA_XVMADDWOD_D_WU_W; + case 0x7: return LISA_XVMADDWOD_Q_DU_D; + } + break; + case 0x38: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVDIV_B; + case 0x1: return LISA_XVDIV_H; + case 0x2: return LISA_XVDIV_W; + case 0x3: return LISA_XVDIV_D; + case 0x4: return LISA_XVMOD_B; + case 0x5: return LISA_XVMOD_H; + case 0x6: return LISA_XVMOD_W; + case 0x7: return LISA_XVMOD_D; + } + break; + case 0x39: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVDIV_BU; + case 0x1: return LISA_XVDIV_HU; + case 0x2: return LISA_XVDIV_WU; + case 0x3: return LISA_XVDIV_DU; + case 0x4: return LISA_XVMOD_BU; + case 0x5: return LISA_XVMOD_HU; + case 0x6: return LISA_XVMOD_WU; + case 0x7: return LISA_XVMOD_DU; + } + break; + case 0x3a: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSLL_B; + case 0x1: return LISA_XVSLL_H; + case 0x2: return LISA_XVSLL_W; + case 0x3: return LISA_XVSLL_D; + case 0x4: return LISA_XVSRL_B; + case 0x5: return LISA_XVSRL_H; + case 0x6: return LISA_XVSRL_W; + case 0x7: return LISA_XVSRL_D; + } + break; + case 0x3b: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSRA_B; + case 0x1: return LISA_XVSRA_H; + case 0x2: return LISA_XVSRA_W; + case 0x3: return LISA_XVSRA_D; + case 0x4: return LISA_XVROTR_B; + case 0x5: return LISA_XVROTR_H; + case 0x6: return LISA_XVROTR_W; + case 0x7: return LISA_XVROTR_D; + } + break; + case 0x3c: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSRLR_B; + case 0x1: return LISA_XVSRLR_H; + case 0x2: return LISA_XVSRLR_W; + case 0x3: return LISA_XVSRLR_D; + case 0x4: return LISA_XVSRAR_B; + case 0x5: return LISA_XVSRAR_H; + case 0x6: return LISA_XVSRAR_W; + case 0x7: return LISA_XVSRAR_D; + } + break; + case 0x3d: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVSRLN_B_H; + case 0x2: return LISA_XVSRLN_H_W; + case 0x3: return LISA_XVSRLN_W_D; + case 0x5: return LISA_XVSRAN_B_H; + case 0x6: return LISA_XVSRAN_H_W; + case 0x7: return LISA_XVSRAN_W_D; + } + break; + case 0x3e: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVSRLRN_B_H; + case 0x2: return LISA_XVSRLRN_H_W; + case 0x3: return LISA_XVSRLRN_W_D; + case 0x5: return LISA_XVSRARN_B_H; + case 0x6: return LISA_XVSRARN_H_W; + case 0x7: return LISA_XVSRARN_W_D; + } + break; + case 0x3f: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVSSRLN_B_H; + case 0x2: return LISA_XVSSRLN_H_W; + case 0x3: return LISA_XVSSRLN_W_D; + case 0x5: return LISA_XVSSRAN_B_H; + case 0x6: return LISA_XVSSRAN_H_W; + case 0x7: return LISA_XVSSRAN_W_D; + } + break; + case 0x40: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVSSRLRN_B_H; + case 0x2: return LISA_XVSSRLRN_H_W; + case 0x3: return LISA_XVSSRLRN_W_D; + case 0x5: return LISA_XVSSRARN_B_H; + case 0x6: return LISA_XVSSRARN_H_W; + case 0x7: return LISA_XVSSRARN_W_D; + } + break; + case 0x41: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVSSRLN_BU_H; + case 0x2: return LISA_XVSSRLN_HU_W; + case 0x3: return LISA_XVSSRLN_WU_D; + case 0x5: return LISA_XVSSRAN_BU_H; + case 0x6: return LISA_XVSSRAN_HU_W; + case 0x7: return LISA_XVSSRAN_WU_D; + } + break; + case 0x42: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVSSRLRN_BU_H; + case 0x2: return LISA_XVSSRLRN_HU_W; + case 0x3: return LISA_XVSSRLRN_WU_D; + case 0x5: return LISA_XVSSRARN_BU_H; + case 0x6: return LISA_XVSSRARN_HU_W; + case 0x7: return LISA_XVSSRARN_WU_D; + } + break; + case 0x43: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVBITCLR_B; + case 0x1: return LISA_XVBITCLR_H; + case 0x2: return LISA_XVBITCLR_W; + case 0x3: return LISA_XVBITCLR_D; + case 0x4: return LISA_XVBITSET_B; + case 0x5: return LISA_XVBITSET_H; + case 0x6: return LISA_XVBITSET_W; + case 0x7: return LISA_XVBITSET_D; + } + break; + case 0x44: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVBITREV_B; + case 0x1: return LISA_XVBITREV_H; + case 0x2: return LISA_XVBITREV_W; + case 0x3: return LISA_XVBITREV_D; + } + break; + case 0x45: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_XVPACKEV_B; + case 0x5: return LISA_XVPACKEV_H; + case 0x6: return LISA_XVPACKEV_W; + case 0x7: return LISA_XVPACKEV_D; + } + break; + case 0x46: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVPACKOD_B; + case 0x1: return LISA_XVPACKOD_H; + case 0x2: return LISA_XVPACKOD_W; + case 0x3: return LISA_XVPACKOD_D; + case 0x4: return LISA_XVILVL_B; + case 0x5: return LISA_XVILVL_H; + case 0x6: return LISA_XVILVL_W; + case 0x7: return LISA_XVILVL_D; + } + break; + case 0x47: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVILVH_B; + case 0x1: return LISA_XVILVH_H; + case 0x2: return LISA_XVILVH_W; + case 0x3: return LISA_XVILVH_D; + case 0x4: return LISA_XVPICKEV_B; + case 0x5: return LISA_XVPICKEV_H; + case 0x6: return LISA_XVPICKEV_W; + case 0x7: return LISA_XVPICKEV_D; + } + break; + case 0x48: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVPICKOD_B; + case 0x1: return LISA_XVPICKOD_H; + case 0x2: return LISA_XVPICKOD_W; + case 0x3: return LISA_XVPICKOD_D; + case 0x4: return LISA_XVREPLVE_B; + case 0x5: return LISA_XVREPLVE_H; + case 0x6: return LISA_XVREPLVE_W; + case 0x7: return LISA_XVREPLVE_D; + } + break; + case 0x49: + switch ((insn >> 15) & 0x7) { + case 0x4: return LISA_XVAND_V; + case 0x5: return LISA_XVOR_V; + case 0x6: return LISA_XVXOR_V; + case 0x7: return LISA_XVNOR_V; + } + break; + case 0x4a: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVANDN_V; + case 0x1: return LISA_XVORN_V; + case 0x6: return LISA_XVFRSTP_B; + case 0x7: return LISA_XVFRSTP_H; + } + break; + case 0x4b: + switch ((insn >> 15) & 0x7) { + case 0x2: return LISA_XVADD_Q; + case 0x3: return LISA_XVSUB_Q; + case 0x4: return LISA_XVSIGNCOV_B; + case 0x5: return LISA_XVSIGNCOV_H; + case 0x6: return LISA_XVSIGNCOV_W; + case 0x7: return LISA_XVSIGNCOV_D; + } + break; + case 0x4c: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVFADD_S; + case 0x2: return LISA_XVFADD_D; + case 0x5: return LISA_XVFSUB_S; + case 0x6: return LISA_XVFSUB_D; + } + break; + case 0x4d: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVFADDSUB_S; + case 0x2: return LISA_XVFADDSUB_D; + case 0x5: return LISA_XVFSUBADD_S; + case 0x6: return LISA_XVFSUBADD_D; + } + break; + case 0x4e: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVFMUL_S; + case 0x2: return LISA_XVFMUL_D; + case 0x5: return LISA_XVFDIV_S; + case 0x6: return LISA_XVFDIV_D; + } + break; + case 0x4f: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVFMAX_S; + case 0x2: return LISA_XVFMAX_D; + case 0x5: return LISA_XVFMIN_S; + case 0x6: return LISA_XVFMIN_D; + } + break; + case 0x50: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVFMAXA_S; + case 0x2: return LISA_XVFMAXA_D; + case 0x5: return LISA_XVFMINA_S; + case 0x6: return LISA_XVFMINA_D; + } + break; + case 0x51: + switch ((insn >> 15) & 0x7) { + case 0x1: return LISA_XVFSCALEB_S; + case 0x2: return LISA_XVFSCALEB_D; + case 0x4: return LISA_XVFCVT_H_S; + case 0x5: return LISA_XVFCVT_S_D; + } + break; + case 0x52: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVFFINT_S_L; + case 0x3: return LISA_XVFTINT_W_D; + case 0x4: return LISA_XVFTINTRM_W_D; + case 0x5: return LISA_XVFTINTRP_W_D; + case 0x6: return LISA_XVFTINTRZ_W_D; + case 0x7: return LISA_XVFTINTRNE_W_D; + } + break; + case 0x53: + switch ((insn >> 15) & 0x7) { + case 0x5: return LISA_XVHADD4_H_BU; + case 0x6: return LISA_XVSHUF4_W; + case 0x7: return LISA_XVSHUF2_D; + } + break; + case 0x58: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVPMUL_W; + case 0x1: return LISA_XVPMUL_D; + case 0x2: return LISA_XVPMUH_W; + case 0x3: return LISA_XVPMUH_D; + case 0x4: return LISA_XVPMULACC_W; + case 0x5: return LISA_XVPMULACC_D; + case 0x6: return LISA_XVPMUHACC_W; + case 0x7: return LISA_XVPMUHACC_D; + } + break; + case 0x59: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVPMULWL_H_B; + case 0x1: return LISA_XVPMULWL_W_H; + case 0x2: return LISA_XVPMULWL_D_W; + case 0x3: return LISA_XVPMULWL_Q_D; + case 0x4: return LISA_XVPMULWH_H_B; + case 0x5: return LISA_XVPMULWH_W_H; + case 0x6: return LISA_XVPMULWH_D_W; + case 0x7: return LISA_XVPMULWH_Q_D; + } + break; + case 0x5a: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVPMADDWL_H_B; + case 0x1: return LISA_XVPMADDWL_W_H; + case 0x2: return LISA_XVPMADDWL_D_W; + case 0x3: return LISA_XVPMADDWL_Q_D; + case 0x4: return LISA_XVPMADDWH_H_B; + case 0x5: return LISA_XVPMADDWH_W_H; + case 0x6: return LISA_XVPMADDWH_D_W; + case 0x7: return LISA_XVPMADDWH_Q_D; + } + break; + case 0x5b: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVPDP2_Q_D; + case 0x1: return LISA_XVPDP2ADD_Q_D; + } + break; + case 0x5c: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVCDP4_RE_D_H; + case 0x1: return LISA_XVCDP4_IM_D_H; + case 0x2: return LISA_XVCDP4ADD_RE_D_H; + case 0x3: return LISA_XVCDP4ADD_IM_D_H; + case 0x4: return LISA_XVCDP2_RE_Q_W; + case 0x5: return LISA_XVCDP2_IM_Q_W; + case 0x6: return LISA_XVCDP2ADD_RE_Q_W; + case 0x7: return LISA_XVCDP2ADD_IM_Q_W; + } + break; + case 0x5e: + switch ((insn >> 15) & 0x7) { + case 0x2: return LISA_XVSIGNSEL_W; + case 0x3: return LISA_XVSIGNSEL_D; + case 0x5: return LISA_XVSHUF_H; + case 0x6: return LISA_XVSHUF_W; + case 0x7: return LISA_XVSHUF_D; + } + break; + case 0x5f: + switch ((insn >> 15) & 0x7) { + case 0x2: return LISA_XVPERM_W; + } + break; + case 0xa0: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSEQI_B; + case 0x1: return LISA_XVSEQI_H; + case 0x2: return LISA_XVSEQI_W; + case 0x3: return LISA_XVSEQI_D; + case 0x4: return LISA_XVSLEI_B; + case 0x5: return LISA_XVSLEI_H; + case 0x6: return LISA_XVSLEI_W; + case 0x7: return LISA_XVSLEI_D; + } + break; + case 0xa1: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSLEI_BU; + case 0x1: return LISA_XVSLEI_HU; + case 0x2: return LISA_XVSLEI_WU; + case 0x3: return LISA_XVSLEI_DU; + case 0x4: return LISA_XVSLTI_B; + case 0x5: return LISA_XVSLTI_H; + case 0x6: return LISA_XVSLTI_W; + case 0x7: return LISA_XVSLTI_D; + } + break; + case 0xa2: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSLTI_BU; + case 0x1: return LISA_XVSLTI_HU; + case 0x2: return LISA_XVSLTI_WU; + case 0x3: return LISA_XVSLTI_DU; + case 0x4: return LISA_XVADDI_BU; + case 0x5: return LISA_XVADDI_HU; + case 0x6: return LISA_XVADDI_WU; + case 0x7: return LISA_XVADDI_DU; + } + break; + case 0xa3: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVSUBI_BU; + case 0x1: return LISA_XVSUBI_HU; + case 0x2: return LISA_XVSUBI_WU; + case 0x3: return LISA_XVSUBI_DU; + case 0x4: return LISA_XVBSLL_V; + case 0x5: return LISA_XVBSRL_V; + } + break; + case 0xa4: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMAXI_B; + case 0x1: return LISA_XVMAXI_H; + case 0x2: return LISA_XVMAXI_W; + case 0x3: return LISA_XVMAXI_D; + case 0x4: return LISA_XVMINI_B; + case 0x5: return LISA_XVMINI_H; + case 0x6: return LISA_XVMINI_W; + case 0x7: return LISA_XVMINI_D; + } + break; + case 0xa5: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVMAXI_BU; + case 0x1: return LISA_XVMAXI_HU; + case 0x2: return LISA_XVMAXI_WU; + case 0x3: return LISA_XVMAXI_DU; + case 0x4: return LISA_XVMINI_BU; + case 0x5: return LISA_XVMINI_HU; + case 0x6: return LISA_XVMINI_WU; + case 0x7: return LISA_XVMINI_DU; + } + break; + case 0xa6: + switch ((insn >> 15) & 0x7) { + case 0x0: return LISA_XVRANDSIGNI_B; + case 0x1: return LISA_XVRANDSIGNI_H; + case 0x2: return LISA_XVRORSIGNI_B; + case 0x3: return LISA_XVRORSIGNI_H; + case 0x4: return LISA_XVFRSTPI_B; + case 0x5: return LISA_XVFRSTPI_H; + case 0x6: return LISA_XVCLRSTRI_V; + case 0x7: return LISA_XVMEPATMSK_V; + } + break; + case 0xa7: + switch ((insn >> 15) & 0x7) { + case 0x0: + switch ((insn >> 10) & 0x1f) { + case 0x0: return LISA_XVCLO_B; + case 0x1: return LISA_XVCLO_H; + case 0x2: return LISA_XVCLO_W; + case 0x3: return LISA_XVCLO_D; + case 0x4: return LISA_XVCLZ_B; + case 0x5: return LISA_XVCLZ_H; + case 0x6: return LISA_XVCLZ_W; + case 0x7: return LISA_XVCLZ_D; + case 0x8: return LISA_XVPCNT_B; + case 0x9: return LISA_XVPCNT_H; + case 0xa: return LISA_XVPCNT_W; + case 0xb: return LISA_XVPCNT_D; + case 0xc: return LISA_XVNEG_B; + case 0xd: return LISA_XVNEG_H; + case 0xe: return LISA_XVNEG_W; + case 0xf: return LISA_XVNEG_D; + case 0x10: return LISA_XVMSKLTZ_B; + case 0x11: return LISA_XVMSKLTZ_H; + case 0x12: return LISA_XVMSKLTZ_W; + case 0x13: return LISA_XVMSKLTZ_D; + case 0x14: return LISA_XVMSKGEZ_B; + case 0x18: return LISA_XVMSKNZ_B; + case 0x1c: return LISA_XVMSKCOPY_B; + } + break; + case 0x1: + switch ((insn >> 10) & 0x1f) { + case 0x0: return LISA_XVMSKFILL_B; + case 0x4: return LISA_XVFRSTM_B; + case 0x5: return LISA_XVFRSTM_H; + case 0x6: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_XVSETEQZ_V; + } + break; + case 0x7: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_XVSETNEZ_V; + } + break; + case 0x8: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_XVSETANYEQZ_B; + } + break; + case 0x9: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_XVSETANYEQZ_H; + } + break; + case 0xa: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_XVSETANYEQZ_W; + } + break; + case 0xb: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_XVSETANYEQZ_D; + } + break; + case 0xc: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_XVSETALLNEZ_B; + } + break; + case 0xd: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_XVSETALLNEZ_H; + } + break; + case 0xe: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_XVSETALLNEZ_W; + } + break; + case 0xf: + switch ((insn >> 3) & 0x3) { + case 0x0: return LISA_XVSETALLNEZ_D; + } + break; + case 0x11: return LISA_XVFLOGB_S; + case 0x12: return LISA_XVFLOGB_D; + case 0x15: return LISA_XVFCLASS_S; + case 0x16: return LISA_XVFCLASS_D; + case 0x19: return LISA_XVFSQRT_S; + case 0x1a: return LISA_XVFSQRT_D; + case 0x1d: return LISA_XVFRECIP_S; + case 0x1e: return LISA_XVFRECIP_D; + } + break; + case 0x2: + switch ((insn >> 10) & 0x1f) { + case 0x1: return LISA_XVFRSQRT_S; + case 0x2: return LISA_XVFRSQRT_D; + case 0xd: return LISA_XVFRINT_S; + case 0xe: return LISA_XVFRINT_D; + case 0x11: return LISA_XVFRINTRM_S; + case 0x12: return LISA_XVFRINTRM_D; + case 0x15: return LISA_XVFRINTRP_S; + case 0x16: return LISA_XVFRINTRP_D; + case 0x19: return LISA_XVFRINTRZ_S; + case 0x1a: return LISA_XVFRINTRZ_D; + case 0x1d: return LISA_XVFRINTRNE_S; + case 0x1e: return LISA_XVFRINTRNE_D; + } + break; + case 0x3: + switch ((insn >> 10) & 0x1f) { + case 0x1: return LISA_XVEXTL_W_B; + case 0x2: return LISA_XVEXTL_D_B; + case 0x5: return LISA_XVEXTL_D_H; + case 0xb: return LISA_XVEXTL_W_BU; + case 0xc: return LISA_XVEXTL_D_BU; + case 0xf: return LISA_XVEXTL_D_HU; + case 0x14: return LISA_XVHADD8_D_BU; + case 0x15: return LISA_XVHMINPOS_W_HU; + case 0x16: return LISA_XVHMINPOS_D_HU; + case 0x17: return LISA_XVHMINPOS_Q_HU; + case 0x18: return LISA_XVCLRTAIL_B; + case 0x19: return LISA_XVCLRTAIL_H; + case 0x1a: return LISA_XVFCVTL_S_H; + case 0x1b: return LISA_XVFCVTH_S_H; + case 0x1c: return LISA_XVFCVTL_D_S; + case 0x1d: return LISA_XVFCVTH_D_S; + } + break; + case 0x4: + switch ((insn >> 10) & 0x1f) { + case 0x0: return LISA_XVFFINT_S_W; + case 0x1: return LISA_XVFFINT_S_WU; + case 0x2: return LISA_XVFFINT_D_L; + case 0x3: return LISA_XVFFINT_D_LU; + case 0x4: return LISA_XVFFINTL_D_W; + case 0x5: return LISA_XVFFINTH_D_W; + case 0xc: return LISA_XVFTINT_W_S; + case 0xd: return LISA_XVFTINT_L_D; + case 0xe: return LISA_XVFTINTRM_W_S; + case 0xf: return LISA_XVFTINTRM_L_D; + case 0x10: return LISA_XVFTINTRP_W_S; + case 0x11: return LISA_XVFTINTRP_L_D; + case 0x12: return LISA_XVFTINTRZ_W_S; + case 0x13: return LISA_XVFTINTRZ_L_D; + case 0x14: return LISA_XVFTINTRNE_W_S; + case 0x15: return LISA_XVFTINTRNE_L_D; + case 0x16: return LISA_XVFTINT_WU_S; + case 0x17: return LISA_XVFTINT_LU_D; + case 0x1c: return LISA_XVFTINTRZ_WU_S; + case 0x1d: return LISA_XVFTINTRZ_LU_D; + } + break; + case 0x5: + switch ((insn >> 10) & 0x1f) { + case 0x0: return LISA_XVFTINTL_L_S; + case 0x1: return LISA_XVFTINTH_L_S; + case 0x2: return LISA_XVFTINTRML_L_S; + case 0x3: return LISA_XVFTINTRMH_L_S; + case 0x4: return LISA_XVFTINTRPL_L_S; + case 0x5: return LISA_XVFTINTRPH_L_S; + case 0x6: return LISA_XVFTINTRZL_L_S; + case 0x7: return LISA_XVFTINTRZH_L_S; + case 0x8: return LISA_XVFTINTRNEL_L_S; + case 0x9: return LISA_XVFTINTRNEH_L_S; + case 0x18: return LISA_XVEXTH_H_B; + case 0x19: return LISA_XVEXTH_W_H; + case 0x1a: return LISA_XVEXTH_D_W; + case 0x1b: return LISA_XVEXTH_Q_D; + case 0x1c: return LISA_XVEXTH_HU_BU; + case 0x1d: return LISA_XVEXTH_WU_HU; + case 0x1e: return LISA_XVEXTH_DU_WU; + case 0x1f: return LISA_XVEXTH_QU_DU; + } + break; + case 0x6: + switch ((insn >> 10) & 0x1f) { + case 0x0: return LISA_XVREPLGR2VR_B; + case 0x1: return LISA_XVREPLGR2VR_H; + case 0x2: return LISA_XVREPLGR2VR_W; + case 0x3: return LISA_XVREPLGR2VR_D; + case 0x4: return LISA_VEXT2XV_H_B; + case 0x5: return LISA_VEXT2XV_W_B; + case 0x6: return LISA_VEXT2XV_D_B; + case 0x7: return LISA_VEXT2XV_W_H; + case 0x8: return LISA_VEXT2XV_D_H; + case 0x9: return LISA_VEXT2XV_D_W; + case 0xa: return LISA_VEXT2XV_HU_BU; + case 0xb: return LISA_VEXT2XV_WU_BU; + case 0xc: return LISA_VEXT2XV_DU_BU; + case 0xd: return LISA_VEXT2XV_WU_HU; + case 0xe: return LISA_VEXT2XV_DU_HU; + case 0xf: return LISA_VEXT2XV_DU_WU; + } + break; + case 0x7: return LISA_XVHSELI_D; + } + break; + case 0xa8: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVROTRI_B; + } + break; + case 0x1: return LISA_XVROTRI_H; + } + break; + case 0x1: return LISA_XVROTRI_W; + } + break; + case 0x1: return LISA_XVROTRI_D; + } + break; + case 0xa9: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVSRLRI_B; + } + break; + case 0x1: return LISA_XVSRLRI_H; + } + break; + case 0x1: return LISA_XVSRLRI_W; + } + break; + case 0x1: return LISA_XVSRLRI_D; + } + break; + case 0xaa: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVSRARI_B; + } + break; + case 0x1: return LISA_XVSRARI_H; + } + break; + case 0x1: return LISA_XVSRARI_W; + } + break; + case 0x1: return LISA_XVSRARI_D; + } + break; + case 0xba: + switch ((insn >> 13) & 0x1f) { + case 0x1e: return LISA_XVINSGR2VR_W; + case 0x1f: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_XVINSGR2VR_D; + } + break; + } + break; + case 0xbb: + switch ((insn >> 13) & 0x1f) { + case 0x1e: return LISA_XVPICKVE2GR_W; + case 0x1f: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_XVPICKVE2GR_D; + } + break; + } + break; + case 0xbc: + switch ((insn >> 13) & 0x1f) { + case 0x1e: return LISA_XVPICKVE2GR_WU; + case 0x1f: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_XVPICKVE2GR_DU; + } + break; + } + break; + case 0xbd: + switch ((insn >> 14) & 0xf) { + case 0xe: return LISA_XVREPL128VEI_B; + case 0xf: + switch ((insn >> 13) & 0x1) { + case 0x0: return LISA_XVREPL128VEI_H; + case 0x1: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_XVREPL128VEI_W; + case 0x1: + switch ((insn >> 11) & 0x1) { + case 0x0: return LISA_XVREPL128VEI_D; + } + break; + } + break; + } + break; + } + break; + case 0xbe: + switch ((insn >> 14) & 0xf) { + case 0xe: return LISA_XVEXTRCOLI_B; + case 0xf: + switch ((insn >> 13) & 0x1) { + case 0x0: return LISA_XVEXTRCOLI_H; + case 0x1: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_XVEXTRCOLI_W; + case 0x1: + switch ((insn >> 11) & 0x1) { + case 0x0: return LISA_XVEXTRCOLI_D; + } + break; + } + break; + } + break; + } + break; + case 0xbf: + switch ((insn >> 13) & 0x1f) { + case 0x1e: return LISA_XVINSVE0_W; + case 0x1f: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_XVINSVE0_D; + } + break; + } + break; + case 0xc0: + switch ((insn >> 13) & 0x1f) { + case 0x1e: return LISA_XVPICKVE_W; + case 0x1f: + switch ((insn >> 12) & 0x1) { + case 0x0: return LISA_XVPICKVE_D; + } + break; + } + break; + case 0xc1: + switch ((insn >> 10) & 0xff) { + case 0xc0: return LISA_XVREPLVE0_B; + case 0xe0: return LISA_XVREPLVE0_H; + case 0xf0: return LISA_XVREPLVE0_W; + case 0xf8: return LISA_XVREPLVE0_D; + case 0xfc: return LISA_XVREPLVE0_Q; + } + break; + case 0xc2: + switch ((insn >> 15) & 0x7) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVSLLWIL_H_B; + } + break; + case 0x1: return LISA_XVSLLWIL_W_H; + } + break; + case 0x1: return LISA_XVSLLWIL_D_W; + case 0x2: + switch ((insn >> 10) & 0x1f) { + case 0x0: return LISA_XVEXTL_Q_D; + } + break; + } + break; + case 0xc3: + switch ((insn >> 15) & 0x7) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVSLLWIL_HU_BU; + } + break; + case 0x1: return LISA_XVSLLWIL_WU_HU; + } + break; + case 0x1: return LISA_XVSLLWIL_DU_WU; + case 0x2: + switch ((insn >> 10) & 0x1f) { + case 0x0: return LISA_XVEXTL_QU_DU; + } + break; + } + break; + case 0xc4: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVBITCLRI_B; + } + break; + case 0x1: return LISA_XVBITCLRI_H; + } + break; + case 0x1: return LISA_XVBITCLRI_W; + } + break; + case 0x1: return LISA_XVBITCLRI_D; + } + break; + case 0xc5: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVBITSETI_B; + } + break; + case 0x1: return LISA_XVBITSETI_H; + } + break; + case 0x1: return LISA_XVBITSETI_W; + } + break; + case 0x1: return LISA_XVBITSETI_D; + } + break; + case 0xc6: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVBITREVI_B; + } + break; + case 0x1: return LISA_XVBITREVI_H; + } + break; + case 0x1: return LISA_XVBITREVI_W; + } + break; + case 0x1: return LISA_XVBITREVI_D; + } + break; + case 0xc7: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVBSTRC12I_B; + } + break; + case 0x1: return LISA_XVBSTRC12I_H; + } + break; + case 0x1: return LISA_XVBSTRC12I_W; + } + break; + case 0x1: return LISA_XVBSTRC12I_D; + } + break; + case 0xc8: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVBSTRC21I_B; + } + break; + case 0x1: return LISA_XVBSTRC21I_H; + } + break; + case 0x1: return LISA_XVBSTRC21I_W; + } + break; + case 0x1: return LISA_XVBSTRC21I_D; + } + break; + case 0xc9: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVSAT_B; + } + break; + case 0x1: return LISA_XVSAT_H; + } + break; + case 0x1: return LISA_XVSAT_W; + } + break; + case 0x1: return LISA_XVSAT_D; + } + break; + case 0xca: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVSAT_BU; + } + break; + case 0x1: return LISA_XVSAT_HU; + } + break; + case 0x1: return LISA_XVSAT_WU; + } + break; + case 0x1: return LISA_XVSAT_DU; + } + break; + case 0xcb: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVSLLI_B; + } + break; + case 0x1: return LISA_XVSLLI_H; + } + break; + case 0x1: return LISA_XVSLLI_W; + } + break; + case 0x1: return LISA_XVSLLI_D; + } + break; + case 0xcc: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVSRLI_B; + } + break; + case 0x1: return LISA_XVSRLI_H; + } + break; + case 0x1: return LISA_XVSRLI_W; + } + break; + case 0x1: return LISA_XVSRLI_D; + } + break; + case 0xcd: + switch ((insn >> 16) & 0x3) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x0: + switch ((insn >> 13) & 0x1) { + case 0x1: return LISA_XVSRAI_B; + } + break; + case 0x1: return LISA_XVSRAI_H; + } + break; + case 0x1: return LISA_XVSRAI_W; + } + break; + case 0x1: return LISA_XVSRAI_D; + } + break; + case 0xce: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSRLRNENI_B_H; + } + break; + case 0x1: return LISA_XVSRLRNENI_H_W; + } + break; + case 0x1: return LISA_XVSRLRNENI_W_D; + } + break; + case 0x1: return LISA_XVSRLRNENI_D_Q; + } + break; + case 0xcf: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSRARNENI_B_H; + } + break; + case 0x1: return LISA_XVSRARNENI_H_W; + } + break; + case 0x1: return LISA_XVSRARNENI_W_D; + } + break; + case 0x1: return LISA_XVSRARNENI_D_Q; + } + break; + case 0xd0: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSRLNI_B_H; + } + break; + case 0x1: return LISA_XVSRLNI_H_W; + } + break; + case 0x1: return LISA_XVSRLNI_W_D; + } + break; + case 0x1: return LISA_XVSRLNI_D_Q; + } + break; + case 0xd1: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSRLRNI_B_H; + } + break; + case 0x1: return LISA_XVSRLRNI_H_W; + } + break; + case 0x1: return LISA_XVSRLRNI_W_D; + } + break; + case 0x1: return LISA_XVSRLRNI_D_Q; + } + break; + case 0xd2: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRLNI_B_H; + } + break; + case 0x1: return LISA_XVSSRLNI_H_W; + } + break; + case 0x1: return LISA_XVSSRLNI_W_D; + } + break; + case 0x1: return LISA_XVSSRLNI_D_Q; + } + break; + case 0xd3: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRLNI_BU_H; + } + break; + case 0x1: return LISA_XVSSRLNI_HU_W; + } + break; + case 0x1: return LISA_XVSSRLNI_WU_D; + } + break; + case 0x1: return LISA_XVSSRLNI_DU_Q; + } + break; + case 0xd4: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRLRNI_B_H; + } + break; + case 0x1: return LISA_XVSSRLRNI_H_W; + } + break; + case 0x1: return LISA_XVSSRLRNI_W_D; + } + break; + case 0x1: return LISA_XVSSRLRNI_D_Q; + } + break; + case 0xd5: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRLRNI_BU_H; + } + break; + case 0x1: return LISA_XVSSRLRNI_HU_W; + } + break; + case 0x1: return LISA_XVSSRLRNI_WU_D; + } + break; + case 0x1: return LISA_XVSSRLRNI_DU_Q; + } + break; + case 0xd6: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSRANI_B_H; + } + break; + case 0x1: return LISA_XVSRANI_H_W; + } + break; + case 0x1: return LISA_XVSRANI_W_D; + } + break; + case 0x1: return LISA_XVSRANI_D_Q; + } + break; + case 0xd7: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSRARNI_B_H; + } + break; + case 0x1: return LISA_XVSRARNI_H_W; + } + break; + case 0x1: return LISA_XVSRARNI_W_D; + } + break; + case 0x1: return LISA_XVSRARNI_D_Q; + } + break; + case 0xd8: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRANI_B_H; + } + break; + case 0x1: return LISA_XVSSRANI_H_W; + } + break; + case 0x1: return LISA_XVSSRANI_W_D; + } + break; + case 0x1: return LISA_XVSSRANI_D_Q; + } + break; + case 0xd9: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRANI_BU_H; + } + break; + case 0x1: return LISA_XVSSRANI_HU_W; + } + break; + case 0x1: return LISA_XVSSRANI_WU_D; + } + break; + case 0x1: return LISA_XVSSRANI_DU_Q; + } + break; + case 0xda: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRARNI_B_H; + } + break; + case 0x1: return LISA_XVSSRARNI_H_W; + } + break; + case 0x1: return LISA_XVSSRARNI_W_D; + } + break; + case 0x1: return LISA_XVSSRARNI_D_Q; + } + break; + case 0xdb: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRARNI_BU_H; + } + break; + case 0x1: return LISA_XVSSRARNI_HU_W; + } + break; + case 0x1: return LISA_XVSSRARNI_WU_D; + } + break; + case 0x1: return LISA_XVSSRARNI_DU_Q; + } + break; + case 0xdc: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRLRNENI_B_H; + } + break; + case 0x1: return LISA_XVSSRLRNENI_H_W; + } + break; + case 0x1: return LISA_XVSSRLRNENI_W_D; + } + break; + case 0x1: return LISA_XVSSRLRNENI_D_Q; + } + break; + case 0xdd: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRLRNENI_BU_H; + } + break; + case 0x1: return LISA_XVSSRLRNENI_HU_W; + } + break; + case 0x1: return LISA_XVSSRLRNENI_WU_D; + } + break; + case 0x1: return LISA_XVSSRLRNENI_DU_Q; + } + break; + case 0xde: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRARNENI_B_H; + } + break; + case 0x1: return LISA_XVSSRARNENI_H_W; + } + break; + case 0x1: return LISA_XVSSRARNENI_W_D; + } + break; + case 0x1: return LISA_XVSSRARNENI_D_Q; + } + break; + case 0xdf: + switch ((insn >> 17) & 0x1) { + case 0x0: + switch ((insn >> 16) & 0x1) { + case 0x0: + switch ((insn >> 15) & 0x1) { + case 0x0: + switch ((insn >> 14) & 0x1) { + case 0x1: return LISA_XVSSRARNENI_BU_H; + } + break; + case 0x1: return LISA_XVSSRARNENI_HU_W; + } + break; + case 0x1: return LISA_XVSSRARNENI_WU_D; + } + break; + case 0x1: return LISA_XVSSRARNENI_DU_Q; + } + break; + case 0xe0: return LISA_XVEXTRINS_D; + case 0xe1: return LISA_XVEXTRINS_W; + case 0xe2: return LISA_XVEXTRINS_H; + case 0xe3: return LISA_XVEXTRINS_B; + case 0xe4: return LISA_XVSHUF4I_B; + case 0xe5: return LISA_XVSHUF4I_H; + case 0xe6: return LISA_XVSHUF4I_W; + case 0xe7: return LISA_XVSHUF4I_D; + case 0xe8: return LISA_XVSHUFI1_B; + case 0xe9: return LISA_XVSHUFI2_B; + case 0xea: return LISA_XVSHUFI3_B; + case 0xeb: return LISA_XVSHUFI4_B; + case 0xec: return LISA_XVSHUFI1_H; + case 0xed: return LISA_XVSHUFI2_H; + case 0xee: return LISA_XVSELI_H; + case 0xef: return LISA_XVSELI_W; + case 0xf0: return LISA_XVSELI_D; + case 0xf1: return LISA_XVBITSELI_B; + case 0xf2: return LISA_XVBITMVZI_B; + case 0xf3: return LISA_XVBITMVNZI_B; + case 0xf4: return LISA_XVANDI_B; + case 0xf5: return LISA_XVORI_B; + case 0xf6: return LISA_XVXORI_B; + case 0xf7: return LISA_XVNORI_B; + case 0xf8: return LISA_XVLDI; + case 0xf9: return LISA_XVPERMI_W; + case 0xfa: return LISA_XVPERMI_D; + case 0xfb: return LISA_XVPERMI_Q; + } + break; + } + return LISA_INVALID; +} + +static const char *ir2_ins_name[] = { + "INVALID", + "ill", + "label", + "x86.inst", + "dup", + "mov64", + "mov32.sx", + "mov32.zx", + "clr.h32", + "add", + "sub", + "addi.addrx", + "load.addrx", + "store.addrx", + "gr2scr", + "scr2gr", + "clo.w", + "clz.w", + "cto.w", + "ctz.w", + "clo.d", + "clz.d", + "cto.d", + "ctz.d", + "revb.2h", + "revb.4h", + "revb.2w", + "revb.d", + "revh.2w", + "revh.d", + "bitrev.4b", + "bitrev.8b", + "bitrev.w", + "bitrev.d", + "ext.w_h", + "ext.w_b", + "rdtimel.w", + "rdtimeh.w", + "rdtime.d", + "cpucfg", + "x86mttop", + "x86mftop", + "x86loope", + "x86loopne", + "x86inc.b", + "x86inc.h", + "x86inc.w", + "x86inc.d", + "x86dec.b", + "x86dec.h", + "x86dec.w", + "x86dec.d", + "x86settm", + "x86clrtm", + "x86inctop", + "x86dectop", + "asrtle.d", + "asrtgt.d", + "alsl.w", + "alsl.wu", + "bytepick.w", + "bytepick.d", + "add.w", + "add.d", + "sub.w", + "sub.d", + "slt", + "sltu", + "maskeqz", + "masknez", + "nor", + "and", + "or", + "xor", + "orn", + "andn", + "sll.w", + "srl.w", + "sra.w", + "sll.d", + "srl.d", + "sra.d", + "rotr.b", + "rotr.h", + "rotr.w", + "rotr.d", + "mul.w", + "mulh.w", + "mulh.wu", + "mul.d", + "mulh.d", + "mulh.du", + "mulw.d_w", + "mulw.d_wu", + "div.w", + "mod.w", + "div.wu", + "mod.wu", + "div.d", + "mod.d", + "div.du", + "mod.du", + "crc.w_b_w", + "crc.w_h_w", + "crc.w_w_w", + "crc.w_d_w", + "crcc.w_b_w", + "crcc.w_h_w", + "crcc.w_w_w", + "crcc.w_d_w", + "addu12i.w", + "addu12i.d", + "break", + "dbgcall", + "syscall", + "hypcall", + "alsl.d", + "adc.b", + "adc.h", + "adc.w", + "adc.d", + "sbc.b", + "sbc.h", + "sbc.w", + "sbc.d", + "rcr.b", + "rcr.h", + "rcr.w", + "rcr.d", + "armmove", + "setx86j", + "setarmj", + "armadd.w", + "armsub.w", + "armadc.w", + "armsbc.w", + "armand.w", + "armor.w", + "armxor.w", + "armsll.w", + "armsrl.w", + "armsra.w", + "armrotr.w", + "armslli.w", + "armsrli.w", + "armsrai.w", + "armrotri.w", + "x86mul.b", + "x86mul.h", + "x86mul.w", + "x86mul.d", + "x86mul.bu", + "x86mul.hu", + "x86mul.wu", + "x86mul.du", + "x86add.wu", + "x86add.du", + "x86sub.wu", + "x86sub.du", + "x86add.b", + "x86add.h", + "x86add.w", + "x86add.d", + "x86sub.b", + "x86sub.h", + "x86sub.w", + "x86sub.d", + "x86adc.b", + "x86adc.h", + "x86adc.w", + "x86adc.d", + "x86sbc.b", + "x86sbc.h", + "x86sbc.w", + "x86sbc.d", + "x86sll.b", + "x86sll.h", + "x86sll.w", + "x86sll.d", + "x86srl.b", + "x86srl.h", + "x86srl.w", + "x86srl.d", + "x86sra.b", + "x86sra.h", + "x86sra.w", + "x86sra.d", + "x86rotr.b", + "x86rotr.h", + "x86rotr.d", + "x86rotr.w", + "x86rotl.b", + "x86rotl.h", + "x86rotl.w", + "x86rotl.d", + "x86rcr.b", + "x86rcr.h", + "x86rcr.w", + "x86rcr.d", + "x86rcl.b", + "x86rcl.h", + "x86rcl.w", + "x86rcl.d", + "x86and.b", + "x86and.h", + "x86and.w", + "x86and.d", + "x86or.b", + "x86or.h", + "x86or.w", + "x86or.d", + "x86xor.b", + "x86xor.h", + "x86xor.w", + "x86xor.d", + "armnot.w", + "armmov.w", + "armmov.d", + "armrrx.w", + "slli.w", + "slli.d", + "srli.w", + "srli.d", + "srai.w", + "srai.d", + "rotri.b", + "rotri.h", + "rotri.w", + "rotri.d", + "rcri.b", + "rcri.h", + "rcri.w", + "rcri.d", + "x86slli.b", + "x86slli.h", + "x86slli.w", + "x86slli.d", + "x86srli.b", + "x86srli.h", + "x86srli.w", + "x86srli.d", + "x86srai.b", + "x86srai.h", + "x86srai.w", + "x86srai.d", + "x86rotri.b", + "x86rotri.h", + "x86rotri.w", + "x86rotri.d", + "x86rcri.b", + "x86rcri.h", + "x86rcri.w", + "x86rcri.d", + "x86rotli.b", + "x86rotli.h", + "x86rotli.w", + "x86rotli.d", + "x86rcli.b", + "x86rcli.h", + "x86rcli.w", + "x86rcli.d", + "x86settag", + "x86mfflag", + "x86mtflag", + "armmfflag", + "armmtflag", + "bstrins.w", + "bstrpick.w", + "bstrins.d", + "bstrpick.d", + "slti", + "sltui", + "addi.w", + "addi.d", + "lu52i.d", + "andi", + "ori", + "xori", + "addu16i.d", + "lu12i.w", + "lu32i.d", + "pcaddi", + "pcalau12i", + "pcaddu12i", + "pcaddu18i", + "ll.w", + "sc.w", + "ll.d", + "sc.d", + "ldptr.w", + "stptr.w", + "ldptr.d", + "stptr.d", + "ld.b", + "ld.h", + "ld.w", + "ld.d", + "st.b", + "st.h", + "st.w", + "st.d", + "ld.bu", + "ld.hu", + "ld.wu", + "preld", + "fld.s", + "fst.s", + "fld.d", + "fst.d", + "vld", + "vst", + "xvld", + "xvst", + "ldl.w", + "ldr.w", + "ldl.d", + "ldr.d", + "stl.w", + "str.w", + "stl.d", + "str.d", + "vldrepl.d", + "vldrepl.w", + "vldrepl.h", + "vldrepl.b", + "vstelm.d", + "vstelm.w", + "vstelm.h", + "vstelm.b", + "xvldrepl.d", + "xvldrepl.w", + "xvldrepl.h", + "xvldrepl.b", + "xvstelm.d", + "xvstelm.w", + "xvstelm.h", + "xvstelm.b", + "ldx.b", + "ldx.h", + "ldx.w", + "ldx.d", + "stx.b", + "stx.h", + "stx.w", + "stx.d", + "ldx.bu", + "ldx.hu", + "ldx.wu", + "preldx", + "fldx.s", + "fldx.d", + "fstx.s", + "fstx.d", + "vldx", + "vstx", + "xvldx", + "xvstx", + "amswap.w", + "amswap.d", + "amadd.w", + "amadd.d", + "amand.w", + "amand.d", + "amor.w", + "amor.d", + "amxor.w", + "amxor.d", + "ammax.w", + "ammax.d", + "ammin.w", + "ammin.d", + "ammax.wu", + "ammax.du", + "ammin.wu", + "ammin.du", + "amswap.db_w", + "amswap.db_d", + "amadd.db_w", + "amadd.db_d", + "amand.db_w", + "amand.db_d", + "amor.db_w", + "amor.db_d", + "amxor.db_w", + "amxor.db_d", + "ammax.db_w", + "ammax.db_d", + "ammin.db_w", + "ammin.db_d", + "ammax.db_wu", + "ammax.db_du", + "ammin.db_wu", + "ammin.db_du", + "dbar", + "ibar", + "fldgt.s", + "fldgt.d", + "fldle.s", + "fldle.d", + "fstgt.s", + "fstgt.d", + "fstle.s", + "fstle.d", + "ldgt.b", + "ldgt.h", + "ldgt.w", + "ldgt.d", + "ldle.b", + "ldle.h", + "ldle.w", + "ldle.d", + "stgt.b", + "stgt.h", + "stgt.w", + "stgt.d", + "stle.b", + "stle.h", + "stle.w", + "stle.d", + "beqz", + "bnez", + "bceqz", + "bcnez", + "jiscr0", + "jiscr1", + "jirl", + "b", + "bl", + "beq", + "bne", + "blt", + "bge", + "bltu", + "bgeu", + "fadd.s", + "fadd.d", + "fsub.s", + "fsub.d", + "fmul.s", + "fmul.d", + "fdiv.s", + "fdiv.d", + "fmax.s", + "fmax.d", + "fmin.s", + "fmin.d", + "fmaxa.s", + "fmaxa.d", + "fmina.s", + "fmina.d", + "fscaleb.s", + "fscaleb.d", + "fcopysign.s", + "fcopysign.d", + "fabs.s", + "fabs.d", + "fneg.s", + "fneg.d", + "flogb.s", + "flogb.d", + "fclass.s", + "fclass.d", + "fsqrt.s", + "fsqrt.d", + "frecip.s", + "frecip.d", + "frsqrt.s", + "frsqrt.d", + "fmov.s", + "fmov.d", + "movgr2fr.w", + "movgr2fr.d", + "movgr2frh.w", + "movfr2gr.s", + "movfr2gr.d", + "movfrh2gr.s", + "movgr2fcsr", + "movfcsr2gr", + "movfr2cf", + "movcf2fr", + "movgr2cf", + "movcf2gr", + "fcvt.ld_d", + "fcvt.ud_d", + "fcvt.d_ld", + "fcvt.s_d", + "fcvt.d_s", + "ftintrm.w_s", + "ftintrm.w_d", + "ftintrm.l_s", + "ftintrm.l_d", + "ftintrp.w_s", + "ftintrp.w_d", + "ftintrp.l_s", + "ftintrp.l_d", + "ftintrz.w_s", + "ftintrz.w_d", + "ftintrz.l_s", + "ftintrz.l_d", + "ftintrne.w_s", + "ftintrne.w_d", + "ftintrne.l_s", + "ftintrne.l_d", + "ftint.w_s", + "ftint.w_d", + "ftint.l_s", + "ftint.l_d", + "ffint.s_w", + "ffint.s_l", + "ffint.d_w", + "ffint.d_l", + "frint.s", + "frint.d", + "fmadd.s", + "fmadd.d", + "fmsub.s", + "fmsub.d", + "fnmadd.s", + "fnmadd.d", + "fnmsub.s", + "fnmsub.d", + "vfmadd.s", + "vfmadd.d", + "vfmsub.s", + "vfmsub.d", + "vfnmadd.s", + "vfnmadd.d", + "vfnmsub.s", + "vfnmsub.d", + "xvfmadd.s", + "xvfmadd.d", + "xvfmsub.s", + "xvfmsub.d", + "xvfnmadd.s", + "xvfnmadd.d", + "xvfnmsub.s", + "xvfnmsub.d", + "fcmp.cond_s", + "fcmp.cond_d", + "vfcmp.cond_s", + "vfcmp.cond_d", + "xvfcmp.cond_s", + "xvfcmp.cond_d", + "fsel", + "vbitsel.v", + "xvbitsel.v", + "vshuf.b", + "xvshuf.b", + "vextr.v", + "xvextr.v", + "vfmaddsub.s", + "vfmaddsub.d", + "vfmsubadd.s", + "vfmsubadd.d", + "xvfmaddsub.s", + "xvfmaddsub.d", + "xvfmsubadd.s", + "xvfmsubadd.d", + "vseq.b", + "vseq.h", + "vseq.w", + "vseq.d", + "vsle.b", + "vsle.h", + "vsle.w", + "vsle.d", + "vsle.bu", + "vsle.hu", + "vsle.wu", + "vsle.du", + "vslt.b", + "vslt.h", + "vslt.w", + "vslt.d", + "vslt.bu", + "vslt.hu", + "vslt.wu", + "vslt.du", + "vadd.b", + "vadd.h", + "vadd.w", + "vadd.d", + "vsub.b", + "vsub.h", + "vsub.w", + "vsub.d", + "vaddw.h_h_b", + "vaddw.w_w_h", + "vaddw.d_d_w", + "vaddw.h_h_bu", + "vaddw.w_w_hu", + "vaddw.d_d_wu", + "vsubw.h_h_b", + "vsubw.w_w_h", + "vsubw.d_d_w", + "vsubw.h_h_bu", + "vsubw.w_w_hu", + "vsubw.d_d_wu", + "vsaddw.h_h_b", + "vsaddw.w_w_h", + "vsaddw.d_d_w", + "vsaddw.hu_hu_bu", + "vsaddw.wu_wu_hu", + "vsaddw.du_du_wu", + "vssubw.h_h_b", + "vssubw.w_w_h", + "vssubw.d_d_w", + "vssubw.hu_hu_bu", + "vssubw.wu_wu_hu", + "vssubw.du_du_wu", + "vaddwev.h_b", + "vaddwev.w_h", + "vaddwev.d_w", + "vaddwev.q_d", + "vsubwev.h_b", + "vsubwev.w_h", + "vsubwev.d_w", + "vsubwev.q_d", + "vaddwod.h_b", + "vaddwod.w_h", + "vaddwod.d_w", + "vaddwod.q_d", + "vsubwod.h_b", + "vsubwod.w_h", + "vsubwod.d_w", + "vsubwod.q_d", + "vaddwl.h_b", + "vaddwl.w_h", + "vaddwl.d_w", + "vaddwl.q_d", + "vsubwl.h_b", + "vsubwl.w_h", + "vsubwl.d_w", + "vsubwl.q_d", + "vaddwh.h_b", + "vaddwh.w_h", + "vaddwh.d_w", + "vaddwh.q_d", + "vsubwh.h_b", + "vsubwh.w_h", + "vsubwh.d_w", + "vsubwh.q_d", + "vaddwev.h_bu", + "vaddwev.w_hu", + "vaddwev.d_wu", + "vaddwev.q_du", + "vsubwev.h_bu", + "vsubwev.w_hu", + "vsubwev.d_wu", + "vsubwev.q_du", + "vaddwod.h_bu", + "vaddwod.w_hu", + "vaddwod.d_wu", + "vaddwod.q_du", + "vsubwod.h_bu", + "vsubwod.w_hu", + "vsubwod.d_wu", + "vsubwod.q_du", + "vaddwl.h_bu", + "vaddwl.w_hu", + "vaddwl.d_wu", + "vaddwl.q_du", + "vsubwl.h_bu", + "vsubwl.w_hu", + "vsubwl.d_wu", + "vsubwl.q_du", + "vaddwh.h_bu", + "vaddwh.w_hu", + "vaddwh.d_wu", + "vaddwh.q_du", + "vsubwh.h_bu", + "vsubwh.w_hu", + "vsubwh.d_wu", + "vsubwh.q_du", + "vaddwev.h_bu_b", + "vaddwev.w_hu_h", + "vaddwev.d_wu_w", + "vaddwev.q_du_d", + "vaddwod.h_bu_b", + "vaddwod.w_hu_h", + "vaddwod.d_wu_w", + "vaddwod.q_du_d", + "vaddwl.h_bu_b", + "vaddwl.w_hu_h", + "vaddwl.d_wu_w", + "vaddwl.q_du_d", + "vaddwh.h_bu_b", + "vaddwh.w_hu_h", + "vaddwh.d_wu_w", + "vaddwh.q_du_d", + "vsadd.b", + "vsadd.h", + "vsadd.w", + "vsadd.d", + "vssub.b", + "vssub.h", + "vssub.w", + "vssub.d", + "vsadd.bu", + "vsadd.hu", + "vsadd.wu", + "vsadd.du", + "vssub.bu", + "vssub.hu", + "vssub.wu", + "vssub.du", + "vssub.bu_bu_b", + "vssub.hu_hu_h", + "vssub.wu_wu_w", + "vssub.du_du_d", + "vssub.bu_b_bu", + "vssub.hu_h_hu", + "vssub.wu_w_wu", + "vssub.du_d_du", + "vssub.b_bu_bu", + "vssub.h_hu_hu", + "vssub.w_wu_wu", + "vssub.d_du_du", + "vhaddw.h_b", + "vhaddw.w_h", + "vhaddw.d_w", + "vhaddw.q_d", + "vhsubw.h_b", + "vhsubw.w_h", + "vhsubw.d_w", + "vhsubw.q_d", + "vhaddw.hu_bu", + "vhaddw.wu_hu", + "vhaddw.du_wu", + "vhaddw.qu_du", + "vhsubw.hu_bu", + "vhsubw.wu_hu", + "vhsubw.du_wu", + "vhsubw.qu_du", + "vadda.b", + "vadda.h", + "vadda.w", + "vadda.d", + "vsadda.b", + "vsadda.h", + "vsadda.w", + "vsadda.d", + "vabsd.b", + "vabsd.h", + "vabsd.w", + "vabsd.d", + "vabsd.bu", + "vabsd.hu", + "vabsd.wu", + "vabsd.du", + "vavg.b", + "vavg.h", + "vavg.w", + "vavg.d", + "vavg.bu", + "vavg.hu", + "vavg.wu", + "vavg.du", + "vavgr.b", + "vavgr.h", + "vavgr.w", + "vavgr.d", + "vavgr.bu", + "vavgr.hu", + "vavgr.wu", + "vavgr.du", + "vhalfd.b", + "vhalfd.h", + "vhalfd.w", + "vhalfd.d", + "vhalfd.bu", + "vhalfd.hu", + "vhalfd.wu", + "vhalfd.du", + "vmax.b", + "vmax.h", + "vmax.w", + "vmax.d", + "vmin.b", + "vmin.h", + "vmin.w", + "vmin.d", + "vmax.bu", + "vmax.hu", + "vmax.wu", + "vmax.du", + "vmin.bu", + "vmin.hu", + "vmin.wu", + "vmin.du", + "vmaxa.b", + "vmaxa.h", + "vmaxa.w", + "vmaxa.d", + "vmina.b", + "vmina.h", + "vmina.w", + "vmina.d", + "vsadw.h_b", + "vsadw.w_h", + "vsadw.d_w", + "vsadw.h_bu", + "vsadw.w_hu", + "vsadw.d_wu", + "vaccsadw.h_b", + "vaccsadw.w_h", + "vaccsadw.d_w", + "vaccsadw.h_bu", + "vaccsadw.w_hu", + "vaccsadw.d_wu", + "vmul.b", + "vmul.h", + "vmul.w", + "vmul.d", + "vmuh.b", + "vmuh.h", + "vmuh.w", + "vmuh.d", + "vmuh.bu", + "vmuh.hu", + "vmuh.wu", + "vmuh.du", + "vmuh.bu_b", + "vmuh.hu_h", + "vmuh.wu_w", + "vmuh.du_d", + "vmulxw.h_b", + "vmulxw.w_h", + "vmulxw.d_w", + "vmulxw.h_bu", + "vmulxw.w_hu", + "vmulxw.d_wu", + "vmulwev.h_b", + "vmulwev.w_h", + "vmulwev.d_w", + "vmulwev.q_d", + "vmulwod.h_b", + "vmulwod.w_h", + "vmulwod.d_w", + "vmulwod.q_d", + "vmulwl.h_b", + "vmulwl.w_h", + "vmulwl.d_w", + "vmulwl.q_d", + "vmulwh.h_b", + "vmulwh.w_h", + "vmulwh.d_w", + "vmulwh.q_d", + "vmulwev.h_bu", + "vmulwev.w_hu", + "vmulwev.d_wu", + "vmulwev.q_du", + "vmulwod.h_bu", + "vmulwod.w_hu", + "vmulwod.d_wu", + "vmulwod.q_du", + "vmulwl.h_bu", + "vmulwl.w_hu", + "vmulwl.d_wu", + "vmulwl.q_du", + "vmulwh.h_bu", + "vmulwh.w_hu", + "vmulwh.d_wu", + "vmulwh.q_du", + "vmulwev.h_bu_b", + "vmulwev.w_hu_h", + "vmulwev.d_wu_w", + "vmulwev.q_du_d", + "vmulwod.h_bu_b", + "vmulwod.w_hu_h", + "vmulwod.d_wu_w", + "vmulwod.q_du_d", + "vmulwl.h_bu_b", + "vmulwl.w_hu_h", + "vmulwl.d_wu_w", + "vmulwl.q_du_d", + "vmulwh.h_bu_b", + "vmulwh.w_hu_h", + "vmulwh.d_wu_w", + "vmulwh.q_du_d", + "vmadd.b", + "vmadd.h", + "vmadd.w", + "vmadd.d", + "vmsub.b", + "vmsub.h", + "vmsub.w", + "vmsub.d", + "vmaddwev.h_b", + "vmaddwev.w_h", + "vmaddwev.d_w", + "vmaddwev.q_d", + "vmaddwod.h_b", + "vmaddwod.w_h", + "vmaddwod.d_w", + "vmaddwod.q_d", + "vmaddwl.h_b", + "vmaddwl.w_h", + "vmaddwl.d_w", + "vmaddwl.q_d", + "vmaddwh.h_b", + "vmaddwh.w_h", + "vmaddwh.d_w", + "vmaddwh.q_d", + "vmaddwev.h_bu", + "vmaddwev.w_hu", + "vmaddwev.d_wu", + "vmaddwev.q_du", + "vmaddwod.h_bu", + "vmaddwod.w_hu", + "vmaddwod.d_wu", + "vmaddwod.q_du", + "vmaddwl.h_bu", + "vmaddwl.w_hu", + "vmaddwl.d_wu", + "vmaddwl.q_du", + "vmaddwh.h_bu", + "vmaddwh.w_hu", + "vmaddwh.d_wu", + "vmaddwh.q_du", + "vmaddwev.h_bu_b", + "vmaddwev.w_hu_h", + "vmaddwev.d_wu_w", + "vmaddwev.q_du_d", + "vmaddwod.h_bu_b", + "vmaddwod.w_hu_h", + "vmaddwod.d_wu_w", + "vmaddwod.q_du_d", + "vmaddwl.h_bu_b", + "vmaddwl.w_hu_h", + "vmaddwl.d_wu_w", + "vmaddwl.q_du_d", + "vmaddwh.h_bu_b", + "vmaddwh.w_hu_h", + "vmaddwh.d_wu_w", + "vmaddwh.q_du_d", + "vdp2.h_b", + "vdp2.w_h", + "vdp2.d_w", + "vdp2.q_d", + "vdp2.hu_bu", + "vdp2.wu_hu", + "vdp2.du_wu", + "vdp2.qu_du", + "vdp2.h_bu_b", + "vdp2.w_hu_h", + "vdp2.d_wu_w", + "vdp2.q_du_d", + "vdp2add.h_b", + "vdp2add.w_h", + "vdp2add.d_w", + "vdp2add.q_d", + "vdp2add.h_bu", + "vdp2add.w_hu", + "vdp2add.d_wu", + "vdp2add.q_du", + "vdp2add.h_bu_b", + "vdp2add.w_hu_h", + "vdp2add.d_wu_w", + "vdp2add.q_du_d", + "vdp2sub.h_b", + "vdp2sub.w_h", + "vdp2sub.d_w", + "vdp2sub.q_d", + "vdp2sub.h_bu", + "vdp2sub.w_hu", + "vdp2sub.d_wu", + "vdp2sub.q_du", + "vdp4.w_b", + "vdp4.d_h", + "vdp4.q_w", + "vdp4.w_bu", + "vdp4.d_hu", + "vdp4.q_wu", + "vdp4.w_bu_b", + "vdp4.d_hu_h", + "vdp4.q_wu_w", + "vdp4add.w_b", + "vdp4add.d_h", + "vdp4add.q_w", + "vdp4add.w_bu", + "vdp4add.d_hu", + "vdp4add.q_wu", + "vdp4add.w_bu_b", + "vdp4add.d_hu_h", + "vdp4add.q_wu_w", + "vdiv.b", + "vdiv.h", + "vdiv.w", + "vdiv.d", + "vmod.b", + "vmod.h", + "vmod.w", + "vmod.d", + "vdiv.bu", + "vdiv.hu", + "vdiv.wu", + "vdiv.du", + "vmod.bu", + "vmod.hu", + "vmod.wu", + "vmod.du", + "vsll.b", + "vsll.h", + "vsll.w", + "vsll.d", + "vsrl.b", + "vsrl.h", + "vsrl.w", + "vsrl.d", + "vsra.b", + "vsra.h", + "vsra.w", + "vsra.d", + "vrotr.b", + "vrotr.h", + "vrotr.w", + "vrotr.d", + "vsrlr.b", + "vsrlr.h", + "vsrlr.w", + "vsrlr.d", + "vsrar.b", + "vsrar.h", + "vsrar.w", + "vsrar.d", + "vsrln.b_h", + "vsrln.h_w", + "vsrln.w_d", + "vsran.b_h", + "vsran.h_w", + "vsran.w_d", + "vsrlrn.b_h", + "vsrlrn.h_w", + "vsrlrn.w_d", + "vsrarn.b_h", + "vsrarn.h_w", + "vsrarn.w_d", + "vssrln.b_h", + "vssrln.h_w", + "vssrln.w_d", + "vssran.b_h", + "vssran.h_w", + "vssran.w_d", + "vssrlrn.b_h", + "vssrlrn.h_w", + "vssrlrn.w_d", + "vssrarn.b_h", + "vssrarn.h_w", + "vssrarn.w_d", + "vssrln.bu_h", + "vssrln.hu_w", + "vssrln.wu_d", + "vssran.bu_h", + "vssran.hu_w", + "vssran.wu_d", + "vssrlrn.bu_h", + "vssrlrn.hu_w", + "vssrlrn.wu_d", + "vssrarn.bu_h", + "vssrarn.hu_w", + "vssrarn.wu_d", + "vbitclr.b", + "vbitclr.h", + "vbitclr.w", + "vbitclr.d", + "vbitset.b", + "vbitset.h", + "vbitset.w", + "vbitset.d", + "vbitrev.b", + "vbitrev.h", + "vbitrev.w", + "vbitrev.d", + "vbstrc12.b", + "vbstrc12.h", + "vbstrc12.w", + "vbstrc12.d", + "vbstrc21.b", + "vbstrc21.h", + "vbstrc21.w", + "vbstrc21.d", + "vpackev.b", + "vpackev.h", + "vpackev.w", + "vpackev.d", + "vpackod.b", + "vpackod.h", + "vpackod.w", + "vpackod.d", + "vilvl.b", + "vilvl.h", + "vilvl.w", + "vilvl.d", + "vilvh.b", + "vilvh.h", + "vilvh.w", + "vilvh.d", + "vpickev.b", + "vpickev.h", + "vpickev.w", + "vpickev.d", + "vpickod.b", + "vpickod.h", + "vpickod.w", + "vpickod.d", + "vreplve.b", + "vreplve.h", + "vreplve.w", + "vreplve.d", + "vextrcol.b", + "vextrcol.h", + "vextrcol.w", + "vextrcol.d", + "vand.v", + "vor.v", + "vxor.v", + "vnor.v", + "vandn.v", + "vorn.v", + "vrandsign.b", + "vrandsign.h", + "vrorsign.b", + "vrorsign.h", + "vfrstp.b", + "vfrstp.h", + "vclrstrr.v", + "vclrstrv.v", + "vadd.q", + "vsub.q", + "vsigncov.b", + "vsigncov.h", + "vsigncov.w", + "vsigncov.d", + "vfadd.s", + "vfadd.d", + "vfsub.s", + "vfsub.d", + "vfaddsub.s", + "vfaddsub.d", + "vfsubadd.s", + "vfsubadd.d", + "vfmul.s", + "vfmul.d", + "vfdiv.s", + "vfdiv.d", + "vfmax.s", + "vfmax.d", + "vfmin.s", + "vfmin.d", + "vfmaxa.s", + "vfmaxa.d", + "vfmina.s", + "vfmina.d", + "vfscaleb.s", + "vfscaleb.d", + "vfcvt.h_s", + "vfcvt.s_d", + "vffint.s_l", + "vftint.w_d", + "vftintrm.w_d", + "vftintrp.w_d", + "vftintrz.w_d", + "vftintrne.w_d", + "vhadd4.h_bu", + "vshuf4.w", + "vshuf2.d", + "aes128.enc", + "aes128.dec", + "aes192.enc", + "aes192.dec", + "aes256.enc", + "aes256.dec", + "aes.kg", + "aes.fr_enc", + "aes.fr_dec", + "aes.lr_enc", + "aes.lr_dec", + "aes.mc_enc", + "aes.mc_dec", + "aes.sb_enc", + "aes.sb_dec", + "aes.sr_enc", + "aes.sr_dec", + "md5.ms", + "md5.4r", + "sha1.ms_1", + "sha1.ms_2", + "sha1.hash_4r", + "sha256.ms_1", + "sha256.ms_2", + "sha256.hash_2r", + "sha512.ms_1", + "sha512.ms_2", + "sha512.hash_r_1", + "sha512.hash_r_2", + "vpmul.w", + "vpmul.d", + "vpmuh.w", + "vpmuh.d", + "vpmulacc.w", + "vpmulacc.d", + "vpmuhacc.w", + "vpmuhacc.d", + "vpmulwl.h_b", + "vpmulwl.w_h", + "vpmulwl.d_w", + "vpmulwl.q_d", + "vpmulwh.h_b", + "vpmulwh.w_h", + "vpmulwh.d_w", + "vpmulwh.q_d", + "vpmaddwl.h_b", + "vpmaddwl.w_h", + "vpmaddwl.d_w", + "vpmaddwl.q_d", + "vpmaddwh.h_b", + "vpmaddwh.w_h", + "vpmaddwh.d_w", + "vpmaddwh.q_d", + "vpdp2.q_d", + "vpdp2add.q_d", + "vcdp4.re_d_h", + "vcdp4.im_d_h", + "vcdp4add.re_d_h", + "vcdp4add.im_d_h", + "vcdp2.re_q_w", + "vcdp2.im_q_w", + "vcdp2add.re_q_w", + "vcdp2add.im_q_w", + "vsignsel.w", + "vsignsel.d", + "vshuf.h", + "vshuf.w", + "vshuf.d", + "vseqi.b", + "vseqi.h", + "vseqi.w", + "vseqi.d", + "vslei.b", + "vslei.h", + "vslei.w", + "vslei.d", + "vslei.bu", + "vslei.hu", + "vslei.wu", + "vslei.du", + "vslti.b", + "vslti.h", + "vslti.w", + "vslti.d", + "vslti.bu", + "vslti.hu", + "vslti.wu", + "vslti.du", + "vaddi.bu", + "vaddi.hu", + "vaddi.wu", + "vaddi.du", + "vsubi.bu", + "vsubi.hu", + "vsubi.wu", + "vsubi.du", + "vbsll.v", + "vbsrl.v", + "vmaxi.b", + "vmaxi.h", + "vmaxi.w", + "vmaxi.d", + "vmini.b", + "vmini.h", + "vmini.w", + "vmini.d", + "vmaxi.bu", + "vmaxi.hu", + "vmaxi.wu", + "vmaxi.du", + "vmini.bu", + "vmini.hu", + "vmini.wu", + "vmini.du", + "vrandsigni.b", + "vrandsigni.h", + "vrorsigni.b", + "vrorsigni.h", + "vfrstpi.b", + "vfrstpi.h", + "vclrstri.v", + "vmepatmsk.v", + "vclo.b", + "vclo.h", + "vclo.w", + "vclo.d", + "vclz.b", + "vclz.h", + "vclz.w", + "vclz.d", + "vpcnt.b", + "vpcnt.h", + "vpcnt.w", + "vpcnt.d", + "vneg.b", + "vneg.h", + "vneg.w", + "vneg.d", + "vmskltz.b", + "vmskltz.h", + "vmskltz.w", + "vmskltz.d", + "vmskgez.b", + "vmsknz.b", + "vmskcopy.b", + "vmskfill.b", + "vfrstm.b", + "vfrstm.h", + "vseteqz.v", + "vsetnez.v", + "vsetanyeqz.b", + "vsetanyeqz.h", + "vsetanyeqz.w", + "vsetanyeqz.d", + "vsetallnez.b", + "vsetallnez.h", + "vsetallnez.w", + "vsetallnez.d", + "vflogb.s", + "vflogb.d", + "vfclass.s", + "vfclass.d", + "vfsqrt.s", + "vfsqrt.d", + "vfrecip.s", + "vfrecip.d", + "vfrsqrt.s", + "vfrsqrt.d", + "vfrint.s", + "vfrint.d", + "vfrintrm.s", + "vfrintrm.d", + "vfrintrp.s", + "vfrintrp.d", + "vfrintrz.s", + "vfrintrz.d", + "vfrintrne.s", + "vfrintrne.d", + "vextl.w_b", + "vextl.d_b", + "vextl.d_h", + "vextl.w_bu", + "vextl.d_bu", + "vextl.d_hu", + "vhadd8.d_bu", + "vhminpos.w_hu", + "vhminpos.d_hu", + "vhminpos.q_hu", + "vclrtail.b", + "vclrtail.h", + "vfcvtl.s_h", + "vfcvth.s_h", + "vfcvtl.d_s", + "vfcvth.d_s", + "vffint.s_w", + "vffint.s_wu", + "vffint.d_l", + "vffint.d_lu", + "vffintl.d_w", + "vffinth.d_w", + "vftint.w_s", + "vftint.l_d", + "vftintrm.w_s", + "vftintrm.l_d", + "vftintrp.w_s", + "vftintrp.l_d", + "vftintrz.w_s", + "vftintrz.l_d", + "vftintrne.w_s", + "vftintrne.l_d", + "vftint.wu_s", + "vftint.lu_d", + "vftintrz.wu_s", + "vftintrz.lu_d", + "vftintl.l_s", + "vftinth.l_s", + "vftintrml.l_s", + "vftintrmh.l_s", + "vftintrpl.l_s", + "vftintrph.l_s", + "vftintrzl.l_s", + "vftintrzh.l_s", + "vftintrnel.l_s", + "vftintrneh.l_s", + "vexth.h_b", + "vexth.w_h", + "vexth.d_w", + "vexth.q_d", + "vexth.hu_bu", + "vexth.wu_hu", + "vexth.du_wu", + "vexth.qu_du", + "vreplgr2vr.b", + "vreplgr2vr.h", + "vreplgr2vr.w", + "vreplgr2vr.d", + "vrotri.b", + "vrotri.h", + "vrotri.w", + "vrotri.d", + "vsrlri.b", + "vsrlri.h", + "vsrlri.w", + "vsrlri.d", + "vsrari.b", + "vsrari.h", + "vsrari.w", + "vsrari.d", + "vinsgr2vr.b", + "vinsgr2vr.h", + "vinsgr2vr.w", + "vinsgr2vr.d", + "vpickve2gr.b", + "vpickve2gr.h", + "vpickve2gr.w", + "vpickve2gr.d", + "vpickve2gr.bu", + "vpickve2gr.hu", + "vpickve2gr.wu", + "vpickve2gr.du", + "vreplvei.b", + "vreplvei.h", + "vreplvei.w", + "vreplvei.d", + "vextrcoli.b", + "vextrcoli.h", + "vextrcoli.w", + "vextrcoli.d", + "vsllwil.h_b", + "vsllwil.w_h", + "vsllwil.d_w", + "vextl.q_d", + "vsllwil.hu_bu", + "vsllwil.wu_hu", + "vsllwil.du_wu", + "vextl.qu_du", + "vbitclri.b", + "vbitclri.h", + "vbitclri.w", + "vbitclri.d", + "vbitseti.b", + "vbitseti.h", + "vbitseti.w", + "vbitseti.d", + "vbitrevi.b", + "vbitrevi.h", + "vbitrevi.w", + "vbitrevi.d", + "vbstrc12i.b", + "vbstrc12i.h", + "vbstrc12i.w", + "vbstrc12i.d", + "vbstrc21i.b", + "vbstrc21i.h", + "vbstrc21i.w", + "vbstrc21i.d", + "vsat.b", + "vsat.h", + "vsat.w", + "vsat.d", + "vsat.bu", + "vsat.hu", + "vsat.wu", + "vsat.du", + "vslli.b", + "vslli.h", + "vslli.w", + "vslli.d", + "vsrli.b", + "vsrli.h", + "vsrli.w", + "vsrli.d", + "vsrai.b", + "vsrai.h", + "vsrai.w", + "vsrai.d", + "vsrlrneni.b_h", + "vsrlrneni.h_w", + "vsrlrneni.w_d", + "vsrlrneni.d_q", + "vsrarneni.b_h", + "vsrarneni.h_w", + "vsrarneni.w_d", + "vsrarneni.d_q", + "vsrlni.b_h", + "vsrlni.h_w", + "vsrlni.w_d", + "vsrlni.d_q", + "vsrlrni.b_h", + "vsrlrni.h_w", + "vsrlrni.w_d", + "vsrlrni.d_q", + "vssrlni.b_h", + "vssrlni.h_w", + "vssrlni.w_d", + "vssrlni.d_q", + "vssrlni.bu_h", + "vssrlni.hu_w", + "vssrlni.wu_d", + "vssrlni.du_q", + "vssrlrni.b_h", + "vssrlrni.h_w", + "vssrlrni.w_d", + "vssrlrni.d_q", + "vssrlrni.bu_h", + "vssrlrni.hu_w", + "vssrlrni.wu_d", + "vssrlrni.du_q", + "vsrani.b_h", + "vsrani.h_w", + "vsrani.w_d", + "vsrani.d_q", + "vsrarni.b_h", + "vsrarni.h_w", + "vsrarni.w_d", + "vsrarni.d_q", + "vssrani.b_h", + "vssrani.h_w", + "vssrani.w_d", + "vssrani.d_q", + "vssrani.bu_h", + "vssrani.hu_w", + "vssrani.wu_d", + "vssrani.du_q", + "vssrarni.b_h", + "vssrarni.h_w", + "vssrarni.w_d", + "vssrarni.d_q", + "vssrarni.bu_h", + "vssrarni.hu_w", + "vssrarni.wu_d", + "vssrarni.du_q", + "vssrlrneni.b_h", + "vssrlrneni.h_w", + "vssrlrneni.w_d", + "vssrlrneni.d_q", + "vssrlrneni.bu_h", + "vssrlrneni.hu_w", + "vssrlrneni.wu_d", + "vssrlrneni.du_q", + "vssrarneni.b_h", + "vssrarneni.h_w", + "vssrarneni.w_d", + "vssrarneni.d_q", + "vssrarneni.bu_h", + "vssrarneni.hu_w", + "vssrarneni.wu_d", + "vssrarneni.du_q", + "vextrins.d", + "vextrins.w", + "vextrins.h", + "vextrins.b", + "vshuf4i.b", + "vshuf4i.h", + "vshuf4i.w", + "vshuf4i.d", + "vshufi1.b", + "vshufi2.b", + "vshufi3.b", + "vshufi4.b", + "vshufi1.h", + "vshufi2.h", + "vseli.h", + "vseli.w", + "vseli.d", + "vbitseli.b", + "vbitmvzi.b", + "vbitmvnzi.b", + "vandi.b", + "vori.b", + "vxori.b", + "vnori.b", + "vldi", + "vpermi.w", + "xvseq.b", + "xvseq.h", + "xvseq.w", + "xvseq.d", + "xvsle.b", + "xvsle.h", + "xvsle.w", + "xvsle.d", + "xvsle.bu", + "xvsle.hu", + "xvsle.wu", + "xvsle.du", + "xvslt.b", + "xvslt.h", + "xvslt.w", + "xvslt.d", + "xvslt.bu", + "xvslt.hu", + "xvslt.wu", + "xvslt.du", + "xvadd.b", + "xvadd.h", + "xvadd.w", + "xvadd.d", + "xvsub.b", + "xvsub.h", + "xvsub.w", + "xvsub.d", + "xvaddw.h_h_b", + "xvaddw.w_w_h", + "xvaddw.d_d_w", + "xvaddw.h_h_bu", + "xvaddw.w_w_hu", + "xvaddw.d_d_wu", + "xvsubw.h_h_b", + "xvsubw.w_w_h", + "xvsubw.d_d_w", + "xvsubw.h_h_bu", + "xvsubw.w_w_hu", + "xvsubw.d_d_wu", + "xvsaddw.h_h_b", + "xvsaddw.w_w_h", + "xvsaddw.d_d_w", + "xvsaddw.hu_hu_bu", + "xvsaddw.wu_wu_hu", + "xvsaddw.du_du_wu", + "xvssubw.h_h_b", + "xvssubw.w_w_h", + "xvssubw.d_d_w", + "xvssubw.hu_hu_bu", + "xvssubw.wu_wu_hu", + "xvssubw.du_du_wu", + "xvaddwev.h_b", + "xvaddwev.w_h", + "xvaddwev.d_w", + "xvaddwev.q_d", + "xvsubwev.h_b", + "xvsubwev.w_h", + "xvsubwev.d_w", + "xvsubwev.q_d", + "xvaddwod.h_b", + "xvaddwod.w_h", + "xvaddwod.d_w", + "xvaddwod.q_d", + "xvsubwod.h_b", + "xvsubwod.w_h", + "xvsubwod.d_w", + "xvsubwod.q_d", + "xvaddwl.h_b", + "xvaddwl.w_h", + "xvaddwl.d_w", + "xvaddwl.q_d", + "xvsubwl.h_b", + "xvsubwl.w_h", + "xvsubwl.d_w", + "xvsubwl.q_d", + "xvaddwh.h_b", + "xvaddwh.w_h", + "xvaddwh.d_w", + "xvaddwh.q_d", + "xvsubwh.h_b", + "xvsubwh.w_h", + "xvsubwh.d_w", + "xvsubwh.q_d", + "xvaddwev.h_bu", + "xvaddwev.w_hu", + "xvaddwev.d_wu", + "xvaddwev.q_du", + "xvsubwev.h_bu", + "xvsubwev.w_hu", + "xvsubwev.d_wu", + "xvsubwev.q_du", + "xvaddwod.h_bu", + "xvaddwod.w_hu", + "xvaddwod.d_wu", + "xvaddwod.q_du", + "xvsubwod.h_bu", + "xvsubwod.w_hu", + "xvsubwod.d_wu", + "xvsubwod.q_du", + "xvaddwl.h_bu", + "xvaddwl.w_hu", + "xvaddwl.d_wu", + "xvaddwl.q_du", + "xvsubwl.h_bu", + "xvsubwl.w_hu", + "xvsubwl.d_wu", + "xvsubwl.q_du", + "xvaddwh.h_bu", + "xvaddwh.w_hu", + "xvaddwh.d_wu", + "xvaddwh.q_du", + "xvsubwh.h_bu", + "xvsubwh.w_hu", + "xvsubwh.d_wu", + "xvsubwh.q_du", + "xvaddwev.h_bu_b", + "xvaddwev.w_hu_h", + "xvaddwev.d_wu_w", + "xvaddwev.q_du_d", + "xvaddwod.h_bu_b", + "xvaddwod.w_hu_h", + "xvaddwod.d_wu_w", + "xvaddwod.q_du_d", + "xvaddwl.h_bu_b", + "xvaddwl.w_hu_h", + "xvaddwl.d_wu_w", + "xvaddwl.q_du_d", + "xvaddwh.h_bu_b", + "xvaddwh.w_hu_h", + "xvaddwh.d_wu_w", + "xvaddwh.q_du_d", + "xvsadd.b", + "xvsadd.h", + "xvsadd.w", + "xvsadd.d", + "xvssub.b", + "xvssub.h", + "xvssub.w", + "xvssub.d", + "xvsadd.bu", + "xvsadd.hu", + "xvsadd.wu", + "xvsadd.du", + "xvssub.bu", + "xvssub.hu", + "xvssub.wu", + "xvssub.du", + "xvssub.bu_bu_b", + "xvssub.hu_hu_h", + "xvssub.wu_wu_w", + "xvssub.du_du_d", + "xvssub.bu_b_bu", + "xvssub.hu_h_hu", + "xvssub.wu_w_wu", + "xvssub.du_d_du", + "xvssub.b_bu_bu", + "xvssub.h_hu_hu", + "xvssub.w_wu_wu", + "xvssub.d_du_du", + "xvhaddw.h_b", + "xvhaddw.w_h", + "xvhaddw.d_w", + "xvhaddw.q_d", + "xvhsubw.h_b", + "xvhsubw.w_h", + "xvhsubw.d_w", + "xvhsubw.q_d", + "xvhaddw.hu_bu", + "xvhaddw.wu_hu", + "xvhaddw.du_wu", + "xvhaddw.qu_du", + "xvhsubw.hu_bu", + "xvhsubw.wu_hu", + "xvhsubw.du_wu", + "xvhsubw.qu_du", + "xvadda.b", + "xvadda.h", + "xvadda.w", + "xvadda.d", + "xvsadda.b", + "xvsadda.h", + "xvsadda.w", + "xvsadda.d", + "xvabsd.b", + "xvabsd.h", + "xvabsd.w", + "xvabsd.d", + "xvabsd.bu", + "xvabsd.hu", + "xvabsd.wu", + "xvabsd.du", + "xvavg.b", + "xvavg.h", + "xvavg.w", + "xvavg.d", + "xvavg.bu", + "xvavg.hu", + "xvavg.wu", + "xvavg.du", + "xvavgr.b", + "xvavgr.h", + "xvavgr.w", + "xvavgr.d", + "xvavgr.bu", + "xvavgr.hu", + "xvavgr.wu", + "xvavgr.du", + "xvhalfd.b", + "xvhalfd.h", + "xvhalfd.w", + "xvhalfd.d", + "xvhalfd.bu", + "xvhalfd.hu", + "xvhalfd.wu", + "xvhalfd.du", + "xvmax.b", + "xvmax.h", + "xvmax.w", + "xvmax.d", + "xvmin.b", + "xvmin.h", + "xvmin.w", + "xvmin.d", + "xvmax.bu", + "xvmax.hu", + "xvmax.wu", + "xvmax.du", + "xvmin.bu", + "xvmin.hu", + "xvmin.wu", + "xvmin.du", + "xvmaxa.b", + "xvmaxa.h", + "xvmaxa.w", + "xvmaxa.d", + "xvmina.b", + "xvmina.h", + "xvmina.w", + "xvmina.d", + "xvsadw.h_b", + "xvsadw.w_h", + "xvsadw.d_w", + "xvsadw.h_bu", + "xvsadw.w_hu", + "xvsadw.d_wu", + "xvaccsadw.h_b", + "xvaccsadw.w_h", + "xvaccsadw.d_w", + "xvaccsadw.h_bu", + "xvaccsadw.w_hu", + "xvaccsadw.d_wu", + "xvmul.b", + "xvmul.h", + "xvmul.w", + "xvmul.d", + "xvmuh.b", + "xvmuh.h", + "xvmuh.w", + "xvmuh.d", + "xvmuh.bu", + "xvmuh.hu", + "xvmuh.wu", + "xvmuh.du", + "xvmuh.bu_b", + "xvmuh.hu_h", + "xvmuh.wu_w", + "xvmuh.du_d", + "xvmulxw.h_b", + "xvmulxw.w_h", + "xvmulxw.d_w", + "xvmulxw.h_bu", + "xvmulxw.w_hu", + "xvmulxw.d_wu", + "xvmulwev.h_b", + "xvmulwev.w_h", + "xvmulwev.d_w", + "xvmulwev.q_d", + "xvmulwod.h_b", + "xvmulwod.w_h", + "xvmulwod.d_w", + "xvmulwod.q_d", + "xvmulwl.h_b", + "xvmulwl.w_h", + "xvmulwl.d_w", + "xvmulwl.q_d", + "xvmulwh.h_b", + "xvmulwh.w_h", + "xvmulwh.d_w", + "xvmulwh.q_d", + "xvmulwev.h_bu", + "xvmulwev.w_hu", + "xvmulwev.d_wu", + "xvmulwev.q_du", + "xvmulwod.h_bu", + "xvmulwod.w_hu", + "xvmulwod.d_wu", + "xvmulwod.q_du", + "xvmulwl.h_bu", + "xvmulwl.w_hu", + "xvmulwl.d_wu", + "xvmulwl.q_du", + "xvmulwh.h_bu", + "xvmulwh.w_hu", + "xvmulwh.d_wu", + "xvmulwh.q_du", + "xvmulwev.h_bu_b", + "xvmulwev.w_hu_h", + "xvmulwev.d_wu_w", + "xvmulwev.q_du_d", + "xvmulwod.h_bu_b", + "xvmulwod.w_hu_h", + "xvmulwod.d_wu_w", + "xvmulwod.q_du_d", + "xvmulwl.h_bu_b", + "xvmulwl.w_hu_h", + "xvmulwl.d_wu_w", + "xvmulwl.q_du_d", + "xvmulwh.h_bu_b", + "xvmulwh.w_hu_h", + "xvmulwh.d_wu_w", + "xvmulwh.q_du_d", + "xvmadd.b", + "xvmadd.h", + "xvmadd.w", + "xvmadd.d", + "xvmsub.b", + "xvmsub.h", + "xvmsub.w", + "xvmsub.d", + "xvmaddwev.h_b", + "xvmaddwev.w_h", + "xvmaddwev.d_w", + "xvmaddwev.q_d", + "xvmaddwod.h_b", + "xvmaddwod.w_h", + "xvmaddwod.d_w", + "xvmaddwod.q_d", + "xvmaddwl.h_b", + "xvmaddwl.w_h", + "xvmaddwl.d_w", + "xvmaddwl.q_d", + "xvmaddwh.h_b", + "xvmaddwh.w_h", + "xvmaddwh.d_w", + "xvmaddwh.q_d", + "xvmaddwev.h_bu", + "xvmaddwev.w_hu", + "xvmaddwev.d_wu", + "xvmaddwev.q_du", + "xvmaddwod.h_bu", + "xvmaddwod.w_hu", + "xvmaddwod.d_wu", + "xvmaddwod.q_du", + "xvmaddwl.h_bu", + "xvmaddwl.w_hu", + "xvmaddwl.d_wu", + "xvmaddwl.q_du", + "xvmaddwh.h_bu", + "xvmaddwh.w_hu", + "xvmaddwh.d_wu", + "xvmaddwh.q_du", + "xvmaddwev.h_bu_b", + "xvmaddwev.w_hu_h", + "xvmaddwev.d_wu_w", + "xvmaddwev.q_du_d", + "xvmaddwod.h_bu_b", + "xvmaddwod.w_hu_h", + "xvmaddwod.d_wu_w", + "xvmaddwod.q_du_d", + "xvmaddwl.h_bu_b", + "xvmaddwl.w_hu_h", + "xvmaddwl.d_wu_w", + "xvmaddwl.q_du_d", + "xvmaddwh.h_bu_b", + "xvmaddwh.w_hu_h", + "xvmaddwh.d_wu_w", + "xvmaddwh.q_du_d", + "xvdp2.h_b", + "xvdp2.w_h", + "xvdp2.d_w", + "xvdp2.q_d", + "xvdp2.hu_bu", + "xvdp2.wu_hu", + "xvdp2.du_wu", + "xvdp2.qu_du", + "xvdp2.h_bu_b", + "xvdp2.w_hu_h", + "xvdp2.d_wu_w", + "xvdp2.q_du_d", + "xvdp2add.h_b", + "xvdp2add.w_h", + "xvdp2add.d_w", + "xvdp2add.q_d", + "xvdp2add.h_bu", + "xvdp2add.w_hu", + "xvdp2add.d_wu", + "xvdp2add.q_du", + "xvdp2add.h_bu_b", + "xvdp2add.w_hu_h", + "xvdp2add.d_wu_w", + "xvdp2add.q_du_d", + "xvdp2sub.h_b", + "xvdp2sub.w_h", + "xvdp2sub.d_w", + "xvdp2sub.q_d", + "xvdp2sub.h_bu", + "xvdp2sub.w_hu", + "xvdp2sub.d_wu", + "xvdp2sub.q_du", + "xvdp4.w_b", + "xvdp4.d_h", + "xvdp4.q_w", + "xvdp4.w_bu", + "xvdp4.d_hu", + "xvdp4.q_wu", + "xvdp4.w_bu_b", + "xvdp4.d_hu_h", + "xvdp4.q_wu_w", + "xvdp4add.w_b", + "xvdp4add.d_h", + "xvdp4add.q_w", + "xvdp4add.w_bu", + "xvdp4add.d_hu", + "xvdp4add.q_wu", + "xvdp4add.w_bu_b", + "xvdp4add.d_hu_h", + "xvdp4add.q_wu_w", + "xvdiv.b", + "xvdiv.h", + "xvdiv.w", + "xvdiv.d", + "xvmod.b", + "xvmod.h", + "xvmod.w", + "xvmod.d", + "xvdiv.bu", + "xvdiv.hu", + "xvdiv.wu", + "xvdiv.du", + "xvmod.bu", + "xvmod.hu", + "xvmod.wu", + "xvmod.du", + "xvsll.b", + "xvsll.h", + "xvsll.w", + "xvsll.d", + "xvsrl.b", + "xvsrl.h", + "xvsrl.w", + "xvsrl.d", + "xvsra.b", + "xvsra.h", + "xvsra.w", + "xvsra.d", + "xvrotr.b", + "xvrotr.h", + "xvrotr.w", + "xvrotr.d", + "xvsrlr.b", + "xvsrlr.h", + "xvsrlr.w", + "xvsrlr.d", + "xvsrar.b", + "xvsrar.h", + "xvsrar.w", + "xvsrar.d", + "xvsrln.b_h", + "xvsrln.h_w", + "xvsrln.w_d", + "xvsran.b_h", + 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"xvfmina.d", + "xvfscaleb.s", + "xvfscaleb.d", + "xvfcvt.h_s", + "xvfcvt.s_d", + "xvffint.s_l", + "xvftint.w_d", + "xvftintrm.w_d", + "xvftintrp.w_d", + "xvftintrz.w_d", + "xvftintrne.w_d", + "xvhadd4.h_bu", + "xvshuf4.w", + "xvshuf2.d", + "xvpmul.w", + "xvpmul.d", + "xvpmuh.w", + "xvpmuh.d", + "xvpmulacc.w", + "xvpmulacc.d", + "xvpmuhacc.w", + "xvpmuhacc.d", + "xvpmulwl.h_b", + "xvpmulwl.w_h", + "xvpmulwl.d_w", + "xvpmulwl.q_d", + "xvpmulwh.h_b", + "xvpmulwh.w_h", + "xvpmulwh.d_w", + "xvpmulwh.q_d", + "xvpmaddwl.h_b", + "xvpmaddwl.w_h", + "xvpmaddwl.d_w", + "xvpmaddwl.q_d", + "xvpmaddwh.h_b", + "xvpmaddwh.w_h", + "xvpmaddwh.d_w", + "xvpmaddwh.q_d", + "xvpdp2.q_d", + "xvpdp2add.q_d", + "xvcdp4.re_d_h", + "xvcdp4.im_d_h", + "xvcdp4add.re_d_h", + "xvcdp4add.im_d_h", + "xvcdp2.re_q_w", + "xvcdp2.im_q_w", + "xvcdp2add.re_q_w", + "xvcdp2add.im_q_w", + "xvsignsel.w", + "xvsignsel.d", + "xvshuf.h", + "xvshuf.w", + "xvshuf.d", + "xvperm.w", + "xvseqi.b", + "xvseqi.h", + "xvseqi.w", + "xvseqi.d", + "xvslei.b", + "xvslei.h", + "xvslei.w", + "xvslei.d", + "xvslei.bu", + "xvslei.hu", + "xvslei.wu", + "xvslei.du", + "xvslti.b", + "xvslti.h", + "xvslti.w", + "xvslti.d", + "xvslti.bu", + "xvslti.hu", + "xvslti.wu", + "xvslti.du", + "xvaddi.bu", + "xvaddi.hu", + "xvaddi.wu", + "xvaddi.du", + "xvsubi.bu", + "xvsubi.hu", + "xvsubi.wu", + "xvsubi.du", + "xvbsll.v", + "xvbsrl.v", + "xvmaxi.b", + "xvmaxi.h", + "xvmaxi.w", + "xvmaxi.d", + "xvmini.b", + "xvmini.h", + "xvmini.w", + "xvmini.d", + "xvmaxi.bu", + "xvmaxi.hu", + "xvmaxi.wu", + "xvmaxi.du", + "xvmini.bu", + "xvmini.hu", + "xvmini.wu", + "xvmini.du", + "xvrandsigni.b", + "xvrandsigni.h", + "xvrorsigni.b", + "xvrorsigni.h", + "xvfrstpi.b", + "xvfrstpi.h", + "xvclrstri.v", + "xvmepatmsk.v", + "xvclo.b", + "xvclo.h", + "xvclo.w", + "xvclo.d", + "xvclz.b", + "xvclz.h", + "xvclz.w", + "xvclz.d", + "xvpcnt.b", + "xvpcnt.h", + "xvpcnt.w", + "xvpcnt.d", + "xvneg.b", + "xvneg.h", + "xvneg.w", + "xvneg.d", + "xvmskltz.b", + "xvmskltz.h", + "xvmskltz.w", + "xvmskltz.d", + "xvmskgez.b", + "xvmsknz.b", + "xvmskcopy.b", + "xvmskfill.b", + "xvfrstm.b", + "xvfrstm.h", + "xvseteqz.v", + "xvsetnez.v", + "xvsetanyeqz.b", + "xvsetanyeqz.h", + "xvsetanyeqz.w", + "xvsetanyeqz.d", + "xvsetallnez.b", + "xvsetallnez.h", + "xvsetallnez.w", + "xvsetallnez.d", + "xvflogb.s", + "xvflogb.d", + "xvfclass.s", + "xvfclass.d", + "xvfsqrt.s", + "xvfsqrt.d", + "xvfrecip.s", + "xvfrecip.d", + "xvfrsqrt.s", + "xvfrsqrt.d", + "xvfrint.s", + "xvfrint.d", + "xvfrintrm.s", + "xvfrintrm.d", + "xvfrintrp.s", + "xvfrintrp.d", + "xvfrintrz.s", + "xvfrintrz.d", + "xvfrintrne.s", + "xvfrintrne.d", + "xvextl.w_b", + "xvextl.d_b", + "xvextl.d_h", + "xvextl.w_bu", + "xvextl.d_bu", + "xvextl.d_hu", + "xvhadd8.d_bu", + "xvhminpos.w_hu", + "xvhminpos.d_hu", + "xvhminpos.q_hu", + "xvclrtail.b", + "xvclrtail.h", + "xvfcvtl.s_h", + "xvfcvth.s_h", + "xvfcvtl.d_s", + "xvfcvth.d_s", + "xvffint.s_w", + "xvffint.s_wu", + "xvffint.d_l", + "xvffint.d_lu", + "xvffintl.d_w", + "xvffinth.d_w", + "xvftint.w_s", + "xvftint.l_d", + "xvftintrm.w_s", + "xvftintrm.l_d", + "xvftintrp.w_s", + "xvftintrp.l_d", + "xvftintrz.w_s", + "xvftintrz.l_d", + "xvftintrne.w_s", + "xvftintrne.l_d", + "xvftint.wu_s", + "xvftint.lu_d", + "xvftintrz.wu_s", + "xvftintrz.lu_d", + "xvftintl.l_s", + "xvftinth.l_s", + "xvftintrml.l_s", + "xvftintrmh.l_s", + "xvftintrpl.l_s", + "xvftintrph.l_s", + "xvftintrzl.l_s", + "xvftintrzh.l_s", + "xvftintrnel.l_s", + "xvftintrneh.l_s", + "xvexth.h_b", + "xvexth.w_h", + "xvexth.d_w", + "xvexth.q_d", + "xvexth.hu_bu", + "xvexth.wu_hu", + "xvexth.du_wu", + "xvexth.qu_du", + "xvreplgr2vr.b", + "xvreplgr2vr.h", + "xvreplgr2vr.w", + "xvreplgr2vr.d", + "vext2xv.h_b", + "vext2xv.w_b", + "vext2xv.d_b", + "vext2xv.w_h", + "vext2xv.d_h", + "vext2xv.d_w", + "vext2xv.hu_bu", + "vext2xv.wu_bu", + "vext2xv.du_bu", + "vext2xv.wu_hu", + "vext2xv.du_hu", + "vext2xv.du_wu", + "xvhseli.d", + "xvrotri.b", + "xvrotri.h", + "xvrotri.w", + "xvrotri.d", + "xvsrlri.b", + "xvsrlri.h", + "xvsrlri.w", + "xvsrlri.d", + "xvsrari.b", + "xvsrari.h", + "xvsrari.w", + "xvsrari.d", + "xvinsgr2vr.w", + "xvinsgr2vr.d", + "xvpickve2gr.w", + "xvpickve2gr.d", + "xvpickve2gr.wu", + "xvpickve2gr.du", + "xvrepl128vei.b", + "xvrepl128vei.h", + "xvrepl128vei.w", + "xvrepl128vei.d", + "xvextrcoli.b", + "xvextrcoli.h", + "xvextrcoli.w", + "xvextrcoli.d", + "xvinsve0.w", + "xvinsve0.d", + "xvpickve.w", + "xvpickve.d", + "xvreplve0.b", + "xvreplve0.h", + "xvreplve0.w", + "xvreplve0.d", + "xvreplve0.q", + "xvsllwil.h_b", + "xvsllwil.w_h", + "xvsllwil.d_w", + "xvextl.q_d", + "xvsllwil.hu_bu", + "xvsllwil.wu_hu", + "xvsllwil.du_wu", + "xvextl.qu_du", + "xvbitclri.b", + "xvbitclri.h", + "xvbitclri.w", + "xvbitclri.d", + "xvbitseti.b", + "xvbitseti.h", + "xvbitseti.w", + "xvbitseti.d", + "xvbitrevi.b", + "xvbitrevi.h", + "xvbitrevi.w", + "xvbitrevi.d", + "xvbstrc12i.b", + "xvbstrc12i.h", + "xvbstrc12i.w", + "xvbstrc12i.d", + "xvbstrc21i.b", + "xvbstrc21i.h", + "xvbstrc21i.w", + "xvbstrc21i.d", + "xvsat.b", + "xvsat.h", + "xvsat.w", + "xvsat.d", + "xvsat.bu", + "xvsat.hu", + "xvsat.wu", + "xvsat.du", + "xvslli.b", + "xvslli.h", + "xvslli.w", + "xvslli.d", + "xvsrli.b", + "xvsrli.h", + "xvsrli.w", + "xvsrli.d", + "xvsrai.b", + "xvsrai.h", + "xvsrai.w", + "xvsrai.d", + "xvsrlrneni.b_h", + "xvsrlrneni.h_w", + "xvsrlrneni.w_d", + "xvsrlrneni.d_q", + "xvsrarneni.b_h", + "xvsrarneni.h_w", + "xvsrarneni.w_d", + "xvsrarneni.d_q", + "xvsrlni.b_h", + "xvsrlni.h_w", + "xvsrlni.w_d", + "xvsrlni.d_q", + "xvsrlrni.b_h", + "xvsrlrni.h_w", + "xvsrlrni.w_d", + "xvsrlrni.d_q", + "xvssrlni.b_h", + "xvssrlni.h_w", + "xvssrlni.w_d", + "xvssrlni.d_q", + "xvssrlni.bu_h", + "xvssrlni.hu_w", + "xvssrlni.wu_d", + "xvssrlni.du_q", + "xvssrlrni.b_h", + "xvssrlrni.h_w", + "xvssrlrni.w_d", + "xvssrlrni.d_q", + "xvssrlrni.bu_h", + "xvssrlrni.hu_w", + "xvssrlrni.wu_d", + "xvssrlrni.du_q", + "xvsrani.b_h", + "xvsrani.h_w", + "xvsrani.w_d", + "xvsrani.d_q", + "xvsrarni.b_h", + "xvsrarni.h_w", + "xvsrarni.w_d", + "xvsrarni.d_q", + "xvssrani.b_h", + "xvssrani.h_w", + "xvssrani.w_d", + "xvssrani.d_q", + "xvssrani.bu_h", + "xvssrani.hu_w", + "xvssrani.wu_d", + "xvssrani.du_q", + "xvssrarni.b_h", + "xvssrarni.h_w", + "xvssrarni.w_d", + "xvssrarni.d_q", + "xvssrarni.bu_h", + "xvssrarni.hu_w", + "xvssrarni.wu_d", + "xvssrarni.du_q", + "xvssrlrneni.b_h", + "xvssrlrneni.h_w", + "xvssrlrneni.w_d", + "xvssrlrneni.d_q", + "xvssrlrneni.bu_h", + "xvssrlrneni.hu_w", + "xvssrlrneni.wu_d", + "xvssrlrneni.du_q", + "xvssrarneni.b_h", + "xvssrarneni.h_w", + "xvssrarneni.w_d", + "xvssrarneni.d_q", + "xvssrarneni.bu_h", + "xvssrarneni.hu_w", + "xvssrarneni.wu_d", + "xvssrarneni.du_q", + "xvextrins.d", + "xvextrins.w", + "xvextrins.h", + "xvextrins.b", + "xvshuf4i.b", + "xvshuf4i.h", + "xvshuf4i.w", + "xvshuf4i.d", + "xvshufi1.b", + "xvshufi2.b", + "xvshufi3.b", + "xvshufi4.b", + "xvshufi1.h", + "xvshufi2.h", + "xvseli.h", + "xvseli.w", + "xvseli.d", + "xvbitseli.b", + "xvbitmvzi.b", + "xvbitmvnzi.b", + "xvandi.b", + "xvori.b", + "xvxori.b", + "xvnori.b", + "xvldi", + "xvpermi.w", + "xvpermi.d", + "xvpermi.q", + "ENDING", +}; + +static const char *ir2_gpr_name[] = { + "$zero" , "$ra" , "$tp" , "$sp" , "$a0" , "$a1" , "$a2" , "$a3" , + "$a4" , "$a5" , "$a6" , "$a7" , "$t0" , "$t1" , "$t2" , "$t3" , + "$t4" , "$t5" , "$t6" , "$t7" , "$t8" , "$x" , "$fp" , "$s0" , + "$s1" , "$s2" , "$s3" , "$s4" , "$s5" , "$s6" , "$s7" , "$s8" , +}; + +static const char *ir2_fpr_name[] = { + "$fa0" , "$fa1" , "$fa2" , "$fa3" , + "$fa4" , "$fa5" , "$fa6" , "$fa7" , + "$ft0" , "$ft1" , "$ft2" , "$ft3" , + "$ft4" , "$ft5" , "$ft6" , "$ft7" , + "$ft8" , "$ft9" , "$ft10" , "$ft11" , + "$ft12" , "$ft13" , "$ft14" , "$ft15" , + "$fs0" , "$fs1" , "$fs2" , "$fs3" , + "$fs4" , "$fs5" , "$fs6" , "$s7" , +}; + +static const char *ir2_scr_name[] = { + "$scr0" , "$scr1" , "$scr2" , "$scr3", +}; + +static const char *ir2_cc_name[] = { + "$cc0" , "$cc1" , "$cc2" , "$cc3" , + "$cc4" , "$cc5" , "$cc6" , "$cc7" , +}; + +LA_OPND_TYPE get_opnd_type(Ins *ins, int i) +{ + GM_LA_OPCODE_FORMAT format = lisa_format_table[ins->op]; + GM_OPERAND_TYPE la_opnd_type = format.opnd[i]; + IR2_OPND_TYPE ir2_opnd_type = ir2_opnd_type_table[la_opnd_type]; + return ir2_opnd_type; +} + +int extract_opnd_val(uint32_t insn, GM_OPERAND_TYPE type) +{ + GM_OPERAND_PLACE_RELATION bit_field = bit_field_table[type]; + int bit_start = bit_field.bit_range_0.start; + int bit_end = bit_field.bit_range_0.end; + int bit_len = bit_end - bit_start + 1; + int val = (insn >> bit_start) & ((1 << bit_len) - 1); + + bit_start = bit_field.bit_range_1.start; + bit_end = bit_field.bit_range_1.end; + if (bit_start >= 0 && bit_end >= 0) { + int field1_val = insn << (31 - bit_end) >> (31 - bit_end + bit_start); + val |= field1_val << bit_len; + } + + if (is_la_sign_opnd[type]) { + if (bit_end >= 0) { + bit_len += bit_field.bit_range_1.end - bit_field.bit_range_1.start + 1; + } + val = val << (32 - bit_len) >> (32 - bit_len); + } + + return val; +} + +void la_disasm(uint32_t opcode, Ins *ins) +{ + LA_OPCODE op = get_ins_op(opcode); + assert(op != LISA_INVALID); + + ins->op = op; + ins->opnd_count = 0; + + GM_LA_OPCODE_FORMAT format = lisa_format_table[op]; + + for (int i = 0; i < 4; i++) { + GM_OPERAND_TYPE opnd_type = format.opnd[i]; + if (opnd_type == OPD_INVALID) { + break; + } + + ins->opnd[i].val = extract_opnd_val(opcode, opnd_type); + ins->opnd_count++; + } +} + +const char *ins_name(Ins *ins) +{ + LA_OPCODE op = ins->op; + if (op == LISA_INVALID || op >= LISA_ENDING) { + return "invalid ins"; + } + return ir2_ins_name[op]; +} + +const char *gpr_name(uint32_t gpr) +{ + if (gpr >= 32) + return "invalid gpr"; + return ir2_gpr_name[gpr]; +} + +void sprint_op(LA_OPCODE op, char *msg) { + sprintf(msg, "%-15s\t", ir2_ins_name[op]); +} + +void sprint_ins(Ins *ins, char * msg) { + assert(ins->op >= LISA_INVALID && ins->op <= LISA_ENDING); + sprintf(msg, "%-15s\t", ir2_ins_name[ins->op]); + for (int i = 0; i < ins->opnd_count; i++) { + if (i != 0) + sprintf(msg + strlen(msg),", "); + + IR2_OPND_TYPE type = get_opnd_type(ins, i); + switch (type) { + case IR2_OPND_GPR: + sprintf(msg + strlen(msg),"%s", ir2_gpr_name[ins->opnd[i].val]); + break; + case IR2_OPND_FPR: + sprintf(msg + strlen(msg),"%s", ir2_fpr_name[ins->opnd[i].val]); + break; + case IR2_OPND_FCSR: + sprintf(msg + strlen(msg),"%d", ins->opnd[i].val); + break; + case IR2_OPND_SCR: + sprintf(msg + strlen(msg),"%s", ir2_scr_name[ins->opnd[i].val]); + break; + case IR2_OPND_CC: + sprintf(msg + strlen(msg),"%s", ir2_cc_name[ins->opnd[i].val]); + break; + case IR2_OPND_LABEL: + break; + case IR2_OPND_IMM: + sprintf(msg + strlen(msg),"0x%x", ins->opnd[i].val); + break; + case IR2_OPND_NONE: + break; + default: + fprintf(stderr, "Error in sprint_ins, unknown opnd\n"); + assert(0); + exit(EXIT_FAILURE); + } + } +} + +void sprint_disasm(uint32_t opcode, char *msg) +{ + Ins ins; + la_disasm(opcode, &ins); + sprint_ins(&ins, msg); +} + +void print_op(LA_OPCODE op) +{ + char msg[32]; + sprint_op(op, msg); + puts(msg); +} + +void print_ins(Ins *ins) +{ + char msg[64]; + sprint_ins(ins, msg); + puts(msg); +} + +void print_disasm(uint32_t opcode) +{ + char msg[64]; + sprint_disasm(opcode, msg); + puts(msg); +} diff --git a/ext/loongarch-disasm.h b/ext/loongarch-disasm.h new file mode 100644 index 0000000000..83d18198b1 --- /dev/null +++ b/ext/loongarch-disasm.h @@ -0,0 +1,2778 @@ +/* + * LoongArch64 Disassembler + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LOONGARCH_DISASSEMBLER_H +#define LOONGARCH_DISASSEMBLER_H + +#include +#include +#include + +/* IR2_OPCODE; */ +typedef enum { + /* LISA_INVALID = 128, */ + LISA_INVALID, + LISA_ILL, + LISA_LABEL, + LISA_X86_INST, + LISA_DUP, + LISA_MOV64, + LISA_MOV32_SX, + LISA_MOV32_ZX, + LISA_CLR_H32, + LISA_ADD, + LISA_SUB, + LISA_ADDI_ADDRX, + LISA_LOAD_ADDRX, + LISA_STORE_ADDRX, + LISA_GR2SCR, + LISA_SCR2GR, + LISA_CLO_W, + LISA_CLZ_W, + LISA_CTO_W, + LISA_CTZ_W, + LISA_CLO_D, + LISA_CLZ_D, + LISA_CTO_D, + LISA_CTZ_D, + LISA_REVB_2H, + LISA_REVB_4H, + LISA_REVB_2W, + LISA_REVB_D, + LISA_REVH_2W, + LISA_REVH_D, + LISA_BITREV_4B, + LISA_BITREV_8B, + LISA_BITREV_W, + LISA_BITREV_D, + LISA_EXT_W_H, + LISA_EXT_W_B, + LISA_RDTIMEL_W, + LISA_RDTIMEH_W, + LISA_RDTIME_D, + LISA_CPUCFG, + LISA_X86MTTOP, + LISA_X86MFTOP, + LISA_X86LOOPE, + LISA_X86LOOPNE, + LISA_X86INC_B, + LISA_X86INC_H, + LISA_X86INC_W, + LISA_X86INC_D, + LISA_X86DEC_B, + LISA_X86DEC_H, + LISA_X86DEC_W, + LISA_X86DEC_D, + LISA_X86SETTM, + LISA_X86CLRTM, + LISA_X86INCTOP, + LISA_X86DECTOP, + LISA_ASRTLE_D, + LISA_ASRTGT_D, + LISA_ALSL_W, + LISA_ALSL_WU, + LISA_BYTEPICK_W, + LISA_BYTEPICK_D, + LISA_ADD_W, + LISA_ADD_D, + LISA_SUB_W, + LISA_SUB_D, + LISA_SLT, + LISA_SLTU, + LISA_MASKEQZ, + LISA_MASKNEZ, + LISA_NOR, + LISA_AND, + LISA_OR, + LISA_XOR, + LISA_ORN, + LISA_ANDN, + LISA_SLL_W, + LISA_SRL_W, + LISA_SRA_W, + LISA_SLL_D, + LISA_SRL_D, + LISA_SRA_D, + LISA_ROTR_B, + LISA_ROTR_H, + LISA_ROTR_W, + LISA_ROTR_D, + LISA_MUL_W, + LISA_MULH_W, + LISA_MULH_WU, + LISA_MUL_D, + LISA_MULH_D, + LISA_MULH_DU, + LISA_MULW_D_W, + LISA_MULW_D_WU, + LISA_DIV_W, + LISA_MOD_W, + LISA_DIV_WU, + LISA_MOD_WU, + LISA_DIV_D, + LISA_MOD_D, + LISA_DIV_DU, + LISA_MOD_DU, + LISA_CRC_W_B_W, + LISA_CRC_W_H_W, + LISA_CRC_W_W_W, + LISA_CRC_W_D_W, + LISA_CRCC_W_B_W, + LISA_CRCC_W_H_W, + LISA_CRCC_W_W_W, + LISA_CRCC_W_D_W, + LISA_ADDU12I_W, + LISA_ADDU12I_D, + LISA_BREAK, + LISA_DBGCALL, + LISA_SYSCALL, + LISA_HYPCALL, + LISA_ALSL_D, + LISA_ADC_B, + LISA_ADC_H, + LISA_ADC_W, + LISA_ADC_D, + LISA_SBC_B, + LISA_SBC_H, + LISA_SBC_W, + LISA_SBC_D, + LISA_RCR_B, + LISA_RCR_H, + LISA_RCR_W, + LISA_RCR_D, + LISA_ARMMOVE, + LISA_SETX86J, + LISA_SETARMJ, + LISA_ARMADD_W, + LISA_ARMSUB_W, + LISA_ARMADC_W, + LISA_ARMSBC_W, + LISA_ARMAND_W, + LISA_ARMOR_W, + LISA_ARMXOR_W, + LISA_ARMSLL_W, + LISA_ARMSRL_W, + LISA_ARMSRA_W, + LISA_ARMROTR_W, + LISA_ARMSLLI_W, + LISA_ARMSRLI_W, + LISA_ARMSRAI_W, + LISA_ARMROTRI_W, + LISA_X86MUL_B, + LISA_X86MUL_H, + LISA_X86MUL_W, + LISA_X86MUL_D, + LISA_X86MUL_BU, + LISA_X86MUL_HU, + LISA_X86MUL_WU, + LISA_X86MUL_DU, + LISA_X86ADD_WU, + LISA_X86ADD_DU, + LISA_X86SUB_WU, + LISA_X86SUB_DU, + LISA_X86ADD_B, + LISA_X86ADD_H, + LISA_X86ADD_W, + LISA_X86ADD_D, + LISA_X86SUB_B, + LISA_X86SUB_H, + LISA_X86SUB_W, + LISA_X86SUB_D, + LISA_X86ADC_B, + LISA_X86ADC_H, + LISA_X86ADC_W, + LISA_X86ADC_D, + LISA_X86SBC_B, + LISA_X86SBC_H, + LISA_X86SBC_W, + LISA_X86SBC_D, + LISA_X86SLL_B, + LISA_X86SLL_H, + LISA_X86SLL_W, + LISA_X86SLL_D, + LISA_X86SRL_B, + LISA_X86SRL_H, + LISA_X86SRL_W, + LISA_X86SRL_D, + LISA_X86SRA_B, + LISA_X86SRA_H, + LISA_X86SRA_W, + LISA_X86SRA_D, + LISA_X86ROTR_B, + LISA_X86ROTR_H, + LISA_X86ROTR_D, + LISA_X86ROTR_W, + LISA_X86ROTL_B, + LISA_X86ROTL_H, + LISA_X86ROTL_W, + LISA_X86ROTL_D, + LISA_X86RCR_B, + LISA_X86RCR_H, + LISA_X86RCR_W, + LISA_X86RCR_D, + LISA_X86RCL_B, + LISA_X86RCL_H, + LISA_X86RCL_W, + LISA_X86RCL_D, + LISA_X86AND_B, + LISA_X86AND_H, + LISA_X86AND_W, + LISA_X86AND_D, + LISA_X86OR_B, + LISA_X86OR_H, + LISA_X86OR_W, + LISA_X86OR_D, + LISA_X86XOR_B, + LISA_X86XOR_H, + LISA_X86XOR_W, + LISA_X86XOR_D, + LISA_ARMNOT_W, + LISA_ARMMOV_W, + LISA_ARMMOV_D, + LISA_ARMRRX_W, + LISA_SLLI_W, + LISA_SLLI_D, + LISA_SRLI_W, + LISA_SRLI_D, + LISA_SRAI_W, + LISA_SRAI_D, + LISA_ROTRI_B, + LISA_ROTRI_H, + LISA_ROTRI_W, + LISA_ROTRI_D, + LISA_RCRI_B, + LISA_RCRI_H, + LISA_RCRI_W, + LISA_RCRI_D, + LISA_X86SLLI_B, + LISA_X86SLLI_H, + LISA_X86SLLI_W, + LISA_X86SLLI_D, + LISA_X86SRLI_B, + LISA_X86SRLI_H, + LISA_X86SRLI_W, + LISA_X86SRLI_D, + LISA_X86SRAI_B, + LISA_X86SRAI_H, + LISA_X86SRAI_W, + LISA_X86SRAI_D, + LISA_X86ROTRI_B, + LISA_X86ROTRI_H, + LISA_X86ROTRI_W, + LISA_X86ROTRI_D, + LISA_X86RCRI_B, + LISA_X86RCRI_H, + LISA_X86RCRI_W, + LISA_X86RCRI_D, + LISA_X86ROTLI_B, + LISA_X86ROTLI_H, + LISA_X86ROTLI_W, + LISA_X86ROTLI_D, + LISA_X86RCLI_B, + LISA_X86RCLI_H, + LISA_X86RCLI_W, + LISA_X86RCLI_D, + LISA_X86SETTAG, + LISA_X86MFFLAG, + LISA_X86MTFLAG, + LISA_ARMMFFLAG, + LISA_ARMMTFLAG, + LISA_BSTRINS_W, + LISA_BSTRPICK_W, + LISA_BSTRINS_D, + LISA_BSTRPICK_D, + LISA_SLTI, + LISA_SLTUI, + LISA_ADDI_W, + LISA_ADDI_D, + LISA_LU52I_D, + LISA_ANDI, + LISA_ORI, + LISA_XORI, + LISA_ADDU16I_D, + LISA_LU12I_W, + LISA_LU32I_D, + LISA_PCADDI, + LISA_PCALAU12I, + LISA_PCADDU12I, + LISA_PCADDU18I, + LISA_LL_W, + LISA_SC_W, + LISA_LL_D, + LISA_SC_D, + LISA_LDPTR_W, + LISA_STPTR_W, + LISA_LDPTR_D, + LISA_STPTR_D, + LISA_LD_B, + LISA_LD_H, + LISA_LD_W, + LISA_LD_D, + LISA_ST_B, + LISA_ST_H, + LISA_ST_W, + LISA_ST_D, + LISA_LD_BU, + LISA_LD_HU, + LISA_LD_WU, + LISA_PRELD, + LISA_FLD_S, + LISA_FST_S, + LISA_FLD_D, + LISA_FST_D, + LISA_VLD, + LISA_VST, + LISA_XVLD, + LISA_XVST, + LISA_LDL_W, + LISA_LDR_W, + LISA_LDL_D, + LISA_LDR_D, + LISA_STL_W, + LISA_STR_W, + LISA_STL_D, + LISA_STR_D, + LISA_VLDREPL_D, + LISA_VLDREPL_W, + LISA_VLDREPL_H, + LISA_VLDREPL_B, + LISA_VSTELM_D, + LISA_VSTELM_W, + LISA_VSTELM_H, + LISA_VSTELM_B, + LISA_XVLDREPL_D, + LISA_XVLDREPL_W, + LISA_XVLDREPL_H, + LISA_XVLDREPL_B, + LISA_XVSTELM_D, + LISA_XVSTELM_W, + LISA_XVSTELM_H, + LISA_XVSTELM_B, + LISA_LDX_B, + LISA_LDX_H, + LISA_LDX_W, + LISA_LDX_D, + LISA_STX_B, + LISA_STX_H, + LISA_STX_W, + LISA_STX_D, + LISA_LDX_BU, + LISA_LDX_HU, + LISA_LDX_WU, + LISA_PRELDX, + LISA_FLDX_S, + LISA_FLDX_D, + LISA_FSTX_S, + LISA_FSTX_D, + LISA_VLDX, + LISA_VSTX, + LISA_XVLDX, + LISA_XVSTX, + LISA_AMSWAP_W, + LISA_AMSWAP_D, + LISA_AMADD_W, + LISA_AMADD_D, + LISA_AMAND_W, + LISA_AMAND_D, + LISA_AMOR_W, + LISA_AMOR_D, + LISA_AMXOR_W, + LISA_AMXOR_D, + LISA_AMMAX_W, + LISA_AMMAX_D, + LISA_AMMIN_W, + LISA_AMMIN_D, + LISA_AMMAX_WU, + LISA_AMMAX_DU, + LISA_AMMIN_WU, + LISA_AMMIN_DU, + LISA_AMSWAP_DB_W, + LISA_AMSWAP_DB_D, + LISA_AMADD_DB_W, + LISA_AMADD_DB_D, + LISA_AMAND_DB_W, + LISA_AMAND_DB_D, + LISA_AMOR_DB_W, + LISA_AMOR_DB_D, + LISA_AMXOR_DB_W, + LISA_AMXOR_DB_D, + LISA_AMMAX_DB_W, + LISA_AMMAX_DB_D, + LISA_AMMIN_DB_W, + LISA_AMMIN_DB_D, + LISA_AMMAX_DB_WU, + LISA_AMMAX_DB_DU, + LISA_AMMIN_DB_WU, + LISA_AMMIN_DB_DU, + LISA_DBAR, + LISA_IBAR, + LISA_FLDGT_S, + LISA_FLDGT_D, + LISA_FLDLE_S, + LISA_FLDLE_D, + LISA_FSTGT_S, + LISA_FSTGT_D, + LISA_FSTLE_S, + LISA_FSTLE_D, + LISA_LDGT_B, + LISA_LDGT_H, + LISA_LDGT_W, + LISA_LDGT_D, + LISA_LDLE_B, + LISA_LDLE_H, + LISA_LDLE_W, + LISA_LDLE_D, + LISA_STGT_B, + LISA_STGT_H, + LISA_STGT_W, + LISA_STGT_D, + LISA_STLE_B, + LISA_STLE_H, + LISA_STLE_W, + LISA_STLE_D, + LISA_BEQZ, + LISA_BNEZ, + LISA_BCEQZ, + LISA_BCNEZ, + LISA_JISCR0, + LISA_JISCR1, + LISA_JIRL, + LISA_B, + LISA_BL, + LISA_BEQ, + LISA_BNE, + LISA_BLT, + LISA_BGE, + LISA_BLTU, + LISA_BGEU, + LISA_FADD_S, + LISA_FADD_D, + LISA_FSUB_S, + LISA_FSUB_D, + LISA_FMUL_S, + LISA_FMUL_D, + LISA_FDIV_S, + LISA_FDIV_D, + LISA_FMAX_S, + LISA_FMAX_D, + LISA_FMIN_S, + LISA_FMIN_D, + LISA_FMAXA_S, + LISA_FMAXA_D, + LISA_FMINA_S, + LISA_FMINA_D, + LISA_FSCALEB_S, + LISA_FSCALEB_D, + LISA_FCOPYSIGN_S, + LISA_FCOPYSIGN_D, + LISA_FABS_S, + LISA_FABS_D, + LISA_FNEG_S, + LISA_FNEG_D, + LISA_FLOGB_S, + LISA_FLOGB_D, + LISA_FCLASS_S, + LISA_FCLASS_D, + LISA_FSQRT_S, + LISA_FSQRT_D, + LISA_FRECIP_S, + LISA_FRECIP_D, + LISA_FRSQRT_S, + LISA_FRSQRT_D, + LISA_FMOV_S, + LISA_FMOV_D, + LISA_MOVGR2FR_W, + LISA_MOVGR2FR_D, + LISA_MOVGR2FRH_W, + LISA_MOVFR2GR_S, + LISA_MOVFR2GR_D, + LISA_MOVFRH2GR_S, + LISA_MOVGR2FCSR, + LISA_MOVFCSR2GR, + LISA_MOVFR2CF, + LISA_MOVCF2FR, + LISA_MOVGR2CF, + LISA_MOVCF2GR, + LISA_FCVT_LD_D, + LISA_FCVT_UD_D, + LISA_FCVT_D_LD, + LISA_FCVT_S_D, + LISA_FCVT_D_S, + LISA_FTINTRM_W_S, + LISA_FTINTRM_W_D, + LISA_FTINTRM_L_S, + LISA_FTINTRM_L_D, + LISA_FTINTRP_W_S, + LISA_FTINTRP_W_D, + LISA_FTINTRP_L_S, + LISA_FTINTRP_L_D, + LISA_FTINTRZ_W_S, + LISA_FTINTRZ_W_D, + LISA_FTINTRZ_L_S, + LISA_FTINTRZ_L_D, + LISA_FTINTRNE_W_S, + LISA_FTINTRNE_W_D, + LISA_FTINTRNE_L_S, + LISA_FTINTRNE_L_D, + LISA_FTINT_W_S, + LISA_FTINT_W_D, + LISA_FTINT_L_S, + LISA_FTINT_L_D, + LISA_FFINT_S_W, + LISA_FFINT_S_L, + LISA_FFINT_D_W, + LISA_FFINT_D_L, + LISA_FRINT_S, + LISA_FRINT_D, + LISA_FMADD_S, + LISA_FMADD_D, + LISA_FMSUB_S, + LISA_FMSUB_D, + LISA_FNMADD_S, + LISA_FNMADD_D, + LISA_FNMSUB_S, + LISA_FNMSUB_D, + LISA_VFMADD_S, + LISA_VFMADD_D, + LISA_VFMSUB_S, + LISA_VFMSUB_D, + LISA_VFNMADD_S, + LISA_VFNMADD_D, + LISA_VFNMSUB_S, + LISA_VFNMSUB_D, + LISA_XVFMADD_S, + LISA_XVFMADD_D, + LISA_XVFMSUB_S, + LISA_XVFMSUB_D, + LISA_XVFNMADD_S, + LISA_XVFNMADD_D, + LISA_XVFNMSUB_S, + LISA_XVFNMSUB_D, + LISA_FCMP_COND_S, + LISA_FCMP_COND_D, + LISA_VFCMP_COND_S, + LISA_VFCMP_COND_D, + LISA_XVFCMP_COND_S, + LISA_XVFCMP_COND_D, + LISA_FSEL, + LISA_VBITSEL_V, + LISA_XVBITSEL_V, + LISA_VSHUF_B, + LISA_XVSHUF_B, + LISA_VEXTR_V, + LISA_XVEXTR_V, + LISA_VFMADDSUB_S, + LISA_VFMADDSUB_D, + LISA_VFMSUBADD_S, + LISA_VFMSUBADD_D, + LISA_XVFMADDSUB_S, + LISA_XVFMADDSUB_D, + LISA_XVFMSUBADD_S, + LISA_XVFMSUBADD_D, + LISA_VSEQ_B, + LISA_VSEQ_H, + LISA_VSEQ_W, + LISA_VSEQ_D, + LISA_VSLE_B, + LISA_VSLE_H, + LISA_VSLE_W, + LISA_VSLE_D, + LISA_VSLE_BU, + LISA_VSLE_HU, + LISA_VSLE_WU, + LISA_VSLE_DU, + LISA_VSLT_B, + LISA_VSLT_H, + LISA_VSLT_W, + LISA_VSLT_D, + LISA_VSLT_BU, + LISA_VSLT_HU, + LISA_VSLT_WU, + LISA_VSLT_DU, + LISA_VADD_B, + LISA_VADD_H, + LISA_VADD_W, + LISA_VADD_D, + LISA_VSUB_B, + LISA_VSUB_H, + LISA_VSUB_W, + LISA_VSUB_D, + LISA_VADDW_H_H_B, + LISA_VADDW_W_W_H, + LISA_VADDW_D_D_W, + LISA_VADDW_H_H_BU, + LISA_VADDW_W_W_HU, + LISA_VADDW_D_D_WU, + LISA_VSUBW_H_H_B, + LISA_VSUBW_W_W_H, + LISA_VSUBW_D_D_W, + LISA_VSUBW_H_H_BU, + LISA_VSUBW_W_W_HU, + LISA_VSUBW_D_D_WU, + LISA_VSADDW_H_H_B, + LISA_VSADDW_W_W_H, + LISA_VSADDW_D_D_W, + LISA_VSADDW_HU_HU_BU, + LISA_VSADDW_WU_WU_HU, + LISA_VSADDW_DU_DU_WU, + LISA_VSSUBW_H_H_B, + LISA_VSSUBW_W_W_H, + LISA_VSSUBW_D_D_W, + LISA_VSSUBW_HU_HU_BU, + LISA_VSSUBW_WU_WU_HU, + LISA_VSSUBW_DU_DU_WU, + LISA_VADDWEV_H_B, + LISA_VADDWEV_W_H, + LISA_VADDWEV_D_W, + LISA_VADDWEV_Q_D, + LISA_VSUBWEV_H_B, + LISA_VSUBWEV_W_H, + LISA_VSUBWEV_D_W, + LISA_VSUBWEV_Q_D, + LISA_VADDWOD_H_B, + LISA_VADDWOD_W_H, + LISA_VADDWOD_D_W, + LISA_VADDWOD_Q_D, + LISA_VSUBWOD_H_B, + LISA_VSUBWOD_W_H, + LISA_VSUBWOD_D_W, + LISA_VSUBWOD_Q_D, + LISA_VADDWL_H_B, + LISA_VADDWL_W_H, + LISA_VADDWL_D_W, + LISA_VADDWL_Q_D, + LISA_VSUBWL_H_B, + LISA_VSUBWL_W_H, + LISA_VSUBWL_D_W, + LISA_VSUBWL_Q_D, + LISA_VADDWH_H_B, + LISA_VADDWH_W_H, + LISA_VADDWH_D_W, + LISA_VADDWH_Q_D, + LISA_VSUBWH_H_B, + LISA_VSUBWH_W_H, + LISA_VSUBWH_D_W, + LISA_VSUBWH_Q_D, + LISA_VADDWEV_H_BU, + LISA_VADDWEV_W_HU, + LISA_VADDWEV_D_WU, + LISA_VADDWEV_Q_DU, + LISA_VSUBWEV_H_BU, + LISA_VSUBWEV_W_HU, + LISA_VSUBWEV_D_WU, + LISA_VSUBWEV_Q_DU, + LISA_VADDWOD_H_BU, + LISA_VADDWOD_W_HU, + LISA_VADDWOD_D_WU, + LISA_VADDWOD_Q_DU, + LISA_VSUBWOD_H_BU, + LISA_VSUBWOD_W_HU, + LISA_VSUBWOD_D_WU, + LISA_VSUBWOD_Q_DU, + LISA_VADDWL_H_BU, + LISA_VADDWL_W_HU, + LISA_VADDWL_D_WU, + LISA_VADDWL_Q_DU, + LISA_VSUBWL_H_BU, + LISA_VSUBWL_W_HU, + LISA_VSUBWL_D_WU, + LISA_VSUBWL_Q_DU, + LISA_VADDWH_H_BU, + LISA_VADDWH_W_HU, + LISA_VADDWH_D_WU, + LISA_VADDWH_Q_DU, + LISA_VSUBWH_H_BU, + LISA_VSUBWH_W_HU, + LISA_VSUBWH_D_WU, + LISA_VSUBWH_Q_DU, + LISA_VADDWEV_H_BU_B, + LISA_VADDWEV_W_HU_H, + LISA_VADDWEV_D_WU_W, + LISA_VADDWEV_Q_DU_D, + LISA_VADDWOD_H_BU_B, + LISA_VADDWOD_W_HU_H, + LISA_VADDWOD_D_WU_W, + LISA_VADDWOD_Q_DU_D, + LISA_VADDWL_H_BU_B, + LISA_VADDWL_W_HU_H, + LISA_VADDWL_D_WU_W, + LISA_VADDWL_Q_DU_D, + LISA_VADDWH_H_BU_B, + LISA_VADDWH_W_HU_H, + LISA_VADDWH_D_WU_W, + LISA_VADDWH_Q_DU_D, + LISA_VSADD_B, + LISA_VSADD_H, + LISA_VSADD_W, + LISA_VSADD_D, + LISA_VSSUB_B, + LISA_VSSUB_H, + LISA_VSSUB_W, + LISA_VSSUB_D, + LISA_VSADD_BU, + LISA_VSADD_HU, + LISA_VSADD_WU, + LISA_VSADD_DU, + LISA_VSSUB_BU, + LISA_VSSUB_HU, + LISA_VSSUB_WU, + LISA_VSSUB_DU, + LISA_VSSUB_BU_BU_B, + LISA_VSSUB_HU_HU_H, + LISA_VSSUB_WU_WU_W, + LISA_VSSUB_DU_DU_D, + LISA_VSSUB_BU_B_BU, + LISA_VSSUB_HU_H_HU, + LISA_VSSUB_WU_W_WU, + LISA_VSSUB_DU_D_DU, + LISA_VSSUB_B_BU_BU, + LISA_VSSUB_H_HU_HU, + LISA_VSSUB_W_WU_WU, + LISA_VSSUB_D_DU_DU, + LISA_VHADDW_H_B, + LISA_VHADDW_W_H, + LISA_VHADDW_D_W, + LISA_VHADDW_Q_D, + LISA_VHSUBW_H_B, + LISA_VHSUBW_W_H, + LISA_VHSUBW_D_W, + LISA_VHSUBW_Q_D, + LISA_VHADDW_HU_BU, + LISA_VHADDW_WU_HU, + LISA_VHADDW_DU_WU, + LISA_VHADDW_QU_DU, + LISA_VHSUBW_HU_BU, + LISA_VHSUBW_WU_HU, + LISA_VHSUBW_DU_WU, + LISA_VHSUBW_QU_DU, + LISA_VADDA_B, + LISA_VADDA_H, + LISA_VADDA_W, + LISA_VADDA_D, + LISA_VSADDA_B, + LISA_VSADDA_H, + LISA_VSADDA_W, + LISA_VSADDA_D, + LISA_VABSD_B, + LISA_VABSD_H, + LISA_VABSD_W, + LISA_VABSD_D, + LISA_VABSD_BU, + LISA_VABSD_HU, + LISA_VABSD_WU, + LISA_VABSD_DU, + LISA_VAVG_B, + LISA_VAVG_H, + LISA_VAVG_W, + LISA_VAVG_D, + LISA_VAVG_BU, + LISA_VAVG_HU, + LISA_VAVG_WU, + LISA_VAVG_DU, + LISA_VAVGR_B, + LISA_VAVGR_H, + LISA_VAVGR_W, + LISA_VAVGR_D, + LISA_VAVGR_BU, + LISA_VAVGR_HU, + LISA_VAVGR_WU, + LISA_VAVGR_DU, + LISA_VHALFD_B, + LISA_VHALFD_H, + LISA_VHALFD_W, + LISA_VHALFD_D, + LISA_VHALFD_BU, + LISA_VHALFD_HU, + LISA_VHALFD_WU, + LISA_VHALFD_DU, + LISA_VMAX_B, + LISA_VMAX_H, + LISA_VMAX_W, + LISA_VMAX_D, + LISA_VMIN_B, + LISA_VMIN_H, + LISA_VMIN_W, + LISA_VMIN_D, + LISA_VMAX_BU, + LISA_VMAX_HU, + LISA_VMAX_WU, + LISA_VMAX_DU, + LISA_VMIN_BU, + LISA_VMIN_HU, + LISA_VMIN_WU, + LISA_VMIN_DU, + LISA_VMAXA_B, + LISA_VMAXA_H, + LISA_VMAXA_W, + LISA_VMAXA_D, + LISA_VMINA_B, + LISA_VMINA_H, + LISA_VMINA_W, + LISA_VMINA_D, + LISA_VSADW_H_B, + LISA_VSADW_W_H, + LISA_VSADW_D_W, + LISA_VSADW_H_BU, + LISA_VSADW_W_HU, + LISA_VSADW_D_WU, + LISA_VACCSADW_H_B, + LISA_VACCSADW_W_H, + LISA_VACCSADW_D_W, + LISA_VACCSADW_H_BU, + LISA_VACCSADW_W_HU, + LISA_VACCSADW_D_WU, + LISA_VMUL_B, + LISA_VMUL_H, + LISA_VMUL_W, + LISA_VMUL_D, + LISA_VMUH_B, + LISA_VMUH_H, + LISA_VMUH_W, + LISA_VMUH_D, + LISA_VMUH_BU, + LISA_VMUH_HU, + LISA_VMUH_WU, + LISA_VMUH_DU, + LISA_VMUH_BU_B, + LISA_VMUH_HU_H, + LISA_VMUH_WU_W, + LISA_VMUH_DU_D, + LISA_VMULXW_H_B, + LISA_VMULXW_W_H, + LISA_VMULXW_D_W, + LISA_VMULXW_H_BU, + LISA_VMULXW_W_HU, + LISA_VMULXW_D_WU, + LISA_VMULWEV_H_B, + LISA_VMULWEV_W_H, + LISA_VMULWEV_D_W, + LISA_VMULWEV_Q_D, + LISA_VMULWOD_H_B, + LISA_VMULWOD_W_H, + LISA_VMULWOD_D_W, + LISA_VMULWOD_Q_D, + LISA_VMULWL_H_B, + LISA_VMULWL_W_H, + LISA_VMULWL_D_W, + LISA_VMULWL_Q_D, + LISA_VMULWH_H_B, + LISA_VMULWH_W_H, + LISA_VMULWH_D_W, + LISA_VMULWH_Q_D, + LISA_VMULWEV_H_BU, + LISA_VMULWEV_W_HU, + LISA_VMULWEV_D_WU, + LISA_VMULWEV_Q_DU, + LISA_VMULWOD_H_BU, + LISA_VMULWOD_W_HU, + LISA_VMULWOD_D_WU, + LISA_VMULWOD_Q_DU, + LISA_VMULWL_H_BU, + LISA_VMULWL_W_HU, + LISA_VMULWL_D_WU, + LISA_VMULWL_Q_DU, + LISA_VMULWH_H_BU, + LISA_VMULWH_W_HU, + LISA_VMULWH_D_WU, + LISA_VMULWH_Q_DU, + LISA_VMULWEV_H_BU_B, + LISA_VMULWEV_W_HU_H, + LISA_VMULWEV_D_WU_W, + LISA_VMULWEV_Q_DU_D, + LISA_VMULWOD_H_BU_B, + LISA_VMULWOD_W_HU_H, + LISA_VMULWOD_D_WU_W, + LISA_VMULWOD_Q_DU_D, + LISA_VMULWL_H_BU_B, + LISA_VMULWL_W_HU_H, + LISA_VMULWL_D_WU_W, + LISA_VMULWL_Q_DU_D, + LISA_VMULWH_H_BU_B, + LISA_VMULWH_W_HU_H, + LISA_VMULWH_D_WU_W, + LISA_VMULWH_Q_DU_D, + LISA_VMADD_B, + LISA_VMADD_H, + LISA_VMADD_W, + LISA_VMADD_D, + LISA_VMSUB_B, + LISA_VMSUB_H, + LISA_VMSUB_W, + LISA_VMSUB_D, + LISA_VMADDWEV_H_B, + LISA_VMADDWEV_W_H, + LISA_VMADDWEV_D_W, + LISA_VMADDWEV_Q_D, + LISA_VMADDWOD_H_B, + LISA_VMADDWOD_W_H, + LISA_VMADDWOD_D_W, + LISA_VMADDWOD_Q_D, + LISA_VMADDWL_H_B, + LISA_VMADDWL_W_H, + LISA_VMADDWL_D_W, + LISA_VMADDWL_Q_D, + LISA_VMADDWH_H_B, + LISA_VMADDWH_W_H, + LISA_VMADDWH_D_W, + LISA_VMADDWH_Q_D, + LISA_VMADDWEV_H_BU, + LISA_VMADDWEV_W_HU, + LISA_VMADDWEV_D_WU, + LISA_VMADDWEV_Q_DU, + LISA_VMADDWOD_H_BU, + LISA_VMADDWOD_W_HU, + LISA_VMADDWOD_D_WU, + LISA_VMADDWOD_Q_DU, + LISA_VMADDWL_H_BU, + LISA_VMADDWL_W_HU, + LISA_VMADDWL_D_WU, + LISA_VMADDWL_Q_DU, + LISA_VMADDWH_H_BU, + LISA_VMADDWH_W_HU, + LISA_VMADDWH_D_WU, + LISA_VMADDWH_Q_DU, + LISA_VMADDWEV_H_BU_B, + LISA_VMADDWEV_W_HU_H, + LISA_VMADDWEV_D_WU_W, + LISA_VMADDWEV_Q_DU_D, + LISA_VMADDWOD_H_BU_B, + LISA_VMADDWOD_W_HU_H, + LISA_VMADDWOD_D_WU_W, + LISA_VMADDWOD_Q_DU_D, + LISA_VMADDWL_H_BU_B, + LISA_VMADDWL_W_HU_H, + LISA_VMADDWL_D_WU_W, + LISA_VMADDWL_Q_DU_D, + LISA_VMADDWH_H_BU_B, + LISA_VMADDWH_W_HU_H, + LISA_VMADDWH_D_WU_W, + LISA_VMADDWH_Q_DU_D, + LISA_VDP2_H_B, + LISA_VDP2_W_H, + LISA_VDP2_D_W, + LISA_VDP2_Q_D, + LISA_VDP2_HU_BU, + LISA_VDP2_WU_HU, + LISA_VDP2_DU_WU, + LISA_VDP2_QU_DU, + LISA_VDP2_H_BU_B, + LISA_VDP2_W_HU_H, + LISA_VDP2_D_WU_W, + LISA_VDP2_Q_DU_D, + LISA_VDP2ADD_H_B, + LISA_VDP2ADD_W_H, + LISA_VDP2ADD_D_W, + LISA_VDP2ADD_Q_D, + LISA_VDP2ADD_H_BU, + LISA_VDP2ADD_W_HU, + LISA_VDP2ADD_D_WU, + LISA_VDP2ADD_Q_DU, + LISA_VDP2ADD_H_BU_B, + LISA_VDP2ADD_W_HU_H, + LISA_VDP2ADD_D_WU_W, + LISA_VDP2ADD_Q_DU_D, + LISA_VDP2SUB_H_B, + LISA_VDP2SUB_W_H, + LISA_VDP2SUB_D_W, + LISA_VDP2SUB_Q_D, + LISA_VDP2SUB_H_BU, + LISA_VDP2SUB_W_HU, + LISA_VDP2SUB_D_WU, + LISA_VDP2SUB_Q_DU, + LISA_VDP4_W_B, + LISA_VDP4_D_H, + LISA_VDP4_Q_W, + LISA_VDP4_W_BU, + LISA_VDP4_D_HU, + LISA_VDP4_Q_WU, + LISA_VDP4_W_BU_B, + LISA_VDP4_D_HU_H, + LISA_VDP4_Q_WU_W, + LISA_VDP4ADD_W_B, + LISA_VDP4ADD_D_H, + LISA_VDP4ADD_Q_W, + LISA_VDP4ADD_W_BU, + LISA_VDP4ADD_D_HU, + LISA_VDP4ADD_Q_WU, + LISA_VDP4ADD_W_BU_B, + LISA_VDP4ADD_D_HU_H, + LISA_VDP4ADD_Q_WU_W, + LISA_VDIV_B, + LISA_VDIV_H, + LISA_VDIV_W, + LISA_VDIV_D, + LISA_VMOD_B, + LISA_VMOD_H, + LISA_VMOD_W, + LISA_VMOD_D, + LISA_VDIV_BU, + LISA_VDIV_HU, + LISA_VDIV_WU, + LISA_VDIV_DU, + LISA_VMOD_BU, + LISA_VMOD_HU, + LISA_VMOD_WU, + LISA_VMOD_DU, + LISA_VSLL_B, + LISA_VSLL_H, + LISA_VSLL_W, + LISA_VSLL_D, + LISA_VSRL_B, + LISA_VSRL_H, + LISA_VSRL_W, + LISA_VSRL_D, + LISA_VSRA_B, + LISA_VSRA_H, + LISA_VSRA_W, + LISA_VSRA_D, + LISA_VROTR_B, + LISA_VROTR_H, + LISA_VROTR_W, + LISA_VROTR_D, + LISA_VSRLR_B, + LISA_VSRLR_H, + LISA_VSRLR_W, + LISA_VSRLR_D, + LISA_VSRAR_B, + LISA_VSRAR_H, + LISA_VSRAR_W, + LISA_VSRAR_D, + LISA_VSRLN_B_H, + LISA_VSRLN_H_W, + LISA_VSRLN_W_D, + LISA_VSRAN_B_H, + LISA_VSRAN_H_W, + LISA_VSRAN_W_D, + LISA_VSRLRN_B_H, + LISA_VSRLRN_H_W, + LISA_VSRLRN_W_D, + LISA_VSRARN_B_H, + LISA_VSRARN_H_W, + LISA_VSRARN_W_D, + LISA_VSSRLN_B_H, + LISA_VSSRLN_H_W, + LISA_VSSRLN_W_D, + LISA_VSSRAN_B_H, + LISA_VSSRAN_H_W, + LISA_VSSRAN_W_D, + LISA_VSSRLRN_B_H, + LISA_VSSRLRN_H_W, + LISA_VSSRLRN_W_D, + LISA_VSSRARN_B_H, + LISA_VSSRARN_H_W, + LISA_VSSRARN_W_D, + LISA_VSSRLN_BU_H, + LISA_VSSRLN_HU_W, + LISA_VSSRLN_WU_D, + LISA_VSSRAN_BU_H, + LISA_VSSRAN_HU_W, + LISA_VSSRAN_WU_D, + LISA_VSSRLRN_BU_H, + LISA_VSSRLRN_HU_W, + LISA_VSSRLRN_WU_D, + LISA_VSSRARN_BU_H, + LISA_VSSRARN_HU_W, + LISA_VSSRARN_WU_D, + LISA_VBITCLR_B, + LISA_VBITCLR_H, + LISA_VBITCLR_W, + LISA_VBITCLR_D, + LISA_VBITSET_B, + LISA_VBITSET_H, + LISA_VBITSET_W, + LISA_VBITSET_D, + LISA_VBITREV_B, + LISA_VBITREV_H, + LISA_VBITREV_W, + LISA_VBITREV_D, + LISA_VBSTRC12_B, + LISA_VBSTRC12_H, + LISA_VBSTRC12_W, + LISA_VBSTRC12_D, + LISA_VBSTRC21_B, + LISA_VBSTRC21_H, + LISA_VBSTRC21_W, + LISA_VBSTRC21_D, + LISA_VPACKEV_B, + LISA_VPACKEV_H, + LISA_VPACKEV_W, + LISA_VPACKEV_D, + LISA_VPACKOD_B, + LISA_VPACKOD_H, + LISA_VPACKOD_W, + LISA_VPACKOD_D, + LISA_VILVL_B, + LISA_VILVL_H, + LISA_VILVL_W, + LISA_VILVL_D, + LISA_VILVH_B, + LISA_VILVH_H, + LISA_VILVH_W, + LISA_VILVH_D, + LISA_VPICKEV_B, + LISA_VPICKEV_H, + LISA_VPICKEV_W, + LISA_VPICKEV_D, + LISA_VPICKOD_B, + LISA_VPICKOD_H, + LISA_VPICKOD_W, + LISA_VPICKOD_D, + LISA_VREPLVE_B, + LISA_VREPLVE_H, + LISA_VREPLVE_W, + LISA_VREPLVE_D, + LISA_VEXTRCOL_B, + LISA_VEXTRCOL_H, + LISA_VEXTRCOL_W, + LISA_VEXTRCOL_D, + LISA_VAND_V, + LISA_VOR_V, + LISA_VXOR_V, + LISA_VNOR_V, + LISA_VANDN_V, + LISA_VORN_V, + LISA_VRANDSIGN_B, + LISA_VRANDSIGN_H, + LISA_VRORSIGN_B, + LISA_VRORSIGN_H, + LISA_VFRSTP_B, + LISA_VFRSTP_H, + LISA_VCLRSTRR_V, + LISA_VCLRSTRV_V, + LISA_VADD_Q, + LISA_VSUB_Q, + LISA_VSIGNCOV_B, + LISA_VSIGNCOV_H, + LISA_VSIGNCOV_W, + LISA_VSIGNCOV_D, + LISA_VFADD_S, + LISA_VFADD_D, + LISA_VFSUB_S, + LISA_VFSUB_D, + LISA_VFADDSUB_S, + LISA_VFADDSUB_D, + LISA_VFSUBADD_S, + LISA_VFSUBADD_D, + LISA_VFMUL_S, + LISA_VFMUL_D, + LISA_VFDIV_S, + LISA_VFDIV_D, + LISA_VFMAX_S, + LISA_VFMAX_D, + LISA_VFMIN_S, + LISA_VFMIN_D, + LISA_VFMAXA_S, + LISA_VFMAXA_D, + LISA_VFMINA_S, + LISA_VFMINA_D, + LISA_VFSCALEB_S, + LISA_VFSCALEB_D, + LISA_VFCVT_H_S, + LISA_VFCVT_S_D, + LISA_VFFINT_S_L, + LISA_VFTINT_W_D, + LISA_VFTINTRM_W_D, + LISA_VFTINTRP_W_D, + LISA_VFTINTRZ_W_D, + LISA_VFTINTRNE_W_D, + LISA_VHADD4_H_BU, + LISA_VSHUF4_W, + LISA_VSHUF2_D, + LISA_AES128_ENC, + LISA_AES128_DEC, + LISA_AES192_ENC, + LISA_AES192_DEC, + LISA_AES256_ENC, + LISA_AES256_DEC, + LISA_AES_KG, + LISA_AES_FR_ENC, + LISA_AES_FR_DEC, + LISA_AES_LR_ENC, + LISA_AES_LR_DEC, + LISA_AES_MC_ENC, + LISA_AES_MC_DEC, + LISA_AES_SB_ENC, + LISA_AES_SB_DEC, + LISA_AES_SR_ENC, + LISA_AES_SR_DEC, + LISA_MD5_MS, + LISA_MD5_4R, + LISA_SHA1_MS_1, + LISA_SHA1_MS_2, + LISA_SHA1_HASH_4R, + LISA_SHA256_MS_1, + LISA_SHA256_MS_2, + LISA_SHA256_HASH_2R, + LISA_SHA512_MS_1, + LISA_SHA512_MS_2, + LISA_SHA512_HASH_R_1, + LISA_SHA512_HASH_R_2, + LISA_VPMUL_W, + LISA_VPMUL_D, + LISA_VPMUH_W, + LISA_VPMUH_D, + LISA_VPMULACC_W, + LISA_VPMULACC_D, + LISA_VPMUHACC_W, + LISA_VPMUHACC_D, + LISA_VPMULWL_H_B, + LISA_VPMULWL_W_H, + LISA_VPMULWL_D_W, + LISA_VPMULWL_Q_D, + LISA_VPMULWH_H_B, + LISA_VPMULWH_W_H, + LISA_VPMULWH_D_W, + LISA_VPMULWH_Q_D, + LISA_VPMADDWL_H_B, + LISA_VPMADDWL_W_H, + LISA_VPMADDWL_D_W, + LISA_VPMADDWL_Q_D, + LISA_VPMADDWH_H_B, + LISA_VPMADDWH_W_H, + LISA_VPMADDWH_D_W, + LISA_VPMADDWH_Q_D, + LISA_VPDP2_Q_D, + LISA_VPDP2ADD_Q_D, + LISA_VCDP4_RE_D_H, + LISA_VCDP4_IM_D_H, + LISA_VCDP4ADD_RE_D_H, + LISA_VCDP4ADD_IM_D_H, + LISA_VCDP2_RE_Q_W, + LISA_VCDP2_IM_Q_W, + LISA_VCDP2ADD_RE_Q_W, + LISA_VCDP2ADD_IM_Q_W, + LISA_VSIGNSEL_W, + LISA_VSIGNSEL_D, + LISA_VSHUF_H, + LISA_VSHUF_W, + LISA_VSHUF_D, + LISA_VSEQI_B, + LISA_VSEQI_H, + LISA_VSEQI_W, + LISA_VSEQI_D, + LISA_VSLEI_B, + LISA_VSLEI_H, + LISA_VSLEI_W, + LISA_VSLEI_D, + LISA_VSLEI_BU, + LISA_VSLEI_HU, + LISA_VSLEI_WU, + LISA_VSLEI_DU, + LISA_VSLTI_B, + LISA_VSLTI_H, + LISA_VSLTI_W, + LISA_VSLTI_D, + LISA_VSLTI_BU, + LISA_VSLTI_HU, + LISA_VSLTI_WU, + LISA_VSLTI_DU, + LISA_VADDI_BU, + LISA_VADDI_HU, + LISA_VADDI_WU, + LISA_VADDI_DU, + LISA_VSUBI_BU, + LISA_VSUBI_HU, + LISA_VSUBI_WU, + LISA_VSUBI_DU, + LISA_VBSLL_V, + LISA_VBSRL_V, + LISA_VMAXI_B, + LISA_VMAXI_H, + LISA_VMAXI_W, + LISA_VMAXI_D, + LISA_VMINI_B, + LISA_VMINI_H, + LISA_VMINI_W, + LISA_VMINI_D, + LISA_VMAXI_BU, + LISA_VMAXI_HU, + LISA_VMAXI_WU, + LISA_VMAXI_DU, + LISA_VMINI_BU, + LISA_VMINI_HU, + LISA_VMINI_WU, + LISA_VMINI_DU, + LISA_VRANDSIGNI_B, + LISA_VRANDSIGNI_H, + LISA_VRORSIGNI_B, + LISA_VRORSIGNI_H, + LISA_VFRSTPI_B, + LISA_VFRSTPI_H, + LISA_VCLRSTRI_V, + LISA_VMEPATMSK_V, + LISA_VCLO_B, + LISA_VCLO_H, + LISA_VCLO_W, + LISA_VCLO_D, + LISA_VCLZ_B, + LISA_VCLZ_H, + LISA_VCLZ_W, + LISA_VCLZ_D, + LISA_VPCNT_B, + LISA_VPCNT_H, + LISA_VPCNT_W, + LISA_VPCNT_D, + LISA_VNEG_B, + LISA_VNEG_H, + LISA_VNEG_W, + LISA_VNEG_D, + LISA_VMSKLTZ_B, + LISA_VMSKLTZ_H, + LISA_VMSKLTZ_W, + LISA_VMSKLTZ_D, + LISA_VMSKGEZ_B, + LISA_VMSKNZ_B, + LISA_VMSKCOPY_B, + LISA_VMSKFILL_B, + LISA_VFRSTM_B, + LISA_VFRSTM_H, + LISA_VSETEQZ_V, + LISA_VSETNEZ_V, + LISA_VSETANYEQZ_B, + LISA_VSETANYEQZ_H, + LISA_VSETANYEQZ_W, + LISA_VSETANYEQZ_D, + LISA_VSETALLNEZ_B, + LISA_VSETALLNEZ_H, + LISA_VSETALLNEZ_W, + LISA_VSETALLNEZ_D, + LISA_VFLOGB_S, + LISA_VFLOGB_D, + LISA_VFCLASS_S, + LISA_VFCLASS_D, + LISA_VFSQRT_S, + LISA_VFSQRT_D, + LISA_VFRECIP_S, + LISA_VFRECIP_D, + LISA_VFRSQRT_S, + LISA_VFRSQRT_D, + LISA_VFRINT_S, + LISA_VFRINT_D, + LISA_VFRINTRM_S, + LISA_VFRINTRM_D, + LISA_VFRINTRP_S, + LISA_VFRINTRP_D, + LISA_VFRINTRZ_S, + LISA_VFRINTRZ_D, + LISA_VFRINTRNE_S, + LISA_VFRINTRNE_D, + LISA_VEXTL_W_B, + LISA_VEXTL_D_B, + LISA_VEXTL_D_H, + LISA_VEXTL_W_BU, + LISA_VEXTL_D_BU, + LISA_VEXTL_D_HU, + LISA_VHADD8_D_BU, + LISA_VHMINPOS_W_HU, + LISA_VHMINPOS_D_HU, + LISA_VHMINPOS_Q_HU, + LISA_VCLRTAIL_B, + LISA_VCLRTAIL_H, + LISA_VFCVTL_S_H, + LISA_VFCVTH_S_H, + LISA_VFCVTL_D_S, + LISA_VFCVTH_D_S, + LISA_VFFINT_S_W, + LISA_VFFINT_S_WU, + LISA_VFFINT_D_L, + LISA_VFFINT_D_LU, + LISA_VFFINTL_D_W, + LISA_VFFINTH_D_W, + LISA_VFTINT_W_S, + LISA_VFTINT_L_D, + LISA_VFTINTRM_W_S, + LISA_VFTINTRM_L_D, + LISA_VFTINTRP_W_S, + LISA_VFTINTRP_L_D, + LISA_VFTINTRZ_W_S, + LISA_VFTINTRZ_L_D, + LISA_VFTINTRNE_W_S, + LISA_VFTINTRNE_L_D, + LISA_VFTINT_WU_S, + LISA_VFTINT_LU_D, + LISA_VFTINTRZ_WU_S, + LISA_VFTINTRZ_LU_D, + LISA_VFTINTL_L_S, + LISA_VFTINTH_L_S, + LISA_VFTINTRML_L_S, + LISA_VFTINTRMH_L_S, + LISA_VFTINTRPL_L_S, + LISA_VFTINTRPH_L_S, + LISA_VFTINTRZL_L_S, + LISA_VFTINTRZH_L_S, + LISA_VFTINTRNEL_L_S, + LISA_VFTINTRNEH_L_S, + LISA_VEXTH_H_B, + LISA_VEXTH_W_H, + LISA_VEXTH_D_W, + LISA_VEXTH_Q_D, + LISA_VEXTH_HU_BU, + LISA_VEXTH_WU_HU, + LISA_VEXTH_DU_WU, + LISA_VEXTH_QU_DU, + LISA_VREPLGR2VR_B, + LISA_VREPLGR2VR_H, + LISA_VREPLGR2VR_W, + LISA_VREPLGR2VR_D, + LISA_VROTRI_B, + LISA_VROTRI_H, + LISA_VROTRI_W, + LISA_VROTRI_D, + LISA_VSRLRI_B, + LISA_VSRLRI_H, + LISA_VSRLRI_W, + LISA_VSRLRI_D, + LISA_VSRARI_B, + LISA_VSRARI_H, + LISA_VSRARI_W, + LISA_VSRARI_D, + LISA_VINSGR2VR_B, + LISA_VINSGR2VR_H, + LISA_VINSGR2VR_W, + LISA_VINSGR2VR_D, + LISA_VPICKVE2GR_B, + LISA_VPICKVE2GR_H, + LISA_VPICKVE2GR_W, + LISA_VPICKVE2GR_D, + LISA_VPICKVE2GR_BU, + LISA_VPICKVE2GR_HU, + LISA_VPICKVE2GR_WU, + LISA_VPICKVE2GR_DU, + LISA_VREPLVEI_B, + LISA_VREPLVEI_H, + LISA_VREPLVEI_W, + LISA_VREPLVEI_D, + LISA_VEXTRCOLI_B, + LISA_VEXTRCOLI_H, + LISA_VEXTRCOLI_W, + LISA_VEXTRCOLI_D, + LISA_VSLLWIL_H_B, + LISA_VSLLWIL_W_H, + LISA_VSLLWIL_D_W, + LISA_VEXTL_Q_D, + LISA_VSLLWIL_HU_BU, + LISA_VSLLWIL_WU_HU, + LISA_VSLLWIL_DU_WU, + LISA_VEXTL_QU_DU, + LISA_VBITCLRI_B, + LISA_VBITCLRI_H, + LISA_VBITCLRI_W, + LISA_VBITCLRI_D, + LISA_VBITSETI_B, + LISA_VBITSETI_H, + LISA_VBITSETI_W, + LISA_VBITSETI_D, + LISA_VBITREVI_B, + LISA_VBITREVI_H, + LISA_VBITREVI_W, + LISA_VBITREVI_D, + LISA_VBSTRC12I_B, + LISA_VBSTRC12I_H, + LISA_VBSTRC12I_W, + LISA_VBSTRC12I_D, + LISA_VBSTRC21I_B, + LISA_VBSTRC21I_H, + LISA_VBSTRC21I_W, + LISA_VBSTRC21I_D, + LISA_VSAT_B, + LISA_VSAT_H, + LISA_VSAT_W, + LISA_VSAT_D, + LISA_VSAT_BU, + LISA_VSAT_HU, + LISA_VSAT_WU, + LISA_VSAT_DU, + LISA_VSLLI_B, + LISA_VSLLI_H, + LISA_VSLLI_W, + LISA_VSLLI_D, + LISA_VSRLI_B, + LISA_VSRLI_H, + LISA_VSRLI_W, + LISA_VSRLI_D, + LISA_VSRAI_B, + LISA_VSRAI_H, + LISA_VSRAI_W, + LISA_VSRAI_D, + LISA_VSRLRNENI_B_H, + LISA_VSRLRNENI_H_W, + LISA_VSRLRNENI_W_D, + LISA_VSRLRNENI_D_Q, + LISA_VSRARNENI_B_H, + LISA_VSRARNENI_H_W, + LISA_VSRARNENI_W_D, + LISA_VSRARNENI_D_Q, + LISA_VSRLNI_B_H, + LISA_VSRLNI_H_W, + LISA_VSRLNI_W_D, + LISA_VSRLNI_D_Q, + LISA_VSRLRNI_B_H, + LISA_VSRLRNI_H_W, + LISA_VSRLRNI_W_D, + LISA_VSRLRNI_D_Q, + LISA_VSSRLNI_B_H, + LISA_VSSRLNI_H_W, + LISA_VSSRLNI_W_D, + LISA_VSSRLNI_D_Q, + LISA_VSSRLNI_BU_H, + LISA_VSSRLNI_HU_W, + LISA_VSSRLNI_WU_D, + LISA_VSSRLNI_DU_Q, + LISA_VSSRLRNI_B_H, + LISA_VSSRLRNI_H_W, + LISA_VSSRLRNI_W_D, + LISA_VSSRLRNI_D_Q, + LISA_VSSRLRNI_BU_H, + LISA_VSSRLRNI_HU_W, + LISA_VSSRLRNI_WU_D, + LISA_VSSRLRNI_DU_Q, + LISA_VSRANI_B_H, + LISA_VSRANI_H_W, + LISA_VSRANI_W_D, + LISA_VSRANI_D_Q, + LISA_VSRARNI_B_H, + LISA_VSRARNI_H_W, + LISA_VSRARNI_W_D, + LISA_VSRARNI_D_Q, + LISA_VSSRANI_B_H, + LISA_VSSRANI_H_W, + LISA_VSSRANI_W_D, + LISA_VSSRANI_D_Q, + LISA_VSSRANI_BU_H, + LISA_VSSRANI_HU_W, + LISA_VSSRANI_WU_D, + LISA_VSSRANI_DU_Q, + LISA_VSSRARNI_B_H, + LISA_VSSRARNI_H_W, + LISA_VSSRARNI_W_D, + LISA_VSSRARNI_D_Q, + LISA_VSSRARNI_BU_H, + LISA_VSSRARNI_HU_W, + LISA_VSSRARNI_WU_D, + LISA_VSSRARNI_DU_Q, + LISA_VSSRLRNENI_B_H, + LISA_VSSRLRNENI_H_W, + LISA_VSSRLRNENI_W_D, + LISA_VSSRLRNENI_D_Q, + LISA_VSSRLRNENI_BU_H, + LISA_VSSRLRNENI_HU_W, + LISA_VSSRLRNENI_WU_D, + LISA_VSSRLRNENI_DU_Q, + LISA_VSSRARNENI_B_H, + LISA_VSSRARNENI_H_W, + LISA_VSSRARNENI_W_D, + LISA_VSSRARNENI_D_Q, + LISA_VSSRARNENI_BU_H, + LISA_VSSRARNENI_HU_W, + LISA_VSSRARNENI_WU_D, + LISA_VSSRARNENI_DU_Q, + LISA_VEXTRINS_D, + LISA_VEXTRINS_W, + LISA_VEXTRINS_H, + LISA_VEXTRINS_B, + LISA_VSHUF4I_B, + LISA_VSHUF4I_H, + LISA_VSHUF4I_W, + LISA_VSHUF4I_D, + LISA_VSHUFI1_B, + LISA_VSHUFI2_B, + LISA_VSHUFI3_B, + LISA_VSHUFI4_B, + LISA_VSHUFI1_H, + LISA_VSHUFI2_H, + LISA_VSELI_H, + LISA_VSELI_W, + LISA_VSELI_D, + LISA_VBITSELI_B, + LISA_VBITMVZI_B, + LISA_VBITMVNZI_B, + LISA_VANDI_B, + LISA_VORI_B, + LISA_VXORI_B, + LISA_VNORI_B, + LISA_VLDI, + LISA_VPERMI_W, + LISA_XVSEQ_B, + LISA_XVSEQ_H, + LISA_XVSEQ_W, + LISA_XVSEQ_D, + LISA_XVSLE_B, + LISA_XVSLE_H, + LISA_XVSLE_W, + LISA_XVSLE_D, + LISA_XVSLE_BU, + LISA_XVSLE_HU, + LISA_XVSLE_WU, + LISA_XVSLE_DU, + LISA_XVSLT_B, + LISA_XVSLT_H, + LISA_XVSLT_W, + LISA_XVSLT_D, + LISA_XVSLT_BU, + LISA_XVSLT_HU, + LISA_XVSLT_WU, + LISA_XVSLT_DU, + LISA_XVADD_B, + LISA_XVADD_H, + LISA_XVADD_W, + LISA_XVADD_D, + LISA_XVSUB_B, + LISA_XVSUB_H, + LISA_XVSUB_W, + LISA_XVSUB_D, + LISA_XVADDW_H_H_B, + LISA_XVADDW_W_W_H, + LISA_XVADDW_D_D_W, + LISA_XVADDW_H_H_BU, + LISA_XVADDW_W_W_HU, + LISA_XVADDW_D_D_WU, + LISA_XVSUBW_H_H_B, + LISA_XVSUBW_W_W_H, + LISA_XVSUBW_D_D_W, + LISA_XVSUBW_H_H_BU, + LISA_XVSUBW_W_W_HU, + LISA_XVSUBW_D_D_WU, + LISA_XVSADDW_H_H_B, + LISA_XVSADDW_W_W_H, + LISA_XVSADDW_D_D_W, + LISA_XVSADDW_HU_HU_BU, + LISA_XVSADDW_WU_WU_HU, + LISA_XVSADDW_DU_DU_WU, + LISA_XVSSUBW_H_H_B, + LISA_XVSSUBW_W_W_H, + LISA_XVSSUBW_D_D_W, + LISA_XVSSUBW_HU_HU_BU, + LISA_XVSSUBW_WU_WU_HU, + LISA_XVSSUBW_DU_DU_WU, + LISA_XVADDWEV_H_B, + LISA_XVADDWEV_W_H, + LISA_XVADDWEV_D_W, + LISA_XVADDWEV_Q_D, + LISA_XVSUBWEV_H_B, + LISA_XVSUBWEV_W_H, + LISA_XVSUBWEV_D_W, + LISA_XVSUBWEV_Q_D, + LISA_XVADDWOD_H_B, + LISA_XVADDWOD_W_H, + LISA_XVADDWOD_D_W, + LISA_XVADDWOD_Q_D, + LISA_XVSUBWOD_H_B, + LISA_XVSUBWOD_W_H, + LISA_XVSUBWOD_D_W, + LISA_XVSUBWOD_Q_D, + LISA_XVADDWL_H_B, + LISA_XVADDWL_W_H, + LISA_XVADDWL_D_W, + LISA_XVADDWL_Q_D, + LISA_XVSUBWL_H_B, + LISA_XVSUBWL_W_H, + LISA_XVSUBWL_D_W, + LISA_XVSUBWL_Q_D, + LISA_XVADDWH_H_B, + LISA_XVADDWH_W_H, + LISA_XVADDWH_D_W, + LISA_XVADDWH_Q_D, + LISA_XVSUBWH_H_B, + LISA_XVSUBWH_W_H, + LISA_XVSUBWH_D_W, + LISA_XVSUBWH_Q_D, + LISA_XVADDWEV_H_BU, + LISA_XVADDWEV_W_HU, + LISA_XVADDWEV_D_WU, + LISA_XVADDWEV_Q_DU, + LISA_XVSUBWEV_H_BU, + LISA_XVSUBWEV_W_HU, + LISA_XVSUBWEV_D_WU, + LISA_XVSUBWEV_Q_DU, + LISA_XVADDWOD_H_BU, + LISA_XVADDWOD_W_HU, + LISA_XVADDWOD_D_WU, + LISA_XVADDWOD_Q_DU, + LISA_XVSUBWOD_H_BU, + LISA_XVSUBWOD_W_HU, + LISA_XVSUBWOD_D_WU, + LISA_XVSUBWOD_Q_DU, + LISA_XVADDWL_H_BU, + LISA_XVADDWL_W_HU, + LISA_XVADDWL_D_WU, + LISA_XVADDWL_Q_DU, + LISA_XVSUBWL_H_BU, + LISA_XVSUBWL_W_HU, + LISA_XVSUBWL_D_WU, + LISA_XVSUBWL_Q_DU, + LISA_XVADDWH_H_BU, + LISA_XVADDWH_W_HU, + LISA_XVADDWH_D_WU, + LISA_XVADDWH_Q_DU, + LISA_XVSUBWH_H_BU, + LISA_XVSUBWH_W_HU, + LISA_XVSUBWH_D_WU, + LISA_XVSUBWH_Q_DU, + LISA_XVADDWEV_H_BU_B, + LISA_XVADDWEV_W_HU_H, + LISA_XVADDWEV_D_WU_W, + LISA_XVADDWEV_Q_DU_D, + LISA_XVADDWOD_H_BU_B, + LISA_XVADDWOD_W_HU_H, + LISA_XVADDWOD_D_WU_W, + LISA_XVADDWOD_Q_DU_D, + LISA_XVADDWL_H_BU_B, + LISA_XVADDWL_W_HU_H, + LISA_XVADDWL_D_WU_W, + LISA_XVADDWL_Q_DU_D, + LISA_XVADDWH_H_BU_B, + LISA_XVADDWH_W_HU_H, + LISA_XVADDWH_D_WU_W, + LISA_XVADDWH_Q_DU_D, + LISA_XVSADD_B, + LISA_XVSADD_H, + LISA_XVSADD_W, + LISA_XVSADD_D, + LISA_XVSSUB_B, + LISA_XVSSUB_H, + LISA_XVSSUB_W, + LISA_XVSSUB_D, + LISA_XVSADD_BU, + LISA_XVSADD_HU, + LISA_XVSADD_WU, + LISA_XVSADD_DU, + LISA_XVSSUB_BU, + LISA_XVSSUB_HU, + LISA_XVSSUB_WU, + LISA_XVSSUB_DU, + LISA_XVSSUB_BU_BU_B, + LISA_XVSSUB_HU_HU_H, + LISA_XVSSUB_WU_WU_W, + LISA_XVSSUB_DU_DU_D, + LISA_XVSSUB_BU_B_BU, + LISA_XVSSUB_HU_H_HU, + LISA_XVSSUB_WU_W_WU, + LISA_XVSSUB_DU_D_DU, + LISA_XVSSUB_B_BU_BU, + LISA_XVSSUB_H_HU_HU, + LISA_XVSSUB_W_WU_WU, + LISA_XVSSUB_D_DU_DU, + LISA_XVHADDW_H_B, + LISA_XVHADDW_W_H, + LISA_XVHADDW_D_W, + LISA_XVHADDW_Q_D, + LISA_XVHSUBW_H_B, + LISA_XVHSUBW_W_H, + LISA_XVHSUBW_D_W, + LISA_XVHSUBW_Q_D, + LISA_XVHADDW_HU_BU, + LISA_XVHADDW_WU_HU, + LISA_XVHADDW_DU_WU, + LISA_XVHADDW_QU_DU, + LISA_XVHSUBW_HU_BU, + LISA_XVHSUBW_WU_HU, + LISA_XVHSUBW_DU_WU, + LISA_XVHSUBW_QU_DU, + LISA_XVADDA_B, + LISA_XVADDA_H, + LISA_XVADDA_W, + LISA_XVADDA_D, + LISA_XVSADDA_B, + LISA_XVSADDA_H, + LISA_XVSADDA_W, + LISA_XVSADDA_D, + LISA_XVABSD_B, + LISA_XVABSD_H, + LISA_XVABSD_W, + LISA_XVABSD_D, + LISA_XVABSD_BU, + LISA_XVABSD_HU, + LISA_XVABSD_WU, + LISA_XVABSD_DU, + LISA_XVAVG_B, + LISA_XVAVG_H, + LISA_XVAVG_W, + LISA_XVAVG_D, + LISA_XVAVG_BU, + LISA_XVAVG_HU, + LISA_XVAVG_WU, + LISA_XVAVG_DU, + LISA_XVAVGR_B, + LISA_XVAVGR_H, + LISA_XVAVGR_W, + LISA_XVAVGR_D, + LISA_XVAVGR_BU, + LISA_XVAVGR_HU, + LISA_XVAVGR_WU, + LISA_XVAVGR_DU, + LISA_XVHALFD_B, + LISA_XVHALFD_H, + LISA_XVHALFD_W, + LISA_XVHALFD_D, + LISA_XVHALFD_BU, + LISA_XVHALFD_HU, + LISA_XVHALFD_WU, + LISA_XVHALFD_DU, + LISA_XVMAX_B, + LISA_XVMAX_H, + LISA_XVMAX_W, + LISA_XVMAX_D, + LISA_XVMIN_B, + LISA_XVMIN_H, + LISA_XVMIN_W, + LISA_XVMIN_D, + LISA_XVMAX_BU, + LISA_XVMAX_HU, + LISA_XVMAX_WU, + LISA_XVMAX_DU, + LISA_XVMIN_BU, + LISA_XVMIN_HU, + LISA_XVMIN_WU, + LISA_XVMIN_DU, + LISA_XVMAXA_B, + LISA_XVMAXA_H, + LISA_XVMAXA_W, + LISA_XVMAXA_D, + LISA_XVMINA_B, + LISA_XVMINA_H, + LISA_XVMINA_W, + LISA_XVMINA_D, + LISA_XVSADW_H_B, + LISA_XVSADW_W_H, + LISA_XVSADW_D_W, + LISA_XVSADW_H_BU, + LISA_XVSADW_W_HU, + LISA_XVSADW_D_WU, + LISA_XVACCSADW_H_B, + LISA_XVACCSADW_W_H, + LISA_XVACCSADW_D_W, + LISA_XVACCSADW_H_BU, + LISA_XVACCSADW_W_HU, + LISA_XVACCSADW_D_WU, + LISA_XVMUL_B, + LISA_XVMUL_H, + LISA_XVMUL_W, + LISA_XVMUL_D, + LISA_XVMUH_B, + LISA_XVMUH_H, + LISA_XVMUH_W, + LISA_XVMUH_D, + LISA_XVMUH_BU, + LISA_XVMUH_HU, + LISA_XVMUH_WU, + LISA_XVMUH_DU, + LISA_XVMUH_BU_B, + LISA_XVMUH_HU_H, + LISA_XVMUH_WU_W, + LISA_XVMUH_DU_D, + LISA_XVMULXW_H_B, + LISA_XVMULXW_W_H, + LISA_XVMULXW_D_W, + LISA_XVMULXW_H_BU, + LISA_XVMULXW_W_HU, + LISA_XVMULXW_D_WU, + LISA_XVMULWEV_H_B, + LISA_XVMULWEV_W_H, + LISA_XVMULWEV_D_W, + LISA_XVMULWEV_Q_D, + LISA_XVMULWOD_H_B, + LISA_XVMULWOD_W_H, + LISA_XVMULWOD_D_W, + LISA_XVMULWOD_Q_D, + LISA_XVMULWL_H_B, + LISA_XVMULWL_W_H, + LISA_XVMULWL_D_W, + LISA_XVMULWL_Q_D, + LISA_XVMULWH_H_B, + LISA_XVMULWH_W_H, + LISA_XVMULWH_D_W, + LISA_XVMULWH_Q_D, + LISA_XVMULWEV_H_BU, + LISA_XVMULWEV_W_HU, + LISA_XVMULWEV_D_WU, + LISA_XVMULWEV_Q_DU, + LISA_XVMULWOD_H_BU, + LISA_XVMULWOD_W_HU, + LISA_XVMULWOD_D_WU, + LISA_XVMULWOD_Q_DU, + LISA_XVMULWL_H_BU, + LISA_XVMULWL_W_HU, + LISA_XVMULWL_D_WU, + LISA_XVMULWL_Q_DU, + LISA_XVMULWH_H_BU, + LISA_XVMULWH_W_HU, + LISA_XVMULWH_D_WU, + LISA_XVMULWH_Q_DU, + LISA_XVMULWEV_H_BU_B, + LISA_XVMULWEV_W_HU_H, + LISA_XVMULWEV_D_WU_W, + LISA_XVMULWEV_Q_DU_D, + LISA_XVMULWOD_H_BU_B, + LISA_XVMULWOD_W_HU_H, + LISA_XVMULWOD_D_WU_W, + LISA_XVMULWOD_Q_DU_D, + LISA_XVMULWL_H_BU_B, + LISA_XVMULWL_W_HU_H, + LISA_XVMULWL_D_WU_W, + LISA_XVMULWL_Q_DU_D, + LISA_XVMULWH_H_BU_B, + LISA_XVMULWH_W_HU_H, + LISA_XVMULWH_D_WU_W, + LISA_XVMULWH_Q_DU_D, + LISA_XVMADD_B, + LISA_XVMADD_H, + LISA_XVMADD_W, + LISA_XVMADD_D, + LISA_XVMSUB_B, + LISA_XVMSUB_H, + LISA_XVMSUB_W, + LISA_XVMSUB_D, + LISA_XVMADDWEV_H_B, + LISA_XVMADDWEV_W_H, + LISA_XVMADDWEV_D_W, + LISA_XVMADDWEV_Q_D, + LISA_XVMADDWOD_H_B, + LISA_XVMADDWOD_W_H, + LISA_XVMADDWOD_D_W, + LISA_XVMADDWOD_Q_D, + LISA_XVMADDWL_H_B, + LISA_XVMADDWL_W_H, + LISA_XVMADDWL_D_W, + LISA_XVMADDWL_Q_D, + LISA_XVMADDWH_H_B, + LISA_XVMADDWH_W_H, + LISA_XVMADDWH_D_W, + LISA_XVMADDWH_Q_D, + LISA_XVMADDWEV_H_BU, + LISA_XVMADDWEV_W_HU, + LISA_XVMADDWEV_D_WU, + LISA_XVMADDWEV_Q_DU, + LISA_XVMADDWOD_H_BU, + LISA_XVMADDWOD_W_HU, + LISA_XVMADDWOD_D_WU, + LISA_XVMADDWOD_Q_DU, + LISA_XVMADDWL_H_BU, + LISA_XVMADDWL_W_HU, + LISA_XVMADDWL_D_WU, + LISA_XVMADDWL_Q_DU, + LISA_XVMADDWH_H_BU, + LISA_XVMADDWH_W_HU, + LISA_XVMADDWH_D_WU, + LISA_XVMADDWH_Q_DU, + LISA_XVMADDWEV_H_BU_B, + LISA_XVMADDWEV_W_HU_H, + LISA_XVMADDWEV_D_WU_W, + LISA_XVMADDWEV_Q_DU_D, + LISA_XVMADDWOD_H_BU_B, + LISA_XVMADDWOD_W_HU_H, + LISA_XVMADDWOD_D_WU_W, + LISA_XVMADDWOD_Q_DU_D, + LISA_XVMADDWL_H_BU_B, + LISA_XVMADDWL_W_HU_H, + LISA_XVMADDWL_D_WU_W, + LISA_XVMADDWL_Q_DU_D, + LISA_XVMADDWH_H_BU_B, + LISA_XVMADDWH_W_HU_H, + LISA_XVMADDWH_D_WU_W, + LISA_XVMADDWH_Q_DU_D, + LISA_XVDP2_H_B, + LISA_XVDP2_W_H, + LISA_XVDP2_D_W, + LISA_XVDP2_Q_D, + LISA_XVDP2_HU_BU, + LISA_XVDP2_WU_HU, + LISA_XVDP2_DU_WU, + LISA_XVDP2_QU_DU, + LISA_XVDP2_H_BU_B, + LISA_XVDP2_W_HU_H, + LISA_XVDP2_D_WU_W, + LISA_XVDP2_Q_DU_D, + LISA_XVDP2ADD_H_B, + LISA_XVDP2ADD_W_H, + LISA_XVDP2ADD_D_W, + LISA_XVDP2ADD_Q_D, + LISA_XVDP2ADD_H_BU, + LISA_XVDP2ADD_W_HU, + LISA_XVDP2ADD_D_WU, + LISA_XVDP2ADD_Q_DU, + LISA_XVDP2ADD_H_BU_B, + LISA_XVDP2ADD_W_HU_H, + LISA_XVDP2ADD_D_WU_W, + LISA_XVDP2ADD_Q_DU_D, + LISA_XVDP2SUB_H_B, + LISA_XVDP2SUB_W_H, + LISA_XVDP2SUB_D_W, + LISA_XVDP2SUB_Q_D, + LISA_XVDP2SUB_H_BU, + LISA_XVDP2SUB_W_HU, + LISA_XVDP2SUB_D_WU, + LISA_XVDP2SUB_Q_DU, + LISA_XVDP4_W_B, + LISA_XVDP4_D_H, + LISA_XVDP4_Q_W, + LISA_XVDP4_W_BU, + LISA_XVDP4_D_HU, + LISA_XVDP4_Q_WU, + LISA_XVDP4_W_BU_B, + LISA_XVDP4_D_HU_H, + LISA_XVDP4_Q_WU_W, + LISA_XVDP4ADD_W_B, + LISA_XVDP4ADD_D_H, + LISA_XVDP4ADD_Q_W, + LISA_XVDP4ADD_W_BU, + LISA_XVDP4ADD_D_HU, + LISA_XVDP4ADD_Q_WU, + LISA_XVDP4ADD_W_BU_B, + LISA_XVDP4ADD_D_HU_H, + LISA_XVDP4ADD_Q_WU_W, + LISA_XVDIV_B, + LISA_XVDIV_H, + LISA_XVDIV_W, + LISA_XVDIV_D, + LISA_XVMOD_B, + LISA_XVMOD_H, + LISA_XVMOD_W, + LISA_XVMOD_D, + LISA_XVDIV_BU, + LISA_XVDIV_HU, + LISA_XVDIV_WU, + LISA_XVDIV_DU, + LISA_XVMOD_BU, + LISA_XVMOD_HU, + LISA_XVMOD_WU, + LISA_XVMOD_DU, + LISA_XVSLL_B, + LISA_XVSLL_H, + LISA_XVSLL_W, + LISA_XVSLL_D, + LISA_XVSRL_B, + LISA_XVSRL_H, + LISA_XVSRL_W, + LISA_XVSRL_D, + LISA_XVSRA_B, + LISA_XVSRA_H, + LISA_XVSRA_W, + LISA_XVSRA_D, + LISA_XVROTR_B, + LISA_XVROTR_H, + LISA_XVROTR_W, + LISA_XVROTR_D, + LISA_XVSRLR_B, + LISA_XVSRLR_H, + LISA_XVSRLR_W, + LISA_XVSRLR_D, + LISA_XVSRAR_B, + LISA_XVSRAR_H, + LISA_XVSRAR_W, + LISA_XVSRAR_D, + LISA_XVSRLN_B_H, + LISA_XVSRLN_H_W, + LISA_XVSRLN_W_D, + LISA_XVSRAN_B_H, + LISA_XVSRAN_H_W, + LISA_XVSRAN_W_D, + LISA_XVSRLRN_B_H, + LISA_XVSRLRN_H_W, + LISA_XVSRLRN_W_D, + LISA_XVSRARN_B_H, + LISA_XVSRARN_H_W, + LISA_XVSRARN_W_D, + LISA_XVSSRLN_B_H, + LISA_XVSSRLN_H_W, + LISA_XVSSRLN_W_D, + LISA_XVSSRAN_B_H, + LISA_XVSSRAN_H_W, + LISA_XVSSRAN_W_D, + LISA_XVSSRLRN_B_H, + LISA_XVSSRLRN_H_W, + LISA_XVSSRLRN_W_D, + LISA_XVSSRARN_B_H, + LISA_XVSSRARN_H_W, + LISA_XVSSRARN_W_D, + LISA_XVSSRLN_BU_H, + LISA_XVSSRLN_HU_W, + LISA_XVSSRLN_WU_D, + LISA_XVSSRAN_BU_H, + LISA_XVSSRAN_HU_W, + LISA_XVSSRAN_WU_D, + LISA_XVSSRLRN_BU_H, + LISA_XVSSRLRN_HU_W, + LISA_XVSSRLRN_WU_D, + LISA_XVSSRARN_BU_H, + LISA_XVSSRARN_HU_W, + LISA_XVSSRARN_WU_D, + LISA_XVBITCLR_B, + LISA_XVBITCLR_H, + LISA_XVBITCLR_W, + LISA_XVBITCLR_D, + LISA_XVBITSET_B, + LISA_XVBITSET_H, + LISA_XVBITSET_W, + LISA_XVBITSET_D, + LISA_XVBITREV_B, + LISA_XVBITREV_H, + LISA_XVBITREV_W, + LISA_XVBITREV_D, + LISA_XVBSTRC12_B, + LISA_XVBSTRC12_H, + LISA_XVBSTRC12_W, + LISA_XVBSTRC12_D, + LISA_XVBSTRC21_B, + LISA_XVBSTRC21_H, + LISA_XVBSTRC21_W, + LISA_XVBSTRC21_D, + LISA_XVPACKEV_B, + LISA_XVPACKEV_H, + LISA_XVPACKEV_W, + LISA_XVPACKEV_D, + LISA_XVPACKOD_B, + LISA_XVPACKOD_H, + LISA_XVPACKOD_W, + LISA_XVPACKOD_D, + LISA_XVILVL_B, + LISA_XVILVL_H, + LISA_XVILVL_W, + LISA_XVILVL_D, + LISA_XVILVH_B, + LISA_XVILVH_H, + LISA_XVILVH_W, + LISA_XVILVH_D, + LISA_XVPICKEV_B, + LISA_XVPICKEV_H, + LISA_XVPICKEV_W, + LISA_XVPICKEV_D, + LISA_XVPICKOD_B, + LISA_XVPICKOD_H, + LISA_XVPICKOD_W, + LISA_XVPICKOD_D, + LISA_XVREPLVE_B, + LISA_XVREPLVE_H, + LISA_XVREPLVE_W, + LISA_XVREPLVE_D, + LISA_XVEXTRCOL_B, + LISA_XVEXTRCOL_H, + LISA_XVEXTRCOL_W, + LISA_XVEXTRCOL_D, + LISA_XVAND_V, + LISA_XVOR_V, + LISA_XVXOR_V, + LISA_XVNOR_V, + LISA_XVANDN_V, + LISA_XVORN_V, + LISA_XVRANDSIGN_B, + LISA_XVRANDSIGN_H, + LISA_XVRORSIGN_B, + LISA_XVRORSIGN_H, + LISA_XVFRSTP_B, + LISA_XVFRSTP_H, + LISA_XVCLRSTRR_V, + LISA_XVCLRSTRV_V, + LISA_XVADD_Q, + LISA_XVSUB_Q, + LISA_XVSIGNCOV_B, + LISA_XVSIGNCOV_H, + LISA_XVSIGNCOV_W, + LISA_XVSIGNCOV_D, + LISA_XVFADD_S, + LISA_XVFADD_D, + LISA_XVFSUB_S, + LISA_XVFSUB_D, + LISA_XVFADDSUB_S, + LISA_XVFADDSUB_D, + LISA_XVFSUBADD_S, + LISA_XVFSUBADD_D, + LISA_XVFMUL_S, + LISA_XVFMUL_D, + LISA_XVFDIV_S, + LISA_XVFDIV_D, + LISA_XVFMAX_S, + LISA_XVFMAX_D, + LISA_XVFMIN_S, + LISA_XVFMIN_D, + LISA_XVFMAXA_S, + LISA_XVFMAXA_D, + LISA_XVFMINA_S, + LISA_XVFMINA_D, + LISA_XVFSCALEB_S, + LISA_XVFSCALEB_D, + LISA_XVFCVT_H_S, + LISA_XVFCVT_S_D, + LISA_XVFFINT_S_L, + LISA_XVFTINT_W_D, + LISA_XVFTINTRM_W_D, + LISA_XVFTINTRP_W_D, + LISA_XVFTINTRZ_W_D, + LISA_XVFTINTRNE_W_D, + LISA_XVHADD4_H_BU, + LISA_XVSHUF4_W, + LISA_XVSHUF2_D, + LISA_XVPMUL_W, + LISA_XVPMUL_D, + LISA_XVPMUH_W, + LISA_XVPMUH_D, + LISA_XVPMULACC_W, + LISA_XVPMULACC_D, + LISA_XVPMUHACC_W, + LISA_XVPMUHACC_D, + LISA_XVPMULWL_H_B, + LISA_XVPMULWL_W_H, + LISA_XVPMULWL_D_W, + LISA_XVPMULWL_Q_D, + LISA_XVPMULWH_H_B, + LISA_XVPMULWH_W_H, + LISA_XVPMULWH_D_W, + LISA_XVPMULWH_Q_D, + LISA_XVPMADDWL_H_B, + LISA_XVPMADDWL_W_H, + LISA_XVPMADDWL_D_W, + LISA_XVPMADDWL_Q_D, + LISA_XVPMADDWH_H_B, + LISA_XVPMADDWH_W_H, + LISA_XVPMADDWH_D_W, + LISA_XVPMADDWH_Q_D, + LISA_XVPDP2_Q_D, + LISA_XVPDP2ADD_Q_D, + LISA_XVCDP4_RE_D_H, + LISA_XVCDP4_IM_D_H, + LISA_XVCDP4ADD_RE_D_H, + LISA_XVCDP4ADD_IM_D_H, + LISA_XVCDP2_RE_Q_W, + LISA_XVCDP2_IM_Q_W, + LISA_XVCDP2ADD_RE_Q_W, + LISA_XVCDP2ADD_IM_Q_W, + LISA_XVSIGNSEL_W, + LISA_XVSIGNSEL_D, + LISA_XVSHUF_H, + LISA_XVSHUF_W, + LISA_XVSHUF_D, + LISA_XVPERM_W, + LISA_XVSEQI_B, + LISA_XVSEQI_H, + LISA_XVSEQI_W, + LISA_XVSEQI_D, + LISA_XVSLEI_B, + LISA_XVSLEI_H, + LISA_XVSLEI_W, + LISA_XVSLEI_D, + LISA_XVSLEI_BU, + LISA_XVSLEI_HU, + LISA_XVSLEI_WU, + LISA_XVSLEI_DU, + LISA_XVSLTI_B, + LISA_XVSLTI_H, + LISA_XVSLTI_W, + LISA_XVSLTI_D, + LISA_XVSLTI_BU, + LISA_XVSLTI_HU, + LISA_XVSLTI_WU, + LISA_XVSLTI_DU, + LISA_XVADDI_BU, + LISA_XVADDI_HU, + LISA_XVADDI_WU, + LISA_XVADDI_DU, + LISA_XVSUBI_BU, + LISA_XVSUBI_HU, + LISA_XVSUBI_WU, + LISA_XVSUBI_DU, + LISA_XVBSLL_V, + LISA_XVBSRL_V, + LISA_XVMAXI_B, + LISA_XVMAXI_H, + LISA_XVMAXI_W, + LISA_XVMAXI_D, + LISA_XVMINI_B, + LISA_XVMINI_H, + LISA_XVMINI_W, + LISA_XVMINI_D, + LISA_XVMAXI_BU, + LISA_XVMAXI_HU, + LISA_XVMAXI_WU, + LISA_XVMAXI_DU, + LISA_XVMINI_BU, + LISA_XVMINI_HU, + LISA_XVMINI_WU, + LISA_XVMINI_DU, + LISA_XVRANDSIGNI_B, + LISA_XVRANDSIGNI_H, + LISA_XVRORSIGNI_B, + LISA_XVRORSIGNI_H, + LISA_XVFRSTPI_B, + LISA_XVFRSTPI_H, + LISA_XVCLRSTRI_V, + LISA_XVMEPATMSK_V, + LISA_XVCLO_B, + LISA_XVCLO_H, + LISA_XVCLO_W, + LISA_XVCLO_D, + LISA_XVCLZ_B, + LISA_XVCLZ_H, + LISA_XVCLZ_W, + LISA_XVCLZ_D, + LISA_XVPCNT_B, + LISA_XVPCNT_H, + LISA_XVPCNT_W, + LISA_XVPCNT_D, + LISA_XVNEG_B, + LISA_XVNEG_H, + LISA_XVNEG_W, + LISA_XVNEG_D, + LISA_XVMSKLTZ_B, + LISA_XVMSKLTZ_H, + LISA_XVMSKLTZ_W, + LISA_XVMSKLTZ_D, + LISA_XVMSKGEZ_B, + LISA_XVMSKNZ_B, + LISA_XVMSKCOPY_B, + LISA_XVMSKFILL_B, + LISA_XVFRSTM_B, + LISA_XVFRSTM_H, + LISA_XVSETEQZ_V, + LISA_XVSETNEZ_V, + LISA_XVSETANYEQZ_B, + LISA_XVSETANYEQZ_H, + LISA_XVSETANYEQZ_W, + LISA_XVSETANYEQZ_D, + LISA_XVSETALLNEZ_B, + LISA_XVSETALLNEZ_H, + LISA_XVSETALLNEZ_W, + LISA_XVSETALLNEZ_D, + LISA_XVFLOGB_S, + LISA_XVFLOGB_D, + LISA_XVFCLASS_S, + LISA_XVFCLASS_D, + LISA_XVFSQRT_S, + LISA_XVFSQRT_D, + LISA_XVFRECIP_S, + LISA_XVFRECIP_D, + LISA_XVFRSQRT_S, + LISA_XVFRSQRT_D, + LISA_XVFRINT_S, + LISA_XVFRINT_D, + LISA_XVFRINTRM_S, + LISA_XVFRINTRM_D, + LISA_XVFRINTRP_S, + LISA_XVFRINTRP_D, + LISA_XVFRINTRZ_S, + LISA_XVFRINTRZ_D, + LISA_XVFRINTRNE_S, + LISA_XVFRINTRNE_D, + LISA_XVEXTL_W_B, + LISA_XVEXTL_D_B, + LISA_XVEXTL_D_H, + LISA_XVEXTL_W_BU, + LISA_XVEXTL_D_BU, + LISA_XVEXTL_D_HU, + LISA_XVHADD8_D_BU, + LISA_XVHMINPOS_W_HU, + LISA_XVHMINPOS_D_HU, + LISA_XVHMINPOS_Q_HU, + LISA_XVCLRTAIL_B, + LISA_XVCLRTAIL_H, + LISA_XVFCVTL_S_H, + LISA_XVFCVTH_S_H, + LISA_XVFCVTL_D_S, + LISA_XVFCVTH_D_S, + LISA_XVFFINT_S_W, + LISA_XVFFINT_S_WU, + LISA_XVFFINT_D_L, + LISA_XVFFINT_D_LU, + LISA_XVFFINTL_D_W, + LISA_XVFFINTH_D_W, + LISA_XVFTINT_W_S, + LISA_XVFTINT_L_D, + LISA_XVFTINTRM_W_S, + LISA_XVFTINTRM_L_D, + LISA_XVFTINTRP_W_S, + LISA_XVFTINTRP_L_D, + LISA_XVFTINTRZ_W_S, + LISA_XVFTINTRZ_L_D, + LISA_XVFTINTRNE_W_S, + LISA_XVFTINTRNE_L_D, + LISA_XVFTINT_WU_S, + LISA_XVFTINT_LU_D, + LISA_XVFTINTRZ_WU_S, + LISA_XVFTINTRZ_LU_D, + LISA_XVFTINTL_L_S, + LISA_XVFTINTH_L_S, + LISA_XVFTINTRML_L_S, + LISA_XVFTINTRMH_L_S, + LISA_XVFTINTRPL_L_S, + LISA_XVFTINTRPH_L_S, + LISA_XVFTINTRZL_L_S, + LISA_XVFTINTRZH_L_S, + LISA_XVFTINTRNEL_L_S, + LISA_XVFTINTRNEH_L_S, + LISA_XVEXTH_H_B, + LISA_XVEXTH_W_H, + LISA_XVEXTH_D_W, + LISA_XVEXTH_Q_D, + LISA_XVEXTH_HU_BU, + LISA_XVEXTH_WU_HU, + LISA_XVEXTH_DU_WU, + LISA_XVEXTH_QU_DU, + LISA_XVREPLGR2VR_B, + LISA_XVREPLGR2VR_H, + LISA_XVREPLGR2VR_W, + LISA_XVREPLGR2VR_D, + LISA_VEXT2XV_H_B, + LISA_VEXT2XV_W_B, + LISA_VEXT2XV_D_B, + LISA_VEXT2XV_W_H, + LISA_VEXT2XV_D_H, + LISA_VEXT2XV_D_W, + LISA_VEXT2XV_HU_BU, + LISA_VEXT2XV_WU_BU, + LISA_VEXT2XV_DU_BU, + LISA_VEXT2XV_WU_HU, + LISA_VEXT2XV_DU_HU, + LISA_VEXT2XV_DU_WU, + LISA_XVHSELI_D, + LISA_XVROTRI_B, + LISA_XVROTRI_H, + LISA_XVROTRI_W, + LISA_XVROTRI_D, + LISA_XVSRLRI_B, + LISA_XVSRLRI_H, + LISA_XVSRLRI_W, + LISA_XVSRLRI_D, + LISA_XVSRARI_B, + LISA_XVSRARI_H, + LISA_XVSRARI_W, + LISA_XVSRARI_D, + LISA_XVINSGR2VR_W, + LISA_XVINSGR2VR_D, + LISA_XVPICKVE2GR_W, + LISA_XVPICKVE2GR_D, + LISA_XVPICKVE2GR_WU, + LISA_XVPICKVE2GR_DU, + LISA_XVREPL128VEI_B, + LISA_XVREPL128VEI_H, + LISA_XVREPL128VEI_W, + LISA_XVREPL128VEI_D, + LISA_XVEXTRCOLI_B, + LISA_XVEXTRCOLI_H, + LISA_XVEXTRCOLI_W, + LISA_XVEXTRCOLI_D, + LISA_XVINSVE0_W, + LISA_XVINSVE0_D, + LISA_XVPICKVE_W, + LISA_XVPICKVE_D, + LISA_XVREPLVE0_B, + LISA_XVREPLVE0_H, + LISA_XVREPLVE0_W, + LISA_XVREPLVE0_D, + LISA_XVREPLVE0_Q, + LISA_XVSLLWIL_H_B, + LISA_XVSLLWIL_W_H, + LISA_XVSLLWIL_D_W, + LISA_XVEXTL_Q_D, + LISA_XVSLLWIL_HU_BU, + LISA_XVSLLWIL_WU_HU, + LISA_XVSLLWIL_DU_WU, + LISA_XVEXTL_QU_DU, + LISA_XVBITCLRI_B, + LISA_XVBITCLRI_H, + LISA_XVBITCLRI_W, + LISA_XVBITCLRI_D, + LISA_XVBITSETI_B, + LISA_XVBITSETI_H, + LISA_XVBITSETI_W, + LISA_XVBITSETI_D, + LISA_XVBITREVI_B, + LISA_XVBITREVI_H, + LISA_XVBITREVI_W, + LISA_XVBITREVI_D, + LISA_XVBSTRC12I_B, + LISA_XVBSTRC12I_H, + LISA_XVBSTRC12I_W, + LISA_XVBSTRC12I_D, + LISA_XVBSTRC21I_B, + LISA_XVBSTRC21I_H, + LISA_XVBSTRC21I_W, + LISA_XVBSTRC21I_D, + LISA_XVSAT_B, + LISA_XVSAT_H, + LISA_XVSAT_W, + LISA_XVSAT_D, + LISA_XVSAT_BU, + LISA_XVSAT_HU, + LISA_XVSAT_WU, + LISA_XVSAT_DU, + LISA_XVSLLI_B, + LISA_XVSLLI_H, + LISA_XVSLLI_W, + LISA_XVSLLI_D, + LISA_XVSRLI_B, + LISA_XVSRLI_H, + LISA_XVSRLI_W, + LISA_XVSRLI_D, + LISA_XVSRAI_B, + LISA_XVSRAI_H, + LISA_XVSRAI_W, + LISA_XVSRAI_D, + LISA_XVSRLRNENI_B_H, + LISA_XVSRLRNENI_H_W, + LISA_XVSRLRNENI_W_D, + LISA_XVSRLRNENI_D_Q, + LISA_XVSRARNENI_B_H, + LISA_XVSRARNENI_H_W, + LISA_XVSRARNENI_W_D, + LISA_XVSRARNENI_D_Q, + LISA_XVSRLNI_B_H, + LISA_XVSRLNI_H_W, + LISA_XVSRLNI_W_D, + LISA_XVSRLNI_D_Q, + LISA_XVSRLRNI_B_H, + LISA_XVSRLRNI_H_W, + LISA_XVSRLRNI_W_D, + LISA_XVSRLRNI_D_Q, + LISA_XVSSRLNI_B_H, + LISA_XVSSRLNI_H_W, + LISA_XVSSRLNI_W_D, + LISA_XVSSRLNI_D_Q, + LISA_XVSSRLNI_BU_H, + LISA_XVSSRLNI_HU_W, + LISA_XVSSRLNI_WU_D, + LISA_XVSSRLNI_DU_Q, + LISA_XVSSRLRNI_B_H, + LISA_XVSSRLRNI_H_W, + LISA_XVSSRLRNI_W_D, + LISA_XVSSRLRNI_D_Q, + LISA_XVSSRLRNI_BU_H, + LISA_XVSSRLRNI_HU_W, + LISA_XVSSRLRNI_WU_D, + LISA_XVSSRLRNI_DU_Q, + LISA_XVSRANI_B_H, + LISA_XVSRANI_H_W, + LISA_XVSRANI_W_D, + LISA_XVSRANI_D_Q, + LISA_XVSRARNI_B_H, + LISA_XVSRARNI_H_W, + LISA_XVSRARNI_W_D, + LISA_XVSRARNI_D_Q, + LISA_XVSSRANI_B_H, + LISA_XVSSRANI_H_W, + LISA_XVSSRANI_W_D, + LISA_XVSSRANI_D_Q, + LISA_XVSSRANI_BU_H, + LISA_XVSSRANI_HU_W, + LISA_XVSSRANI_WU_D, + LISA_XVSSRANI_DU_Q, + LISA_XVSSRARNI_B_H, + LISA_XVSSRARNI_H_W, + LISA_XVSSRARNI_W_D, + LISA_XVSSRARNI_D_Q, + LISA_XVSSRARNI_BU_H, + LISA_XVSSRARNI_HU_W, + LISA_XVSSRARNI_WU_D, + LISA_XVSSRARNI_DU_Q, + LISA_XVSSRLRNENI_B_H, + LISA_XVSSRLRNENI_H_W, + LISA_XVSSRLRNENI_W_D, + LISA_XVSSRLRNENI_D_Q, + LISA_XVSSRLRNENI_BU_H, + LISA_XVSSRLRNENI_HU_W, + LISA_XVSSRLRNENI_WU_D, + LISA_XVSSRLRNENI_DU_Q, + LISA_XVSSRARNENI_B_H, + LISA_XVSSRARNENI_H_W, + LISA_XVSSRARNENI_W_D, + LISA_XVSSRARNENI_D_Q, + LISA_XVSSRARNENI_BU_H, + LISA_XVSSRARNENI_HU_W, + LISA_XVSSRARNENI_WU_D, + LISA_XVSSRARNENI_DU_Q, + LISA_XVEXTRINS_D, + LISA_XVEXTRINS_W, + LISA_XVEXTRINS_H, + LISA_XVEXTRINS_B, + LISA_XVSHUF4I_B, + LISA_XVSHUF4I_H, + LISA_XVSHUF4I_W, + LISA_XVSHUF4I_D, + LISA_XVSHUFI1_B, + LISA_XVSHUFI2_B, + LISA_XVSHUFI3_B, + LISA_XVSHUFI4_B, + LISA_XVSHUFI1_H, + LISA_XVSHUFI2_H, + LISA_XVSELI_H, + LISA_XVSELI_W, + LISA_XVSELI_D, + LISA_XVBITSELI_B, + LISA_XVBITMVZI_B, + LISA_XVBITMVNZI_B, + LISA_XVANDI_B, + LISA_XVORI_B, + LISA_XVXORI_B, + LISA_XVNORI_B, + LISA_XVLDI, + LISA_XVPERMI_W, + LISA_XVPERMI_D, + LISA_XVPERMI_Q, + LISA_ENDING, +} IR2_OPCODE; + +/* IR2_OPND_TYPE */ +typedef enum { + IR2_OPND_NONE = 80, + IR2_OPND_GPR, + IR2_OPND_SCR, + IR2_OPND_FPR, + IR2_OPND_FCSR, /* immediate used in cfc1/ctc1 */ + IR2_OPND_CC, /* condition code, FCC field in FCSR */ + IR2_OPND_IMM, /* immediate */ + IR2_OPND_LABEL, + IR2_OPND_MEM, /* middle type. not used as backend */ +} IR2_OPND_TYPE; + +/* Operand Bit Field Type */ +typedef enum { + OPD_INVALID = 0, + FCC_CA, + FCC_CD, + FCC_CJ, + IMM_CODE, + IMM_CONDF, + IMM_CONDH, + IMM_CONDL, + OPD_CSR, + FPR_FA, + OPD_FCSRH, + OPD_FCSRL, + FPR_FD, + FPR_FJ, + FPR_FK, + IMM_HINTL, + IMM_HINTS, + IMM_I13, + IMM_IDXS, + IMM_IDXM, + IMM_IDXL, + IMM_IDXLL, + IMM_LEVEL, + IMM_LSBD, + IMM_LSBW, + IMM_MODE, + IMM_MSBD, + IMM_MSBW, + IMM_OFFS, + IMM_OFFL, + IMM_OFFLL, + OPD_OPCACHE, + IMM_OPX86, + IMM_PTR, + GPR_RD, + GPR_RJ, + GPR_RK, + IMM_SA2, + IMM_SA3, + SCR_SD, + IMM_SEQ, + IMM_SI10, + IMM_SI11, + IMM_SI12, + IMM_SI14, + IMM_SI16, + IMM_SI20, + IMM_SI5, + IMM_SI8, + IMM_SI9, + SCR_SJ, + IMM_UI1, + IMM_UI12, + IMM_UI2, + IMM_UI3, + IMM_UI4, + IMM_UI5H, + IMM_UI5L, + IMM_UI6, + IMM_UI7, + IMM_UI8, + FPR_VA, + FPR_VD, + FPR_VJ, + FPR_VK, + FPR_XA, + FPR_XD, + FPR_XJ, + FPR_XK, +} GM_OPERAND_TYPE; + +extern const IR2_OPND_TYPE ir2_opnd_type_table[]; + +/* Opcode Format */ +typedef struct pair { + int start; + int end; +} pair; + +typedef struct { + GM_OPERAND_TYPE type; + pair bit_range_0; + pair bit_range_1; /* some branch offset is splited into 2 parts */ +} GM_OPERAND_PLACE_RELATION; + +typedef struct { + IR2_OPCODE op; + uint32_t opcode; + GM_OPERAND_TYPE opnd[4]; +} GM_LA_OPCODE_FORMAT; + +extern const GM_OPERAND_PLACE_RELATION bit_field_table[]; + +extern const GM_LA_OPCODE_FORMAT lisa_format_table[]; + +typedef IR2_OPCODE LA_OPCODE; +typedef IR2_OPND_TYPE LA_OPND_TYPE; + +typedef struct { + int val; +} LA_OPND; + +typedef struct Ins { + LA_OPCODE op; + LA_OPND opnd[4]; + int opnd_count; + + /* linked list */ + struct Ins *prev; + struct Ins *next; +} Ins; + +uint32_t la_assemble(Ins *ins); + +void la_disasm(uint32_t opcode, Ins *ins); +LA_OPCODE get_ins_op(uint32_t insn); +int extract_opnd_val(uint32_t insn, GM_OPERAND_TYPE type); + +LA_OPND_TYPE get_opnd_type(Ins *ins, int i); + +const char *ins_name(Ins *ins); +const char *gpr_name(uint32_t gpr); + +void sprint_op(LA_OPCODE op, char *msg); +void sprint_ins(Ins *ins, char *msg); +void sprint_disasm(uint32_t opcode, char *msg); + +void print_op(LA_OPCODE op); +void print_ins(Ins *ins); +void print_disasm(uint32_t opcode); + +#endif diff --git a/unittest/TestLoongArch64Emitter.cpp b/unittest/TestLoongArch64Emitter.cpp new file mode 100644 index 0000000000..a01e122601 --- /dev/null +++ b/unittest/TestLoongArch64Emitter.cpp @@ -0,0 +1,80 @@ +// Copyright (c) 2025- PPSSPP Project. + +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, version 2.0 or later versions. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License 2.0 for more details. + +// A copy of the GPL 2.0 should have been included with the program. +// If not, see http://www.gnu.org/licenses/ + +// Official git repository and contact information can be found at +// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. + +#include +#include "Common/CPUDetect.h" +#include "Common/LoongArch64Emitter.h" +#include "UnitTest.h" + +bool TestLoongArch64Emitter(){ + using namespace LoongArch64Gen; + + cpu_info.LOONGARCH_COMPLEX = true; + cpu_info.LOONGARCH_LAM = true; + cpu_info.LOONGARCH_UAL = true; + cpu_info.LOONGARCH_FPU = true; + cpu_info.LOONGARCH_LSX = true; + cpu_info.LOONGARCH_LASX = true; + cpu_info.LOONGARCH_CRC32 = true; + cpu_info.LOONGARCH_COMPLEX = true; + cpu_info.LOONGARCH_CRYPTO = true; + cpu_info.LOONGARCH_LVZ = true; + cpu_info.LOONGARCH_LBT_X86 = true; + cpu_info.LOONGARCH_LBT_ARM = true; + cpu_info.LOONGARCH_LBT_MIPS = true; + cpu_info.LOONGARCH_PTW = true; + + u32 code[1024]; + LoongArch64Emitter emitter((u8 *)code, (u8 *)code); + + emitter.ADD_W(R12, R13, R14); // t0, t1, t2 + emitter.ADD_D(R12, R13, R14); // t0, t1, t2 + emitter.SUB_W(R12, R13, R14); // t0, t1, t2 + emitter.SUB_D(R12, R13, R14); // t0, t1, t2 + + emitter.ADDI_W(R12, R13, 1024); // t0, t1, 1024 + emitter.ADDI_D(R12, R13, 1024); // t0, t1, 1024 + emitter.ADDU16I_D(R12, R13, 16384); // t0, t1, 1024 + + emitter.ALSL_W(R12, R13, R14, 4); // t0, t1, t2, 4 + emitter.ALSL_D(R12, R13, R14, 4); // t0, t1, t2, 4 + emitter.ALSL_WU(R12, R13, R14, 4); // t0, t1, t2, 4 + + static constexpr uint32_t expected[] = { + 0x001039ac, // add.w + 0x0010b9ac, // add.d + 0x001139ac, // sub.w + 0x0011b9ac, // sub.d + + 0x029001ac, // addi.w + 0x02d001ac, // addi.d + 0x110001ac, // addiu16i.d + + 0x0005b9ac, // alsl.w + 0x002db9ac, // alsl.d + 0x0007b9ac, // alsl.wu + }; + + ptrdiff_t len = (u32 *)emitter.GetWritableCodePtr() - code; + EXPECT_EQ_INT(len, ARRAY_SIZE(expected)); + + for (ptrdiff_t i = 0; i < len; ++i) { + EXPECT_EQ_HEX(code[i], expected[i]); + } + + return true; +} \ No newline at end of file diff --git a/unittest/UnitTest.cpp b/unittest/UnitTest.cpp index be4b2deabc..d9c0d38877 100644 --- a/unittest/UnitTest.cpp +++ b/unittest/UnitTest.cpp @@ -1244,6 +1244,7 @@ bool TestArmEmitter(); bool TestArm64Emitter(); bool TestX64Emitter(); bool TestRiscVEmitter(); +bool TestLoongArch64Emitter(); bool TestShaderGenerators(); bool TestSoftwareGPUJit(); bool TestIRPassSimplify(); @@ -1262,6 +1263,9 @@ TestItem availableTests[] = { #endif #if PPSSPP_ARCH(AMD64) || PPSSPP_ARCH(X86) || PPSSPP_ARCH(RISCV64) TEST_ITEM(RiscVEmitter), +#endif +#if PPSSPP_ARCH(AMD64) || PPSSPP_ARCH(X86) || PPSSPP_ARCH(LOONGARCH64) + TEST_ITEM(LoongArch64Emitter), #endif TEST_ITEM(VertexJit), TEST_ITEM(Asin), diff --git a/unittest/UnitTests.vcxproj b/unittest/UnitTests.vcxproj index da341b86e7..0e643f6475 100644 --- a/unittest/UnitTests.vcxproj +++ b/unittest/UnitTests.vcxproj @@ -294,6 +294,7 @@ + @@ -347,4 +348,4 @@ - + \ No newline at end of file diff --git a/unittest/UnitTests.vcxproj.filters b/unittest/UnitTests.vcxproj.filters index eb084afaf0..6c7b2f460d 100644 --- a/unittest/UnitTests.vcxproj.filters +++ b/unittest/UnitTests.vcxproj.filters @@ -17,6 +17,7 @@ +