arm64jit: Add initial base for IR jit.

This works, but very slowly at this point.

Core/MIPS/ARM64/Arm64IRCompSystem.cpp

@@ -0,0 +1,147 @@
+// Copyright (c) 2023- PPSSPP Project.
+
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, version 2.0 or later versions.
+
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License 2.0 for more details.
+
+// A copy of the GPL 2.0 should have been included with the program.
+// If not, see http://www.gnu.org/licenses/
+
+// Official git repository and contact information can be found at
+// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
+
+#include "ppsspp_config.h"
+// In other words, PPSSPP_ARCH(ARM64) || DISASM_ALL.
+#if PPSSPP_ARCH(ARM64) || (PPSSPP_PLATFORM(WINDOWS) && !defined(__LIBRETRO__))
+
+#include "Common/Profiler/Profiler.h"
+#include "Core/Core.h"
+#include "Core/HLE/HLE.h"
+#include "Core/HLE/ReplaceTables.h"
+#include "Core/MemMap.h"
+#include "Core/MIPS/ARM64/Arm64IRJit.h"
+#include "Core/MIPS/ARM64/Arm64IRRegCache.h"
+
+// This file contains compilation for basic PC/downcount accounting, syscalls, debug funcs, etc.
+//
+// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
+// Currently known non working ones should have DISABLE.  No flags because that's in IR already.
+
+// #define CONDITIONAL_DISABLE { CompIR_Generic(inst); return; }
+#define CONDITIONAL_DISABLE {}
+#define DISABLE { CompIR_Generic(inst); return; }
+#define INVALIDOP { _assert_msg_(false, "Invalid IR inst %d", (int)inst.op); CompIR_Generic(inst); return; }
+
+namespace MIPSComp {
+
+using namespace Arm64Gen;
+using namespace Arm64IRJitConstants;
+
+void Arm64JitBackend::CompIR_Basic(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Downcount:
+	case IROp::SetConst:
+	case IROp::SetConstF:
+	case IROp::SetPC:
+	case IROp::SetPCConst:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void Arm64JitBackend::CompIR_Breakpoint(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Breakpoint:
+	case IROp::MemoryCheck:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void Arm64JitBackend::CompIR_System(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::Syscall:
+	case IROp::CallReplacement:
+	case IROp::Break:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void Arm64JitBackend::CompIR_Transfer(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	switch (inst.op) {
+	case IROp::SetCtrlVFPU:
+	case IROp::SetCtrlVFPUReg:
+	case IROp::SetCtrlVFPUFReg:
+	case IROp::FpCondFromReg:
+	case IROp::FpCondToReg:
+	case IROp::FpCtrlFromReg:
+	case IROp::FpCtrlToReg:
+	case IROp::VfpuCtrlToReg:
+	case IROp::FMovFromGPR:
+	case IROp::FMovToGPR:
+		CompIR_Generic(inst);
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+void Arm64JitBackend::CompIR_ValidateAddress(IRInst inst) {
+	CONDITIONAL_DISABLE;
+
+	bool isWrite = inst.src2 & 1;
+	int alignment = 0;
+	switch (inst.op) {
+	case IROp::ValidateAddress8:
+		alignment = 1;
+		break;
+
+	case IROp::ValidateAddress16:
+		alignment = 2;
+		break;
+
+	case IROp::ValidateAddress32:
+		alignment = 4;
+		break;
+
+	case IROp::ValidateAddress128:
+		alignment = 16;
+		break;
+
+	default:
+		INVALIDOP;
+		break;
+	}
+}
+
+} // namespace MIPSComp
+
+#endif