From 1a2edc67d07ca63e6659fa38b9675e2c415c609f Mon Sep 17 00:00:00 2001
From: Henrik Rydgard <hrydgard@gmail.com>
Date: Sun, 8 May 2016 02:03:11 +0200
Subject: [PATCH] Add support for float store/load

---
 Core/MIPS/IR/IRCompFPU.cpp | 22 +++++++++++++++++++++-
 Core/MIPS/IR/IRInst.cpp    |  8 ++++++++
 Core/MemMap.h              | 16 ++++++++++++++++
 3 files changed, 45 insertions(+), 1 deletion(-)

diff --git a/Core/MIPS/IR/IRCompFPU.cpp b/Core/MIPS/IR/IRCompFPU.cpp
index f94bddbaad..c4353dd983 100644
--- a/Core/MIPS/IR/IRCompFPU.cpp
+++ b/Core/MIPS/IR/IRCompFPU.cpp
@@ -73,7 +73,27 @@ void IRJit::Comp_FPU3op(MIPSOpcode op) {
 }
 
 void IRJit::Comp_FPULS(MIPSOpcode op) {
-	DISABLE;
+	CONDITIONAL_DISABLE;
+	s32 offset = _IMM16;
+	int ft = _FT;
+	MIPSGPReg rs = _RS;
+
+	switch (op >> 26) {
+	case 49: //FI(ft) = Memory::Read_U32(addr); break; //lwc1
+	{
+		ir.Write(IROp::LoadFloat, ft, rs, ir.AddConstant(offset));
+	}
+	break;
+	case 57: //Memory::Write_U32(FI(ft), addr); break; //swc1
+	{
+		ir.Write(IROp::StoreFloat, ft, rs, ir.AddConstant(offset));
+	}
+	break;
+
+	default:
+		_dbg_assert_msg_(CPU, 0, "Trying to interpret FPULS instruction that can't be interpreted");
+		break;
+	}
 }
 
 void IRJit::Comp_FPUComp(MIPSOpcode op) {
diff --git a/Core/MIPS/IR/IRInst.cpp b/Core/MIPS/IR/IRInst.cpp
index cba03ae795..439c0b25fd 100644
--- a/Core/MIPS/IR/IRInst.cpp
+++ b/Core/MIPS/IR/IRInst.cpp
@@ -61,9 +61,11 @@ static const IRMeta irMeta[] = {
 	{ IROp::Load16, "Load16", "GGC" },
 	{ IROp::Load16Ext, "Load16Ext", "GGC" },
 	{ IROp::Load32, "Load32", "GGC" },
+	{ IROp::LoadFloat, "LoadFloat", "FGC" },
 	{ IROp::Store8, "Store8", "GGC" },
 	{ IROp::Store16, "Store16", "GGC" },
 	{ IROp::Store32, "Store32", "GGC" },
+	{ IROp::StoreFloat, "StoreFloat", "FGC" },
 	{ IROp::FAdd, "FAdd", "FFF" },
 	{ IROp::FSub, "FSub", "FFF" },
 	{ IROp::FMul, "FMul", "FFF" },
@@ -176,6 +178,9 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
 		case IROp::Load32:
 			mips->r[inst->dest] = Memory::ReadUnchecked_U32(mips->r[inst->src1] + constPool[inst->src2]);
 			break;
+		case IROp::LoadFloat:
+			mips->f[inst->dest] = Memory::ReadUnchecked_Float(mips->r[inst->src1] + constPool[inst->src2]);
+			break;
 
 		case IROp::Store8:
 			Memory::WriteUnchecked_U8(mips->r[inst->src3], mips->r[inst->src1] + constPool[inst->src2]);
@@ -186,6 +191,9 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, const u32 *constPool, int c
 		case IROp::Store32:
 			Memory::WriteUnchecked_U32(mips->r[inst->src3], mips->r[inst->src1] + constPool[inst->src2]);
 			break;
+		case IROp::StoreFloat:
+			Memory::WriteUnchecked_Float(mips->f[inst->src3], mips->r[inst->src1] + constPool[inst->src2]);
+			break;
 
 		case IROp::ShlImm:
 			mips->r[inst->dest] = mips->r[inst->src1] << (int)inst->src2;
diff --git a/Core/MemMap.h b/Core/MemMap.h
index c49a41d119..c2b4ad3b12 100644
--- a/Core/MemMap.h
+++ b/Core/MemMap.h
@@ -186,6 +186,14 @@ inline u32 ReadUnchecked_U32(const u32 address) {
 #endif
 }
 
+inline float ReadUnchecked_Float(const u32 address) {
+#ifdef _ARCH_32
+	return *(float *)(base + (address & MEMVIEW32_MASK));
+#else
+	return *(float *)(base + address);
+#endif
+}
+
 inline u16 ReadUnchecked_U16(const u32 address) {
 #ifdef _ARCH_32
 	return *(u16_le *)(base + (address & MEMVIEW32_MASK));
@@ -210,6 +218,14 @@ inline void WriteUnchecked_U32(u32 data, u32 address) {
 #endif
 }
 
+inline void WriteUnchecked_Float(float data, u32 address) {
+#ifdef _ARCH_32
+	*(float *)(base + (address & MEMVIEW32_MASK)) = data;
+#else
+	*(float *)(base + address) = data;
+#endif
+}
+
 inline void WriteUnchecked_U16(u16 data, u32 address) {
 #ifdef _ARCH_32
 	*(u16_le *)(base + (address & MEMVIEW32_MASK)) = data;