From 175ceef58326213d83239de6fd49450989a2b392 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sat, 30 Mar 2019 10:23:37 -0700 Subject: [PATCH] interp: Cleanup vsocp size handling. --- Core/MIPS/IR/IRCompVFPU.cpp | 2 +- Core/MIPS/MIPSIntVFPU.cpp | 13 +++++++------ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/Core/MIPS/IR/IRCompVFPU.cpp b/Core/MIPS/IR/IRCompVFPU.cpp index c964628c72..eb73cb27fa 100644 --- a/Core/MIPS/IR/IRCompVFPU.cpp +++ b/Core/MIPS/IR/IRCompVFPU.cpp @@ -1905,7 +1905,7 @@ namespace MIPSComp { void IRFrontend::Comp_Vocp(MIPSOpcode op) { CONDITIONAL_DISABLE(VFPU_VEC); - if (js.HasUnknownPrefix()) { + if (js.HasUnknownPrefix() || !IsPrefixWithinSize(js.prefixS, op) || js.HasTPrefix() || (js.prefixS & VFPU_NEGATE(1, 1, 1, 1)) != 0) { DISABLE; } diff --git a/Core/MIPS/MIPSIntVFPU.cpp b/Core/MIPS/MIPSIntVFPU.cpp index d6e0230b67..0b8be5894d 100644 --- a/Core/MIPS/MIPSIntVFPU.cpp +++ b/Core/MIPS/MIPSIntVFPU.cpp @@ -579,8 +579,7 @@ namespace MIPSInt EatPrefixes(); } - void Int_Vocp(MIPSOpcode op) - { + void Int_Vocp(MIPSOpcode op) { float s[4], t[4], d[4]; int vd = _VD; int vs = _VS; @@ -601,19 +600,21 @@ namespace MIPSInt // Always positive NaN. Note that s is always negated from the registers. d[i] = my_isnan(s[i]) ? fabsf(s[i]) : t[i] + s[i]; } + RetainInvalidSwizzleST(d, sz); ApplyPrefixD(d, sz); WriteVector(d, sz, vd); PC += 4; EatPrefixes(); } - void Int_Vsocp(MIPSOpcode op) - { + void Int_Vsocp(MIPSOpcode op) { float s[4], t[4], d[4]; int vd = _VD; int vs = _VS; VectorSize sz = GetVecSize(op); - VectorSize outSize = GetDoubleVectorSize(sz); + VectorSize outSize = GetDoubleVectorSizeSafe(sz); + if (outSize == V_Invalid) + outSize = V_Quad; ReadVector(s, sz, vs); // S prefix forces negate in even/odd and xxyy swizzle. @@ -636,7 +637,7 @@ namespace MIPSInt d[2] = nanclamp(t[2] + s[2], 0.0f, 1.0f); d[3] = nanclamp(t[3] + s[3], 0.0f, 1.0f); } - ApplyPrefixD(d, sz); + ApplyPrefixD(d, sz, true); WriteVector(d, outSize, vd); PC += 4; EatPrefixes();