CPU: Give each MIPSState an address space for its memory accesses

Memory::AddressSpace is where a CPU's addresses point (base) and its block
shadow, with the unchecked accessors and block shadow helpers as methods. The
main CPU's is Memory::g_mainSpace, kept in step with Memory::base and
blockShadow, and MIPSState::space points at it.

The CPU cores now go through their state's space instead of the globals: the
interpreter's and IR interpreter's loads and stores (which also saves the IR
interpreter reloading the global base), the IR interpreter's block lookup,
the block table's shadow entries, and the native JITs' memory base register,
block shadow lookups and pointerified registers. Address validity and
everything outside the cores still use the globals.

No change for the main CPU; this is so another CPU (the Media Engine) can see
memory differently. Benchmarked against master (God of War: Chains of
Olympus, Tekken 6): JIT instructions retired within noise, IR interpreter
2% fewer.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>

Core/MIPS/x86/X64IRCompSystem.cpp

@@ -400,7 +400,7 @@ void X64JitBackend::CompIR_ValidateAddress(IRInst inst) {
 	if (regs_.IsGPRMappedAsPointer(inst.src1)) {
 		LEA(PTRBITS, SCRATCH1, MDisp(regs_.RXPtr(inst.src1), inst.constant));
 #if defined(MASKED_PSP_MEMORY)
-		SUB(PTRBITS, R(SCRATCH1), ImmPtr(Memory::base));
+		SUB(PTRBITS, R(SCRATCH1), ImmPtr(mips_->space->base));
 #else
 		SUB(PTRBITS, R(SCRATCH1), R(MEMBASEREG));
 #endif