From 028e85dc924400a94ba5ed5859cbbf823d6cca01 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Thu, 7 Mar 2013 00:40:38 -0800 Subject: [PATCH] Cleanup some differences between the two jits. --- Core/MIPS/ARM/ArmCompALU.cpp | 27 +++++++++++++++++++-------- Core/MIPS/ARM/ArmCompBranch.cpp | 4 ++-- Core/MIPS/ARM/ArmJit.cpp | 10 +++++----- Core/MIPS/x86/CompALU.cpp | 22 ++++++++++++++++------ 4 files changed, 42 insertions(+), 21 deletions(-) diff --git a/Core/MIPS/ARM/ArmCompALU.cpp b/Core/MIPS/ARM/ArmCompALU.cpp index 8c3a865892..494190fd42 100644 --- a/Core/MIPS/ARM/ArmCompALU.cpp +++ b/Core/MIPS/ARM/ArmCompALU.cpp @@ -69,6 +69,10 @@ namespace MIPSComp int rt = _RT; int rs = _RS; + // noop, won't write to ZERO. + if (rt == 0) + return; + switch (op >> 26) { case 8: // same as addiu? @@ -76,8 +80,6 @@ namespace MIPSComp { if (gpr.IsImm(rs)) { gpr.SetImm(rt, gpr.GetImm(rs) + simm); - } else if (rs == 0) { // add to zero register = immediate - gpr.SetImm(rt, (u32)simm); } else { gpr.MapDirtyIn(rt, rs); Operand2 op2; @@ -186,6 +188,10 @@ namespace MIPSComp int rs = _RS; int rd = _RD; + // noop, won't write to ZERO. + if (rd == 0) + return; + switch (op & 63) { case 10: //if (!R(rt)) R(rd) = R(rs); break; //movz @@ -235,13 +241,13 @@ namespace MIPSComp } break; - // case 32: //R(rd) = R(rs) + R(rt); break; //add + case 32: //R(rd) = R(rs) + R(rt); break; //add case 33: //R(rd) = R(rs) + R(rt); break; //addu // Some optimized special cases - if (rs == 0) { + if (gpr.IsImm(rs) && gpr.GetImm(rs) == 0) { gpr.MapDirtyIn(rd, rt); MOV(gpr.R(rd), gpr.R(rt)); - } else if (rt == 0) { + } else if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0) { gpr.MapDirtyIn(rd, rs); MOV(gpr.R(rd), gpr.R(rs)); } else { @@ -269,7 +275,7 @@ namespace MIPSComp case 39: // R(rd) = ~(R(rs) | R(rt)); break; //nor gpr.MapDirtyInIn(rd, rs, rt); - if (rt == 0) { + if (gpr.IsImm(rt) && gpr.GetImm(rt) == 0) { MVN(gpr.R(rd), gpr.R(rs)); } else { ORR(gpr.R(rd), gpr.R(rs), gpr.R(rt)); @@ -318,7 +324,6 @@ namespace MIPSComp break; default: - // gpr.UnlockAll(); Comp_Generic(op); break; } @@ -355,7 +360,13 @@ namespace MIPSComp { CONDITIONAL_DISABLE; int rs = _RS; + int rd = _RD; int fd = _FD; + + // noop, won't write to ZERO. + if (rd == 0) + return; + // WARNING : ROTR switch (op & 0x3f) { @@ -402,7 +413,7 @@ namespace MIPSComp return; } - gpr.MapDirtyIn(rt, rs, false); + gpr.MapDirtyIn(rt, rs); if (useUBFXandBFI) { UBFX(gpr.R(rt), gpr.R(rs), pos, size); } else { diff --git a/Core/MIPS/ARM/ArmCompBranch.cpp b/Core/MIPS/ARM/ArmCompBranch.cpp index 75770ed842..e18a8949b6 100644 --- a/Core/MIPS/ARM/ArmCompBranch.cpp +++ b/Core/MIPS/ARM/ArmCompBranch.cpp @@ -220,8 +220,8 @@ void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely) FlushAll(); - LDR(R0, R10, offsetof(MIPSState, fpcond)); - TST(R0, Operand2(1, TYPE_IMM)); + LDR(R0, CTXREG, offsetof(MIPSState, fpcond)); + TST(R0, Operand2(1, TYPE_IMM)); ArmGen::FixupBranch ptr; if (!likely) diff --git a/Core/MIPS/ARM/ArmJit.cpp b/Core/MIPS/ARM/ArmJit.cpp index b2d763ae6c..6cd8220ddb 100644 --- a/Core/MIPS/ARM/ArmJit.cpp +++ b/Core/MIPS/ARM/ArmJit.cpp @@ -290,28 +290,28 @@ void Jit::Comp_Generic(u32 op) } void Jit::MovFromPC(ARMReg r) { - LDR(r, R10, offsetof(MIPSState, pc)); + LDR(r, CTXREG, offsetof(MIPSState, pc)); } void Jit::MovToPC(ARMReg r) { - STR(r, R10, offsetof(MIPSState, pc)); + STR(r, CTXREG, offsetof(MIPSState, pc)); } void Jit::WriteDownCount(int offset) { int theDowncount = js.downcountAmount + offset; - LDR(R1, R10, offsetof(MIPSState, downcount)); + LDR(R1, CTXREG, offsetof(MIPSState, downcount)); Operand2 op2; if (TryMakeOperand2(theDowncount, op2)) // We can enlarge this if we used rotations { SUBS(R1, R1, op2); - STR(R1, R10, offsetof(MIPSState, downcount)); + STR(R1, CTXREG, offsetof(MIPSState, downcount)); } else { // Should be fine to use R2 here, flushed the regcache anyway. // If js.downcountAmount can be expressed as an Imm8, we don't need this anyway. MOVI2R(R2, theDowncount); SUBS(R1, R1, R2); - STR(R1, R10, offsetof(MIPSState, downcount)); + STR(R1, CTXREG, offsetof(MIPSState, downcount)); } } diff --git a/Core/MIPS/x86/CompALU.cpp b/Core/MIPS/x86/CompALU.cpp index 7b447674f2..f14343240f 100644 --- a/Core/MIPS/x86/CompALU.cpp +++ b/Core/MIPS/x86/CompALU.cpp @@ -55,8 +55,9 @@ namespace MIPSComp void Jit::Comp_IType(u32 op) { CONDITIONAL_DISABLE; - s32 simm = (s16)(op & 0xFFFF); - u32 uimm = (u16)(op & 0xFFFF); + s32 simm = (s32)(s16)(op & 0xFFFF); // sign extension + u32 uimm = op & 0xFFFF; + u32 suimm = (u32)(s32)simm; int rt = _RT; int rs = _RS; @@ -68,7 +69,7 @@ namespace MIPSComp switch (op >> 26) { case 8: // same as addiu? - case 9: //R(rt) = R(rs) + simm; break; //addiu + case 9: // R(rt) = R(rs) + simm; break; //addiu { if (gpr.IsImmediate(rs)) { @@ -508,8 +509,14 @@ namespace MIPSComp { CONDITIONAL_DISABLE; int rs = _RS; + int rd = _RD; int fd = _FD; - // WARNIGN : ROTR + + // noop, won't write to ZERO. + if (rd == 0) + return; + + // WARNING : ROTR switch (op & 0x3f) { case 0: CompShiftImm(op, &XEmitter::SHL, &ShiftType_ImmLogicalLeft); break; @@ -522,7 +529,6 @@ namespace MIPSComp default: Comp_Generic(op); - //_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted"); break; } } @@ -532,8 +538,8 @@ namespace MIPSComp CONDITIONAL_DISABLE; int rs = _RS; int rt = _RT; - int pos = _POS; + int pos = _POS; int size = _SIZE + 1; u32 mask = 0xFFFFFFFFUL >> (32 - size); @@ -600,6 +606,10 @@ namespace MIPSComp CONDITIONAL_DISABLE int rt = _RT; int rd = _RD; + // Don't change $zr. + if (rd == 0) + return; + switch ((op >> 6) & 31) { case 16: // seb // R(rd) = (u32)(s32)(s8)(u8)R(rt);