From bec587164b3b13e65c07bfe01541b9a8d8d6d199 Mon Sep 17 00:00:00 2001 From: refractionpcsx2 Date: Mon, 5 Oct 2020 21:49:15 +0100 Subject: [PATCH] microVU: Make sure flags are exact on M-bit (#3797) * microVU: Don't break on M-Bit if previous instruction was M-Bit Fixes Gungrave --- pcsx2/x86/microVU_Compile.inl | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/pcsx2/x86/microVU_Compile.inl b/pcsx2/x86/microVU_Compile.inl index 9d21cbe8f9..62c07eadcc 100644 --- a/pcsx2/x86/microVU_Compile.inl +++ b/pcsx2/x86/microVU_Compile.inl @@ -564,7 +564,13 @@ void* mVUcompile(microVU& mVU, u32 startPC, uptr pState) } if ((curI & _Mbit_) && isVU0) { - mVUup.mBit = true; + incPC(-2); + if (!(curI & _Mbit_)) { //If the last instruction was also M-Bit we don't need to sync again + incPC(2); + mVUup.mBit = true; + } + else + incPC(2); } if (curI & _Ibit_) { @@ -611,7 +617,10 @@ void* mVUcompile(microVU& mVU, u32 startPC, uptr pState) } if (mVUup.mBit && !branch && !mVUup.eBit) + { + mVUregs.needExactMatch |= 7; break; + } if (mVUinfo.isEOB) break; @@ -652,6 +661,10 @@ void* mVUcompile(microVU& mVU, u32 startPC, uptr pState) mVUDoDBit(mVU, &mFC); } else if (mVUup.mBit && !mVUup.eBit && !mVUinfo.isEOB) { + // Need to make sure the flags are exact, Gungrave does FCAND with Mbit, then directly after FMAND with M-bit + // Also call setupBranch to sort flag instances + + mVUsetupBranch(mVU, mFC); // Make sure we save the current state so it can come back to it u32* cpS = (u32*)&mVUregs; u32* lpS = (u32*)&mVU.prog.lpState;