From ae3934cffbd2c0d8af65acf200cf6048b5e8cff9 Mon Sep 17 00:00:00 2001
From: gigaherz <gigaherz@96395faa-99c1-11dd-bbfe-3dabce05a288>
Date: Wed, 10 Feb 2010 14:29:22 +0000
Subject: [PATCH] Forgot some people might want to run pcsx2 WITHOUT my new
 dmac enabled.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2580 96395faa-99c1-11dd-bbfe-3dabce05a288
---
 pcsx2/IopDma.cpp | 59 +++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 53 insertions(+), 6 deletions(-)

diff --git a/pcsx2/IopDma.cpp b/pcsx2/IopDma.cpp
index 69e5e9a9e1..bac550bf64 100644
--- a/pcsx2/IopDma.cpp
+++ b/pcsx2/IopDma.cpp
@@ -277,12 +277,59 @@ struct DmaHandlerInfo
 //////////////////////////////////////////////////////////////////////////////////////////////
 // Plugin interface accessors
 
-s32  CALLBACK spu2DmaRead  (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return SPU2dmaRead(channel,data,bytesLeft,bytesProcessed); }
-s32  CALLBACK spu2DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return SPU2dmaWrite(channel,data,bytesLeft,bytesProcessed); }
-void CALLBACK spu2DmaInterrupt (s32 channel) { SPU2dmaInterrupt(channel); }
-s32  CALLBACK dev9DmaRead  (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return DEV9dmaRead(channel,data,bytesLeft,bytesProcessed); }
-s32  CALLBACK dev9DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return DEV9dmaWrite(channel,data,bytesLeft,bytesProcessed); }
-void CALLBACK dev9DmaInterrupt (s32 channel) { DEV9dmaInterrupt(channel); }
+s32  CALLBACK spu2DmaRead  (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) 
+{
+#ifdef ENABLE_NEW_IOPDMA_SPU2
+	return SPU2dmaRead(channel,data,bytesLeft,bytesProcessed); 
+#else
+	*bytesProcessed = bytesLeft;
+	return 0;
+#endif
+}
+
+s32  CALLBACK spu2DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) 
+{
+#ifdef ENABLE_NEW_IOPDMA_SPU2
+	return SPU2dmaWrite(channel,data,bytesLeft,bytesProcessed); 
+#else
+	*bytesProcessed = bytesLeft;
+	return 0;
+#endif
+}
+
+void CALLBACK spu2DmaInterrupt (s32 channel) 
+{
+#ifdef ENABLE_NEW_IOPDMA_SPU2
+	SPU2dmaInterrupt(channel); 
+#endif
+}
+
+s32  CALLBACK dev9DmaRead  (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) 
+{
+#ifdef ENABLE_NEW_IOPDMA_DEV9
+	return DEV9dmaRead(channel,data,bytesLeft,bytesProcessed); 
+#else
+	*bytesProcessed = bytesLeft;
+	return 0;
+#endif
+}
+
+s32  CALLBACK dev9DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) 
+{
+#ifdef ENABLE_NEW_IOPDMA_DEV9
+	return DEV9dmaWrite(channel,data,bytesLeft,bytesProcessed); 
+#else
+	*bytesProcessed = bytesLeft;
+	return 0;
+#endif
+}
+
+void CALLBACK dev9DmaInterrupt (s32 channel) 
+{
+#ifdef ENABLE_NEW_IOPDMA_DEV9
+	DEV9dmaInterrupt(channel); 
+#endif
+}
 
 //////////////////////////////////////////////////////////////////////////////////////////////
 // Dma channel definitions