diff --git a/3rdparty/bzip2/bzip2.cbp b/3rdparty/bzip2/bzip2.cbp
index df2541ac01..b7a49c1245 100644
--- a/3rdparty/bzip2/bzip2.cbp
+++ b/3rdparty/bzip2/bzip2.cbp
@@ -7,7 +7,7 @@
-
+
@@ -19,7 +19,7 @@
-
+
@@ -35,7 +35,7 @@
-
+
diff --git a/3rdparty/zlib/zlib.cbp b/3rdparty/zlib/zlib.cbp
index 8d34e52645..06ec1b6cf1 100644
--- a/3rdparty/zlib/zlib.cbp
+++ b/3rdparty/zlib/zlib.cbp
@@ -7,7 +7,7 @@
-
+
@@ -20,7 +20,7 @@
-
+
@@ -33,7 +33,7 @@
-
+
diff --git a/common/build/Utilities/Utilities.cbp b/common/build/Utilities/Utilities.cbp
new file mode 100644
index 0000000000..55793bc2b9
--- /dev/null
+++ b/common/build/Utilities/Utilities.cbp
@@ -0,0 +1,84 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/common/build/x86emitter/x86emitter.cbp b/common/build/x86emitter/x86emitter.cbp
new file mode 100644
index 0000000000..55b08c98e6
--- /dev/null
+++ b/common/build/x86emitter/x86emitter.cbp
@@ -0,0 +1,102 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
diff --git a/common/include/Pcsx2Defs.h b/common/include/Pcsx2Defs.h
index 11e87f5d0d..1d0f5b4610 100644
--- a/common/include/Pcsx2Defs.h
+++ b/common/include/Pcsx2Defs.h
@@ -5,17 +5,17 @@
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
- *
+ *
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
+ *
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
-
+
#ifndef __PCSX2DEFS_H__
#define __PCSX2DEFS_H__
@@ -199,9 +199,9 @@
# define __naked __declspec(naked)
# define __unused /*unused*/
-# define __noinline __declspec(noinline)
+# define __noinline __declspec(noinline)
-// Don't know if there are Visual C++ equivalents of these.
+// Don't know if there are Visual C++ equivalents of these.
# define __hot
# define __cold
# define likely(x) x
@@ -215,7 +215,7 @@
# define GCC_VERSION (__GNUC__ * 10000 \
+ __GNUC_MINOR__ * 100 \
+ __GNUC_PATCHLEVEL__)
-
+
/* Test for GCC > 4.4.0; Should be adjusted when new versions come out */
# if GCC_VERSION >= 40400
# define THE_UNBEARABLE_LIGHTNESS_OF_BEING_GCC_4_4_0
diff --git a/common/include/Utilities/Dependencies.h b/common/include/Utilities/Dependencies.h
index 466e72996b..5f8fd92d62 100644
--- a/common/include/Utilities/Dependencies.h
+++ b/common/include/Utilities/Dependencies.h
@@ -18,6 +18,9 @@
#pragma once
+// must include wx/setup.h first, otherwise we get warnings/errors regarding __LINUX__
+#include
+
#include "Pcsx2Defs.h"
#include
diff --git a/common/src/Utilities/Console.cpp b/common/src/Utilities/Console.cpp
index cb128ca4bb..88b4043d47 100644
--- a/common/src/Utilities/Console.cpp
+++ b/common/src/Utilities/Console.cpp
@@ -89,9 +89,7 @@ namespace Console
{
ScopedLock locker( m_writelock );
vssprintf( m_format_buffer, fmt, args );
- const char* cstr = m_format_buffer.c_str();
-
- Write( fmt );
+ Write( m_format_buffer.c_str() );
}
__forceinline void __fastcall _WriteLn( const char* fmt, va_list args )
@@ -106,7 +104,7 @@ namespace Console
_WriteLn( fmt, args );
ClearColor();
}
-
+
// ------------------------------------------------------------------------
bool Write( const char* fmt, VARG_PARAM dummy, ... )
{
diff --git a/common/src/Utilities/Linux/LnxHostSys.cpp b/common/src/Utilities/Linux/LnxHostSys.cpp
index 4a6aa81f4b..1ee6af8e23 100644
--- a/common/src/Utilities/Linux/LnxHostSys.cpp
+++ b/common/src/Utilities/Linux/LnxHostSys.cpp
@@ -16,13 +16,15 @@
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
-#include "PrecompiledHeader.h"
+#include "../PrecompiledHeader.h"
#include
#include
namespace HostSys
{
+ static const uptr m_pagemask = getpagesize()-1;
+
void *Mmap(uptr base, u32 size)
{
u8 *Mem;
diff --git a/common/src/Utilities/LnxThreads.cpp b/common/src/Utilities/LnxThreads.cpp
index fe985ebcf1..09f8a6f816 100644
--- a/common/src/Utilities/LnxThreads.cpp
+++ b/common/src/Utilities/LnxThreads.cpp
@@ -18,6 +18,7 @@
#include "PrecompiledHeader.h"
#include "Threading.h"
+#include "x86emitter/tools.h"
// Note: assuming multicore is safer because it forces the interlocked routines to use
// the LOCK prefix. The prefix works on single core CPUs fine (but is slow), but not
@@ -75,98 +76,4 @@ namespace Threading
return NULL;
}
-
- /////////////////////////////////////////////////////////////////////////
- // Cross-platform atomic operations for GCC.
- // These are much faster than the old versions for single core CPUs.
- // Note, I've disabled the single core optimization, because pcsx2 shouldn't
- // ever create threads on single core CPUs anyway.
-
- __forceinline long pcsx2_InterlockedExchange(volatile long* Target, long Value)
- {
- long result;
- /*
- * The XCHG instruction always locks the bus with or without the
- * LOCKED prefix. This makes it significantly slower than CMPXCHG on
- * uni-processor machines. The Windows InterlockedExchange function
- * is nearly 3 times faster than the XCHG instruction, so this routine
- * is not yet very useful for speeding up pthreads.
- */
-
-
- if( true ) //isMultiCore )
- {
- __asm__ __volatile__ (
- "xchgl %2,%1"
- :"=r" (result)
- :"m" (*Target), "0" (Value));
- }
- else
- {
- /*
- * Faster version of XCHG for uni-processor systems because
- * it doesn't lock the bus. If an interrupt or context switch
- * occurs between the movl and the cmpxchgl then the value in
- * 'location' may have changed, in which case we will loop
- * back to do the movl again.
- */
-
- __asm__ __volatile__ (
- "0:\n\t"
- "movl %1,%%eax\n\t"
- "cmpxchgl %2,%1\n\t"
- "jnz 0b"
- :"=&a" (result)
- :"m" (*Target), "r" (Value));
- }
-
- return result;
- }
-
- __forceinline long pcsx2_InterlockedExchangeAdd(volatile long* Addend, long Value)
- {
- if( true ) //isMultiCore )
- {
- __asm__ __volatile__(
- ".intel_syntax noprefix\n"
- "lock xadd [%0], eax\n"
- ".att_syntax\n" : : "r"(Addend), "a"(Value) : "memory");
- }
- else
- {
- __asm__ __volatile__(
- ".intel_syntax noprefix\n"
- "xadd [%0], eax\n"
- ".att_syntax\n" : : "r"(Addend), "a"(Value) : "memory");
- }
- }
-
- __forceinline long pcsx2_InterlockedCompareExchange(volatile long *dest, long value, long comp)
- {
- long result;
-
- if( true ) //isMultiCore )
- {
- __asm__ __volatile__ (
- "lock\n\t"
- "cmpxchgl %2,%1" /* if (EAX == [location]) */
- /* [location] = value */
- /* else */
- /* EAX = [location] */
- :"=a" (result)
- :"m" (*dest), "r" (value), "a" (comp));
- }
- else
- {
- __asm__ __volatile__ (
- "cmpxchgl %2,%1" /* if (EAX == [location]) */
- /* [location] = value */
- /* else */
- /* EAX = [location] */
- :"=a" (result)
- :"m" (*dest), "r" (value), "a" (comp));
- }
-
- return result;
- }
}
diff --git a/common/src/Utilities/ThreadTools.cpp b/common/src/Utilities/ThreadTools.cpp
index 665ad569bc..bfc76225bf 100644
--- a/common/src/Utilities/ThreadTools.cpp
+++ b/common/src/Utilities/ThreadTools.cpp
@@ -51,7 +51,7 @@ namespace Threading
int Thread::GetReturnCode() const
{
- if( !m_terminated )
+ if( !m_terminated )
throw std::logic_error( "Thread is still running. No return code is available." );
return m_returncode;
@@ -60,10 +60,10 @@ namespace Threading
// pthread Cond is an evil api that is not suited for Pcsx2 needs.
// Let's not use it. (Air)
#if 0
- WaitEvent::WaitEvent()
+ WaitEvent::WaitEvent()
{
int err = 0;
-
+
err = pthread_cond_init(&cond, NULL);
err = pthread_mutex_init(&mutex, NULL);
}
@@ -93,7 +93,7 @@ namespace Threading
{
sem_init( &sema, false, 0 );
}
-
+
Semaphore::~Semaphore()
{
sem_destroy( &sema );
@@ -153,7 +153,23 @@ namespace Threading
//////////////////////////////////////////////////////////////////////
// define some overloads for InterlockedExchanges
// for commonly used types, like u32 and s32.
-
+
+ __forceinline long pcsx2_InterlockedExchange( volatile long* target, long srcval )
+ {
+ return _InterlockedExchange( target, srcval );
+ }
+
+ __forceinline long pcsx2_InterlockedCompareExchange( volatile long* target, long srcval, long comp )
+ {
+ // Use the pthreads-win32 implementation...
+ return _InterlockedCompareExchange( target, srcval, comp );
+ }
+
+ __forceinline long pcsx2_InterlockedExchangeAdd( volatile long* target, long srcval )
+ {
+ return _InterlockedExchangeAdd( target, srcval );
+ }
+
__forceinline void AtomicExchange( volatile u32& Target, u32 value )
{
pcsx2_InterlockedExchange( (volatile long*)&Target, value );
@@ -204,4 +220,4 @@ namespace Threading
pcsx2_InterlockedCompareExchange( (volatile long*)target, (long)value, (long)comparand );
}
-}
\ No newline at end of file
+}
diff --git a/common/src/Utilities/WinThreads.cpp b/common/src/Utilities/WinThreads.cpp
index 0c1728b1d7..dbadceaa98 100644
--- a/common/src/Utilities/WinThreads.cpp
+++ b/common/src/Utilities/WinThreads.cpp
@@ -87,58 +87,5 @@ namespace Threading
return NULL;
}
-
- // Note: assuming multicore is safer because it forces the interlocked routines to use
- // the LOCK prefix. The prefix works on single core CPUs fine (but is slow), but not
- // having the LOCK prefix is very bad indeed.
-
- //////////////////////////////////////////////////////////////////////
- // Win32 versions of InterlockedExchange.
- // These are much faster than the Win32 Kernel versions thanks to inlining.
-
- __forceinline long pcsx2_InterlockedExchange( volatile long* target, long srcval )
- {
- return _InterlockedExchange( target, srcval );
- }
-
- __forceinline long pcsx2_InterlockedCompareExchange( volatile long* target, long srcval, long comp )
- {
- // Use the pthreads-win32 implementation...
- return _InterlockedCompareExchange( target, srcval, comp );
- }
-
- __forceinline long pcsx2_InterlockedExchangeAdd( volatile long* target, long srcval )
- {
- //long result;
-
- // Use our own implementation...
- // Pcsx2 won't use threads unless it's a multicore cpu, so no need to use
- // the optimized single-core method.
-
- if( true ) //ptw32_smp_system )
- {
- __asm
- {
- mov ecx,dword ptr [target]
- mov eax,dword ptr [srcval]
- lock xadd dword ptr [ecx],eax
-
- // msvc smartly returns eax for us without so much as a compiler warning even...
- //mov dword ptr [result], eax
- }
- }
- else
- {
- __asm
- {
- mov ecx,dword ptr [target]
- mov eax,dword ptr [srcval]
- xadd dword ptr [ecx],eax
-
- // msvc smartly returns eax for us without so much as a compiler warning even...
- //mov dword ptr [result], eax
- }
- }
-// return result;
- }
}
+
diff --git a/common/src/Utilities/vssprintf.cpp b/common/src/Utilities/vssprintf.cpp
index 64a5556389..b3bf380277 100644
--- a/common/src/Utilities/vssprintf.cpp
+++ b/common/src/Utilities/vssprintf.cpp
@@ -460,7 +460,7 @@ static void cropzeros(char *buffer)
stop = buffer--;
while (*buffer == '0') buffer--;
if (*buffer == '.') buffer--;
- while (*++buffer = *stop++);
+ while ( (*++buffer = *stop++) != 0 );
}
}
diff --git a/common/src/x86emitter/PrecompiledHeader.h b/common/src/x86emitter/PrecompiledHeader.h
index 6a2d726aa1..8495f7e0d3 100644
--- a/common/src/x86emitter/PrecompiledHeader.h
+++ b/common/src/x86emitter/PrecompiledHeader.h
@@ -1,6 +1,9 @@
#ifndef EMITTER_PRECOMPILED_HEADER
#define EMITTER_PRECOMPILED_HEADER
+// must include wx/setup.h first, otherwise we get warnings/errors regarding __LINUX__
+#include
+
#include "Pcsx2Defs.h"
#include
diff --git a/common/src/x86emitter/cpudetect.cpp b/common/src/x86emitter/cpudetect.cpp
index 2d210ffc52..e3ef3f2b7d 100644
--- a/common/src/x86emitter/cpudetect.cpp
+++ b/common/src/x86emitter/cpudetect.cpp
@@ -5,12 +5,12 @@
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
- *
+ *
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
+ *
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
@@ -35,7 +35,7 @@ static s32 iCpuId( u32 cmd, u32 *regs )
xor ecx, ecx; // ecx should be zero for CPUID(4)
}
#else
- __asm__ ( "xor ecx, ecx" );
+ __asm__ ( "xor %ecx, %ecx" );
#endif
__cpuid( (int*)regs, cmd );
@@ -48,7 +48,7 @@ static u64 GetRdtsc( void )
}
//////////////////////////////////////////////////////////////////////////////////////////
-// Note: This function doesn't support GCC/Linux. Looking online it seems the only
+// Note: This function doesn't support GCC/Linux. Looking online it seems the only
// way to simulate the Microsoft SEH model is to use unix signals, and the 'sigaction'
// function specifically. Maybe a project for a linux developer at a later date. :)
//
@@ -89,7 +89,7 @@ static void SetSingleAffinity()
DWORD_PTR availProcCpus, availSysCpus;
if( !GetProcessAffinityMask( GetCurrentProcess(), &availProcCpus, &availSysCpus ) ) return;
-
+
int i;
for( i=0; i<32; ++i )
{
@@ -158,17 +158,17 @@ int arr[] = {
0x20202020,0x20402020,0x36362e32,0x7a4847
};
-void cpudetectInit()
+void cpudetectInit()
{
u32 regs[ 4 ];
u32 cmds;
int cputype=0; // Cpu type
//AMD 64 STUFF
u32 x86_64_8BITBRANDID;
- u32 x86_64_12BITBRANDID;
+ u32 x86_64_12BITBRANDID;
int num;
char str[50];
-
+
memzero_obj( cpuinfo.x86ID );
cpuinfo.x86Family = 0;
cpuinfo.x86Model = 0;
@@ -176,21 +176,21 @@ void cpudetectInit()
cpuinfo.x86StepID = 0;
cpuinfo.x86Flags = 0;
cpuinfo.x86EFlags = 0;
-
+
if ( iCpuId( 0, regs ) == -1 ) return;
cmds = regs[ 0 ];
((u32*)cpuinfo.x86ID)[ 0 ] = regs[ 1 ];
((u32*)cpuinfo.x86ID)[ 1 ] = regs[ 3 ];
((u32*)cpuinfo.x86ID)[ 2 ] = regs[ 2 ];
-
+
// Hack - prevents reg[2] & reg[3] from being optimized out of existance!
num = sprintf(str, "\tx86Flags = %8.8x %8.8x\n", regs[3], regs[2]);
-
+
u32 LogicalCoresPerPhysicalCPU = 0;
u32 PhysicalCoresPerPhysicalCPU = 1;
- if ( cmds >= 0x00000001 )
+ if ( cmds >= 0x00000001 )
{
if ( iCpuId( 0x00000001, regs ) != -1 )
{
@@ -216,14 +216,14 @@ void cpudetectInit()
if ( iCpuId( 0x80000000, regs ) != -1 )
{
cmds = regs[ 0 ];
- if ( cmds >= 0x80000001 )
+ if ( cmds >= 0x80000001 )
{
if ( iCpuId( 0x80000001, regs ) != -1 )
{
x86_64_12BITBRANDID = regs[1] & 0xfff;
cpuinfo.x86EFlags2 = regs[ 2 ];
cpuinfo.x86EFlags = regs[ 3 ];
-
+
}
}
/* detect multicore for amd cpu */
@@ -235,7 +235,7 @@ void cpudetectInit()
}
}
}
-
+
switch(cpuinfo.x86PType)
{
case 0:
@@ -256,7 +256,7 @@ void cpudetectInit()
}
if ( cpuinfo.x86ID[ 0 ] == 'G' ){ cputype=0;}//trick lines but if you know a way better ;p
if ( cpuinfo.x86ID[ 0 ] == 'A' ){ cputype=1;}
-
+
memzero_obj( cpuinfo.x86Fam );
iCpuId( 0x80000002, (u32*)cpuinfo.x86Fam);
iCpuId( 0x80000003, (u32*)(cpuinfo.x86Fam+16));
@@ -292,12 +292,12 @@ void cpudetectInit()
cpucaps.hasMultiThreading = ( cpuinfo.x86Flags >> 28 ) & 1;
cpucaps.hasThermalMonitor = ( cpuinfo.x86Flags >> 29 ) & 1;
cpucaps.hasIntel64BitArchitecture = ( cpuinfo.x86Flags >> 30 ) & 1;
-
+
//that is only for AMDs
cpucaps.hasMultimediaExtensionsExt = ( cpuinfo.x86EFlags >> 22 ) & 1; //mmx2
cpucaps.hasAMD64BitArchitecture = ( cpuinfo.x86EFlags >> 29 ) & 1; //64bit cpu
cpucaps.has3DNOWInstructionExtensionsExt = ( cpuinfo.x86EFlags >> 30 ) & 1; //3dnow+
- cpucaps.has3DNOWInstructionExtensions = ( cpuinfo.x86EFlags >> 31 ) & 1; //3dnow
+ cpucaps.has3DNOWInstructionExtensions = ( cpuinfo.x86EFlags >> 31 ) & 1; //3dnow
cpucaps.hasStreamingSIMD4ExtensionsA = ( cpuinfo.x86EFlags2 >> 6 ) & 1; //INSERTQ / EXTRQ / MOVNT
InitCPUTicks();
@@ -311,8 +311,8 @@ void cpudetectInit()
// --> SSE3 / SSSE3 / SSE4.1 / SSE 4.2 detection <--
cpucaps.hasStreamingSIMD3Extensions = ( cpuinfo.x86Flags2 >> 0 ) & 1; //sse3
- cpucaps.hasSupplementalStreamingSIMD3Extensions = ( cpuinfo.x86Flags2 >> 9 ) & 1; //ssse3
- cpucaps.hasStreamingSIMD4Extensions = ( cpuinfo.x86Flags2 >> 19 ) & 1; //sse4.1
+ cpucaps.hasSupplementalStreamingSIMD3Extensions = ( cpuinfo.x86Flags2 >> 9 ) & 1; //ssse3
+ cpucaps.hasStreamingSIMD4Extensions = ( cpuinfo.x86Flags2 >> 19 ) & 1; //sse4.1
cpucaps.hasStreamingSIMD4Extensions2 = ( cpuinfo.x86Flags2 >> 20 ) & 1; //sse4.2
//////////////////////////////////////////////////////////////////////////////////////////
@@ -343,7 +343,7 @@ void cpudetectInit()
u8* funcSSE41 = xGetPtr();
xBLEND.VPD( xmm1, xmm0 );
xRET();
-
+
bool sse3_result = _test_instruction( recSSE ); // sse3
bool ssse3_result = _test_instruction( funcSSSE3 );
bool sse41_result = _test_instruction( funcSSE41 );
@@ -359,7 +359,7 @@ void cpudetectInit()
{
Console::Notice( "SSE3 Detection Inconsistency: cpuid=%s, test_result=%s",
params bool_to_char( !!cpucaps.hasStreamingSIMD3Extensions ), bool_to_char( sse3_result ) );
-
+
cpucaps.hasStreamingSIMD3Extensions = sse3_result;
}
diff --git a/common/src/x86emitter/legacy.cpp b/common/src/x86emitter/legacy.cpp
index e0a80caaed..8e268930cc 100644
--- a/common/src/x86emitter/legacy.cpp
+++ b/common/src/x86emitter/legacy.cpp
@@ -5,12 +5,12 @@
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
-*
+*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
-*
+*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
@@ -95,7 +95,7 @@ static __forceinline ModSibStrict _mhlp2( x86IntRegType src1, x86IntReg
{ x##cod( _mhlp2(to1,to2) + offset, _reghlp(from) ); } \
emitterT void cod##bits##RmStoR( x86IntRegType to, x86IntRegType from1, x86IntRegType from2, int offset ) \
{ x##cod( _reghlp(to), _mhlp2(from1,from2) + offset ); }
-
+
#define DEFINE_LEGACY_SHIFT_HELPER( cod, bits ) \
emitterT void cod##bits##CLtoR( x86IntRegType to ) { x##cod( _reghlp(to), cl ); } \
emitterT void cod##bits##ItoR( x86IntRegType to, u8 imm ) { x##cod( _reghlp(to), imm ); } \
@@ -108,9 +108,9 @@ static __forceinline ModSibStrict _mhlp2( x86IntRegType src1, x86IntReg
emitterT void cod##bits##R( x86IntRegType to ) { x##cod( _reghlp(to) ); } \
emitterT void cod##bits##M( uptr to ) { x##cod( ptr##bits[to] ); } \
emitterT void cod##bits##Rm( x86IntRegType to, uptr offset ) { x##cod( _mhlp(to) + offset ); }
-
-//emitterT void cod##bits##RtoRmS( x86IntRegType to1, x86IntRegType to2, x86IntRegType from, int offset ) \
-// { cod( _mhlp2(to1,to2) + offset, _reghlp(from) ); } \
+
+//emitterT void cod##bits##RtoRmS( x86IntRegType to1, x86IntRegType to2, x86IntRegType from, int offset )
+// { cod( _mhlp2(to1,to2) + offset, _reghlp(from) ); }
#define DEFINE_OPCODE_LEGACY( cod ) \
DEFINE_LEGACY_HELPER( cod, 32 ) \
@@ -199,18 +199,18 @@ emitterT void MOV8RmSOffsettoR( x86IntRegType to, x86IntRegType from1, s32 from2
xMOV( xRegister8(to), ptr[(xAddressReg(from1)<(to), from );
}
-emitterT void AND32I8toM( uptr to, s8 from )
+emitterT void AND32I8toM( uptr to, s8 from )
{
xAND( ptr8[to], from );
}
/* cmove r32 to r32*/
-emitterT void CMOVE32RtoR( x86IntRegType to, x86IntRegType from )
+emitterT void CMOVE32RtoR( x86IntRegType to, x86IntRegType from )
{
xCMOVE( xRegister32(to), xRegister32(from) );
}
@@ -237,7 +237,7 @@ emitterT void MUL32M( u32 from ) { xUMUL( ptr32[from] ); }
emitterT void IMUL32M( u32 from ) { xMUL( ptr32[from] ); }
/* imul r32 by r32 to r32 */
-emitterT void IMUL32RtoR( x86IntRegType to, x86IntRegType from )
+emitterT void IMUL32RtoR( x86IntRegType to, x86IntRegType from )
{
xMUL( xRegister32(to), xRegister32(from) );
}
@@ -258,7 +258,7 @@ emitterT void LEA32RtoR(x86IntRegType to, x86IntRegType from, s32 offset)
}
emitterT void LEA32RRtoR(x86IntRegType to, x86IntRegType from0, x86IntRegType from1)
-{
+{
xLEA( xRegister32( to ), ptr[xAddressReg(from0)+xAddressReg(from1)] );
}
@@ -357,7 +357,7 @@ emitterT u32* J32Rel( int cc, u32 to )
}
////////////////////////////////////////////////////
-emitterT void x86SetPtr( u8* ptr )
+emitterT void x86SetPtr( u8* ptr )
{
x86Ptr = ptr;
}
@@ -401,7 +401,7 @@ void x86SetJ8A( u8* j8 )
}
////////////////////////////////////////////////////
-emitterT void x86SetJ32( u32* j32 )
+emitterT void x86SetJ32( u32* j32 )
{
*j32 = ( x86Ptr - (u8*)j32 ) - 4;
}
@@ -413,7 +413,7 @@ emitterT void x86SetJ32A( u32* j32 )
}
////////////////////////////////////////////////////
-emitterT void x86Align( int bytes )
+emitterT void x86Align( int bytes )
{
// forward align
x86Ptr = (u8*)( ( (uptr)x86Ptr + bytes - 1) & ~( bytes - 1 ) );
@@ -432,29 +432,29 @@ emitterT void NOP( void ) { xNOP(); }
////////////////////////////////////
/* jmp rel8 */
-emitterT u8* JMP8( u8 to )
+emitterT u8* JMP8( u8 to )
{
- xWrite8( 0xEB );
+ xWrite8( 0xEB );
xWrite8( to );
return x86Ptr - 1;
}
/* jmp rel32 */
-emitterT u32* JMP32( uptr to )
+emitterT u32* JMP32( uptr to )
{
assert( (sptr)to <= 0x7fffffff && (sptr)to >= -0x7fffffff );
- xWrite8( 0xE9 );
- xWrite32( to );
+ xWrite8( 0xE9 );
+ xWrite32( to );
return (u32*)(x86Ptr - 4 );
}
/* jmp r32/r64 */
-emitterT void JMPR( x86IntRegType to )
+emitterT void JMPR( x86IntRegType to )
{
xJMP( xRegister32(to) );
}
-// jmp m32
+// jmp m32
emitterT void JMP32M( uptr to )
{
xJMP( ptr32[to] );
@@ -476,247 +476,247 @@ emitterT u8* JE8( u8 to ) {
}
/* jz rel8 */
-emitterT u8* JZ8( u8 to )
+emitterT u8* JZ8( u8 to )
{
- return J8Rel( 0x74, to );
+ return J8Rel( 0x74, to );
}
/* js rel8 */
-emitterT u8* JS8( u8 to )
-{
+emitterT u8* JS8( u8 to )
+{
return J8Rel( 0x78, to );
}
/* jns rel8 */
-emitterT u8* JNS8( u8 to )
-{
+emitterT u8* JNS8( u8 to )
+{
return J8Rel( 0x79, to );
}
/* jg rel8 */
-emitterT u8* JG8( u8 to )
-{
+emitterT u8* JG8( u8 to )
+{
return J8Rel( 0x7F, to );
}
/* jge rel8 */
-emitterT u8* JGE8( u8 to )
-{
- return J8Rel( 0x7D, to );
+emitterT u8* JGE8( u8 to )
+{
+ return J8Rel( 0x7D, to );
}
/* jl rel8 */
-emitterT u8* JL8( u8 to )
-{
- return J8Rel( 0x7C, to );
+emitterT u8* JL8( u8 to )
+{
+ return J8Rel( 0x7C, to );
}
/* ja rel8 */
-emitterT u8* JA8( u8 to )
-{
- return J8Rel( 0x77, to );
+emitterT u8* JA8( u8 to )
+{
+ return J8Rel( 0x77, to );
}
-emitterT u8* JAE8( u8 to )
-{
- return J8Rel( 0x73, to );
+emitterT u8* JAE8( u8 to )
+{
+ return J8Rel( 0x73, to );
}
/* jb rel8 */
-emitterT u8* JB8( u8 to )
-{
- return J8Rel( 0x72, to );
+emitterT u8* JB8( u8 to )
+{
+ return J8Rel( 0x72, to );
}
/* jbe rel8 */
-emitterT u8* JBE8( u8 to )
-{
- return J8Rel( 0x76, to );
+emitterT u8* JBE8( u8 to )
+{
+ return J8Rel( 0x76, to );
}
/* jle rel8 */
-emitterT u8* JLE8( u8 to )
-{
- return J8Rel( 0x7E, to );
+emitterT u8* JLE8( u8 to )
+{
+ return J8Rel( 0x7E, to );
}
/* jne rel8 */
-emitterT u8* JNE8( u8 to )
-{
- return J8Rel( 0x75, to );
+emitterT u8* JNE8( u8 to )
+{
+ return J8Rel( 0x75, to );
}
/* jnz rel8 */
-emitterT u8* JNZ8( u8 to )
-{
- return J8Rel( 0x75, to );
+emitterT u8* JNZ8( u8 to )
+{
+ return J8Rel( 0x75, to );
}
/* jng rel8 */
-emitterT u8* JNG8( u8 to )
-{
- return J8Rel( 0x7E, to );
+emitterT u8* JNG8( u8 to )
+{
+ return J8Rel( 0x7E, to );
}
/* jnge rel8 */
-emitterT u8* JNGE8( u8 to )
-{
- return J8Rel( 0x7C, to );
+emitterT u8* JNGE8( u8 to )
+{
+ return J8Rel( 0x7C, to );
}
/* jnl rel8 */
-emitterT u8* JNL8( u8 to )
-{
- return J8Rel( 0x7D, to );
+emitterT u8* JNL8( u8 to )
+{
+ return J8Rel( 0x7D, to );
}
/* jnle rel8 */
-emitterT u8* JNLE8( u8 to )
-{
- return J8Rel( 0x7F, to );
+emitterT u8* JNLE8( u8 to )
+{
+ return J8Rel( 0x7F, to );
}
/* jo rel8 */
-emitterT u8* JO8( u8 to )
-{
- return J8Rel( 0x70, to );
+emitterT u8* JO8( u8 to )
+{
+ return J8Rel( 0x70, to );
}
/* jno rel8 */
-emitterT u8* JNO8( u8 to )
-{
- return J8Rel( 0x71, to );
+emitterT u8* JNO8( u8 to )
+{
+ return J8Rel( 0x71, to );
}
-// jb rel32
+// jb rel32
emitterT u32* JB32( u32 to )
{
return J32Rel( 0x82, to );
}
/* je rel32 */
-emitterT u32* JE32( u32 to )
+emitterT u32* JE32( u32 to )
{
return J32Rel( 0x84, to );
}
/* jz rel32 */
-emitterT u32* JZ32( u32 to )
+emitterT u32* JZ32( u32 to )
{
- return J32Rel( 0x84, to );
+ return J32Rel( 0x84, to );
}
/* js rel32 */
-emitterT u32* JS32( u32 to )
-{
+emitterT u32* JS32( u32 to )
+{
return J32Rel( 0x88, to );
}
/* jns rel32 */
-emitterT u32* JNS32( u32 to )
-{
+emitterT u32* JNS32( u32 to )
+{
return J32Rel( 0x89, to );
}
/* jg rel32 */
-emitterT u32* JG32( u32 to )
-{
+emitterT u32* JG32( u32 to )
+{
return J32Rel( 0x8F, to );
}
/* jge rel32 */
-emitterT u32* JGE32( u32 to )
-{
- return J32Rel( 0x8D, to );
+emitterT u32* JGE32( u32 to )
+{
+ return J32Rel( 0x8D, to );
}
/* jl rel32 */
-emitterT u32* JL32( u32 to )
-{
- return J32Rel( 0x8C, to );
+emitterT u32* JL32( u32 to )
+{
+ return J32Rel( 0x8C, to );
}
/* jle rel32 */
-emitterT u32* JLE32( u32 to )
-{
- return J32Rel( 0x8E, to );
+emitterT u32* JLE32( u32 to )
+{
+ return J32Rel( 0x8E, to );
}
/* ja rel32 */
-emitterT u32* JA32( u32 to )
-{
- return J32Rel( 0x87, to );
+emitterT u32* JA32( u32 to )
+{
+ return J32Rel( 0x87, to );
}
/* jae rel32 */
-emitterT u32* JAE32( u32 to )
-{
- return J32Rel( 0x83, to );
+emitterT u32* JAE32( u32 to )
+{
+ return J32Rel( 0x83, to );
}
/* jne rel32 */
-emitterT u32* JNE32( u32 to )
-{
- return J32Rel( 0x85, to );
+emitterT u32* JNE32( u32 to )
+{
+ return J32Rel( 0x85, to );
}
/* jnz rel32 */
-emitterT u32* JNZ32( u32 to )
-{
- return J32Rel( 0x85, to );
+emitterT u32* JNZ32( u32 to )
+{
+ return J32Rel( 0x85, to );
}
/* jng rel32 */
-emitterT u32* JNG32( u32 to )
-{
- return J32Rel( 0x8E, to );
+emitterT u32* JNG32( u32 to )
+{
+ return J32Rel( 0x8E, to );
}
/* jnge rel32 */
-emitterT u32* JNGE32( u32 to )
-{
- return J32Rel( 0x8C, to );
+emitterT u32* JNGE32( u32 to )
+{
+ return J32Rel( 0x8C, to );
}
/* jnl rel32 */
-emitterT u32* JNL32( u32 to )
-{
- return J32Rel( 0x8D, to );
+emitterT u32* JNL32( u32 to )
+{
+ return J32Rel( 0x8D, to );
}
/* jnle rel32 */
-emitterT u32* JNLE32( u32 to )
-{
- return J32Rel( 0x8F, to );
+emitterT u32* JNLE32( u32 to )
+{
+ return J32Rel( 0x8F, to );
}
/* jo rel32 */
-emitterT u32* JO32( u32 to )
-{
- return J32Rel( 0x80, to );
+emitterT u32* JO32( u32 to )
+{
+ return J32Rel( 0x80, to );
}
/* jno rel32 */
-emitterT u32* JNO32( u32 to )
-{
- return J32Rel( 0x81, to );
+emitterT u32* JNO32( u32 to )
+{
+ return J32Rel( 0x81, to );
}
/* call func */
-emitterT void CALLFunc( uptr func )
+emitterT void CALLFunc( uptr func )
{
xCALL( (void*)func );
}
/* call r32 */
-emitterT void CALL32R( x86IntRegType to )
+emitterT void CALL32R( x86IntRegType to )
{
xCALL( xRegister32( to ) );
}
/* call m32 */
-emitterT void CALL32M( u32 to )
+emitterT void CALL32M( u32 to )
{
xCALL( ptr32[to] );
}
@@ -726,7 +726,7 @@ emitterT void BSRRtoR(x86IntRegType to, x86IntRegType from)
xBSR( xRegister32(to), xRegister32(from) );
}
-emitterT void BSWAP32R( x86IntRegType to )
+emitterT void BSWAP32R( x86IntRegType to )
{
xBSWAP( xRegister32(to) );
}
diff --git a/common/src/x86emitter/x86emitter.cpp b/common/src/x86emitter/x86emitter.cpp
index c1b16ab982..299584b3c7 100644
--- a/common/src/x86emitter/x86emitter.cpp
+++ b/common/src/x86emitter/x86emitter.cpp
@@ -5,12 +5,12 @@
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
- *
+ *
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
+ *
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
@@ -74,17 +74,17 @@ __forceinline void xWrite8( u8 val )
}
__forceinline void xWrite16( u16 val )
-{
+{
xWrite( val );
-}
+}
__forceinline void xWrite32( u32 val )
-{
+{
xWrite( val );
-}
+}
__forceinline void xWrite64( u64 val )
-{
+{
xWrite( val );
}
@@ -93,7 +93,7 @@ const xAddressIndexer ptr128;
const xAddressIndexer ptr64;
const xAddressIndexer ptr32;
const xAddressIndexer ptr16;
-const xAddressIndexer ptr8;
+const xAddressIndexer ptr8;
// ------------------------------------------------------------------------
@@ -130,7 +130,7 @@ const xRegister8
dl( 2 ), bl( 3 ),
ah( 4 ), ch( 5 ),
dh( 6 ), bh( 7 );
-
+
const xRegisterCL cl;
const char *const x86_regnames_gpr8[8] =
@@ -174,9 +174,9 @@ namespace Internal
if( src.IsEmpty() ) return "empty";
switch( sizeof(T) )
{
- case 1: return tbl_regnames_gpr8[ src.Id ];
- case 2: return tbl_regnames_gpr16[ src.Id ];
- case 4: return tbl_regnames_gpr32[ src.Id ];
+ case 1: return x86_regnames_gpr8[ src.Id ];
+ case 2: return x86_regnames_gpr16[ src.Id ];
+ case 4: return x86_regnames_gpr32[ src.Id ];
}
}
@@ -196,7 +196,7 @@ namespace Internal
// brand P4s with a broken barrel shifter?). The workaround is to do our own manual
// x86Ptr access and update using a u32 instead of u8. Thanks to little endianness,
// the same end result is achieved and no false dependencies are generated. The draw-
- // back is that it clobbers 3 bytes past the end of the write, which could cause a
+ // back is that it clobbers 3 bytes past the end of the write, which could cause a
// headache for someone who himself is doing some kind of headache-inducing amount of
// recompiler SMC. So we don't do a work-around, and just hope for the compiler to
// stop sucking someday instead. :)
@@ -277,7 +277,7 @@ namespace Internal
{
jASSUME( regfield < 8 );
- int displacement_size = (info.Displacement == 0) ? 0 :
+ int displacement_size = (info.Displacement == 0) ? 0 :
( ( info.IsByteSizeDisp() ) ? 1 : 2 );
if( !NeedsSibMagic( info ) )
@@ -444,7 +444,7 @@ const SetImplAll xSETPO;
// Assigns the current emitter buffer target address.
// This is provided instead of using x86Ptr directly, since we may in the future find
// a need to change the storage class system for the x86Ptr 'under the hood.'
-__emitinline void xSetPtr( void* ptr )
+__emitinline void xSetPtr( void* ptr )
{
x86Ptr = (u8*)ptr;
}
@@ -459,7 +459,7 @@ __emitinline u8* xGetPtr()
}
// ------------------------------------------------------------------------
-__emitinline void xAlignPtr( uint bytes )
+__emitinline void xAlignPtr( uint bytes )
{
// forward align
x86Ptr = (u8*)( ( (uptr)x86Ptr + bytes - 1) & ~(bytes - 1) );
@@ -483,13 +483,13 @@ __emitinline void xAdvancePtr( uint bytes )
// Necessary because by default ModSib compounds registers into Index when possible.
//
// If the ModSib is in illegal form ([Base + Index*5] for example) then an assertion
-// followed by an InvalidParameter Exception will be tossed around in haphazard
+// followed by an InvalidParameter Exception will be tossed around in haphazard
// fashion.
//
// Optimization Note: Currently VC does a piss poor job of inlining this, even though
// constant propagation *should* resove it to little or no code (VC's constprop fails
// on C++ class initializers). There is a work around [using array initializers instead]
-// but it's too much trouble for code that isn't performance critical anyway.
+// but it's too much trouble for code that isn't performance critical anyway.
// And, with luck, maybe VC10 will optimize it better and make it a non-issue. :D
//
void ModSibBase::Reduce()
@@ -518,7 +518,7 @@ void ModSibBase::Reduce()
}
// The Scale has a series of valid forms, all shown here:
-
+
switch( Scale )
{
case 0: break;
@@ -530,7 +530,7 @@ void ModSibBase::Reduce()
Base = Index;
Scale = 1;
break;
-
+
case 4: Scale = 2; break;
case 5: // becomes [reg*4+reg]
@@ -538,15 +538,15 @@ void ModSibBase::Reduce()
Base = Index;
Scale = 2;
break;
-
+
case 6: // invalid!
assert( false );
break;
-
+
case 7: // so invalid!
assert( false );
break;
-
+
case 8: Scale = 3; break;
case 9: // becomes [reg*8+reg]
jASSUME( Base.IsEmpty() );
@@ -569,8 +569,8 @@ template< typename OperandType >
static void EmitLeaMagic( xRegister to, const ModSibBase& src, bool preserve_flags )
{
typedef xRegister ToReg;
-
- int displacement_size = (src.Displacement == 0) ? 0 :
+
+ int displacement_size = (src.Displacement == 0) ? 0 :
( ( src.IsByteSizeDisp() ) ? 1 : 2 );
// See EmitSibMagic for commenting on SIB encoding.
@@ -597,7 +597,7 @@ static void EmitLeaMagic( xRegister to, const ModSibBase& src, bool
{
// encode as MOV and ADD combo. Make sure to use the immediate on the
// ADD since it can encode as an 8-bit sign-extended value.
-
+
xMOV( to, ToReg( src.Index.Id ) );
xADD( to, src.Displacement );
return;
@@ -659,7 +659,7 @@ static void EmitLeaMagic( xRegister to, const ModSibBase& src, bool
{
// special case handling of ESP as Index, which is replaceable with
// a single MOV even when preserve_flags is set! :D
-
+
xMOV( to, ToReg( src.Base.Id ) );
return;
}
diff --git a/pcsx2/Linux/pcsx2-codeblocks.workspace b/pcsx2/Linux/pcsx2-codeblocks.workspace
index 5b2eaeb9bf..e5e019d349 100644
--- a/pcsx2/Linux/pcsx2-codeblocks.workspace
+++ b/pcsx2/Linux/pcsx2-codeblocks.workspace
@@ -1,22 +1,13 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
diff --git a/pcsx2/Linux/pcsx2.cbp b/pcsx2/Linux/pcsx2.cbp
index 068d348803..6769746c73 100644
--- a/pcsx2/Linux/pcsx2.cbp
+++ b/pcsx2/Linux/pcsx2.cbp
@@ -28,7 +28,9 @@
-
+
+
+
@@ -53,7 +55,9 @@
-
+
+
+
@@ -77,7 +81,9 @@
-
+
+
+
@@ -102,22 +108,16 @@
-
-
-
-
-
-
@@ -182,8 +182,6 @@
-
-
@@ -257,11 +255,9 @@
-
-
@@ -283,42 +279,24 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
@@ -328,18 +306,13 @@
-
-
-
-
-
@@ -401,23 +374,14 @@
-
-
-
-
-
-
-
-
-
diff --git a/pcsx2/ps2/Iop/IopHwWrite.cpp b/pcsx2/ps2/Iop/IopHwWrite.cpp
index 0a05edf598..4052523afb 100644
--- a/pcsx2/ps2/Iop/IopHwWrite.cpp
+++ b/pcsx2/ps2/Iop/IopHwWrite.cpp
@@ -5,12 +5,12 @@
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
- *
+ *
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
+ *
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
@@ -68,7 +68,7 @@ void __fastcall iopHwWrite8_Page1( u32 addr, mem8_t val )
u32 masked_addr = pgmsk( addr );
switch( masked_addr )
- {
+ {
mcase(HW_SIO_DATA): sioWrite8( val ); break;
// for use of serial port ignore for now
@@ -116,8 +116,6 @@ void __fastcall iopHwWrite8_Page3( u32 addr, mem8_t val )
if( addr == 0x1f80380c ) // STDOUT
{
- bool flush = false;
-
// Terminate lines on CR or full buffers, and ignore \n's if the string contents
// are empty (otherwise terminate on \n too!)
if( ( val == '\r' ) || ( g_pbufi == 1023 ) ||
@@ -148,7 +146,7 @@ void __fastcall iopHwWrite8_Page8( u32 addr, mem8_t val )
psxHu8( addr ) = val;
PSXHW_LOG( "HwWrite8 to %s, addr 0x%08x = 0x%02x", _log_GetIopHwName(addr), addr, psxHu8(addr) );
-
+
}
//////////////////////////////////////////////////////////////////////////////////////////
@@ -187,7 +185,7 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
case 0x8:
psxRcntWtarget16( cntidx, val );
break;
-
+
default:
psxHu(addr) = val;
break;
@@ -332,14 +330,14 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
SPU2WriteMemAddr( 1, val );
HW_DMA7_MADR = val;
break;
-
+
// ------------------------------------------------------------------------
//
/*
mcase(0x1f801088): // DMA0 CHCR -- MDEC IN [ignored]
DmaExec(0);
break;
-
+
mcase(0x1f801098): // DMA1 CHCR -- MDEC OUT [ignored]
DmaExec(1);
break;
@@ -395,7 +393,7 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
// ------------------------------------------------------------------------
// DMA ICR handlers -- General XOR behavior!
-
+
mcase(0x1f8010f4):
{
u32 tmp = (~val) & HW_DMA_ICR;
@@ -417,7 +415,7 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
psxHu(addr) = ((tmp ^ val) & 0xffffff) ^ tmp;
}
break;
-
+
mcase(0x1f801576): // ICR2_hi (16 bit?) [dunno if it ever happens]
{
const u32 val2 = (u32)val << 16;
@@ -454,7 +452,7 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
break;
}
}
-
+
PSXHW_LOG( "HwWrite%s to %s, addr 0x%08x = 0x%04x",
sizeof(T) == 2 ? "16" : "32", _log_GetIopHwName( addr ), addr, val
);
@@ -517,7 +515,7 @@ void __fastcall iopHwWrite32_Page8( u32 addr, mem32_t val )
{
// SIO2 Send commands alternate registers. First reg maps to Send1, second
// to Send2, third to Send1, etc. And the following clever code does this:
-
+
const int parm = (masked_addr-0x240) / 8;
if(masked_addr & 4) sio2_setSend2( parm, val ); else sio2_setSend1( parm, val );
}
@@ -533,7 +531,7 @@ void __fastcall iopHwWrite32_Page8( u32 addr, mem32_t val )
// Other SIO2 registers are read-only, no-ops on write.
default:
psxHu32(addr) = val;
- break;
+ break;
}
}
else if( masked_addr >= pgmsk(HW_FW_START) && masked_addr <= pgmsk(HW_FW_END) )