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https://github.com/PCSX2/pcsx2.git
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Core: Refactor a lot of timer work and fix a couple of bugs
EE/IOP Timers: improve clock sync, disable v/h sync when SINT enabled. Some changes based on tests from PS2 [SAVEVERSION+]
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@@ -31,8 +31,8 @@ Counter counters[4];
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SyncCounter hsyncCounter;
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SyncCounter vsyncCounter;
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u32 nextsCounter; // records the cpuRegs.cycle value of the last call to rcntUpdate()
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s32 nextCounter; // delta from nextsCounter, in cycles, until the next rcntUpdate()
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u32 nextStartCounter; // records the cpuRegs.cycle value of the last call to rcntUpdate()
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s32 nextDeltaCounter; // delta from nextsCounter, in cycles, until the next rcntUpdate()
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// Forward declarations needed because C/C++ both are wimpy single-pass compilers.
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@@ -59,7 +59,7 @@ static bool IsProgressiveVideoMode()
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void rcntReset(int index)
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{
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counters[index].count = 0;
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counters[index].sCycleT = cpuRegs.cycle;
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counters[index].startCycle = cpuRegs.cycle;
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}
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// Updates the state of the nextCounter value (if needed) to serve
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@@ -76,13 +76,13 @@ static __fi void _rcntSet(int cntidx)
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if (!rcntCanCount(cntidx) || (counter.mode.ClockSource == 0x3))
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return;
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if (!counter.mode.TargetInterrupt && !counter.mode.OverflowInterrupt)
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if (!counter.mode.TargetInterrupt && !counter.mode.OverflowInterrupt && !counter.mode.ZeroReturn)
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return;
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// check for special cases where the overflow or target has just passed
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// (we probably missed it because we're doing/checking other things)
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if (counter.count > 0x10000 || counter.count > counter.target)
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{
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nextCounter = 4;
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nextDeltaCounter = 4;
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return;
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}
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@@ -91,13 +91,14 @@ static __fi void _rcntSet(int cntidx)
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// that into account. Adding the difference from that cycle count to the current one
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// will do the trick!
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c = ((0x10000 - counter.count) * counter.rate) - (cpuRegs.cycle - counter.sCycleT);
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c += cpuRegs.cycle - nextsCounter; // adjust for time passed since last rcntUpdate();
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if (c < nextCounter)
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{
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nextCounter = c;
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c = ((0x10000 - counter.count) * counter.rate) - (cpuRegs.cycle - counter.startCycle);
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c += cpuRegs.cycle - nextStartCounter; // adjust for time passed since last rcntUpdate();
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cpuSetNextEvent(nextsCounter, nextCounter); // Need to update on counter resets/target changes
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if (c < nextDeltaCounter)
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{
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nextDeltaCounter = c;
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cpuSetNextEvent(nextStartCounter, nextDeltaCounter); // Need to update on counter resets/target changes
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}
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// Ignore target diff if target is currently disabled.
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@@ -111,12 +112,13 @@ static __fi void _rcntSet(int cntidx)
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else
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{
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c = ((counter.target - counter.count) * counter.rate) - (cpuRegs.cycle - counter.sCycleT);
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c += cpuRegs.cycle - nextsCounter; // adjust for time passed since last rcntUpdate();
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if (c < nextCounter)
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c = ((counter.target - counter.count) * counter.rate) - (cpuRegs.cycle - counter.startCycle);
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c += cpuRegs.cycle - nextStartCounter; // adjust for time passed since last rcntUpdate();
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if (c < nextDeltaCounter)
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{
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nextCounter = c;
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cpuSetNextEvent(nextsCounter, nextCounter); // Need to update on counter resets/target changes
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nextDeltaCounter = c;
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cpuSetNextEvent(nextStartCounter, nextDeltaCounter); // Need to update on counter resets/target changes
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}
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}
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}
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@@ -127,22 +129,22 @@ static __fi void cpuRcntSet()
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int i;
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// Default to next VBlank
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nextsCounter = cpuRegs.cycle;
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nextCounter = vsyncCounter.CycleT - (cpuRegs.cycle - vsyncCounter.sCycle);
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nextStartCounter = cpuRegs.cycle;
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nextDeltaCounter = vsyncCounter.deltaCycles - (cpuRegs.cycle - vsyncCounter.startCycle);
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// Also check next HSync
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s32 nextHsync = hsyncCounter.CycleT - (cpuRegs.cycle - hsyncCounter.sCycle);
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if (nextHsync < nextCounter)
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nextCounter = nextHsync;
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s32 nextHsync = hsyncCounter.deltaCycles - (cpuRegs.cycle - hsyncCounter.startCycle);
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if (nextHsync < nextDeltaCounter)
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nextDeltaCounter = nextHsync;
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for (i = 0; i < 4; i++)
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_rcntSet(i);
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// sanity check!
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if (nextCounter < 0)
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nextCounter = 0;
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if (nextDeltaCounter < 0)
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nextDeltaCounter = 0;
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cpuSetNextEvent(nextsCounter, nextCounter); // Need to update on counter resets/target changes
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cpuSetNextEvent(nextStartCounter, nextDeltaCounter); // Need to update on counter resets/target changes
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}
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@@ -187,11 +189,11 @@ void rcntInit()
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gsIsInterlaced = VMManager::Internal::IsFastBootInProgress();
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hsyncCounter.Mode = MODE_HRENDER;
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hsyncCounter.sCycle = cpuRegs.cycle;
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vsyncCounter.CycleT = vSyncInfo.hRender;
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hsyncCounter.startCycle = cpuRegs.cycle;
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hsyncCounter.deltaCycles = vSyncInfo.hRender;
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vsyncCounter.Mode = MODE_VRENDER;
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vsyncCounter.CycleT = vSyncInfo.Render;
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vsyncCounter.sCycle = cpuRegs.cycle;
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vsyncCounter.deltaCycles = vSyncInfo.Render;
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vsyncCounter.startCycle = cpuRegs.cycle;
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for (i = 0; i < 4; i++)
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rcntReset(i);
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@@ -240,31 +242,18 @@ static void vSyncInfoCalc(vSyncTimingInfo* info, double framesPerSecond, u32 sca
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info->GSBlank = (u32)(GSBlank / 10000);
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info->Render = (u32)(Render / 10000);
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info->Blank = (u32)(Blank / 10000);
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const u64 accumilated_vrender = (Render % 10000) + (Blank % 10000);
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info->Render += (u32)(accumilated_vrender / 10000);
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info->hRender = (u32)(hRender / 10000);
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info->hBlank = (u32)(hBlank / 10000);
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info->hScanlinesPerFrame = scansPerFrame;
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if ((Render % 10000) >= 5000)
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info->Render++;
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if ((Blank % 10000) >= 5000)
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info->Blank++;
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const u64 accumilatedHRenderError = (hRender % 10000) + (hBlank % 10000);
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const u64 accumilatedHFractional = accumilatedHRenderError % 10000;
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info->hRender += (u32)(accumilatedHRenderError / 10000);
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info->hSyncError = (accumilatedHFractional * (scansPerFrame / (IsInterlacedVideoMode() ? 2 : 1))) / 10000;
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if ((hRender % 10000) >= 5000)
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info->hRender++;
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if ((hBlank % 10000) >= 5000)
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info->hBlank++;
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// Calculate accumulative hSync rounding error per half-frame:
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if (IsInterlacedVideoMode()) // gets off the chart in that mode
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{
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u32 hSyncCycles = ((info->hRender + info->hBlank) * scansPerFrame) / 2;
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u32 vSyncCycles = (info->Render + info->Blank);
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info->hSyncError = vSyncCycles - hSyncCycles;
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//Console.Warning("%d",info->hSyncError);
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}
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else
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info->hSyncError = 0;
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// Note: In NTSC modes there is some small rounding error in the vsync too,
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// however it would take thousands of frames for it to amount to anything and
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// is thus not worth the effort at this time.
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@@ -419,10 +408,16 @@ void UpdateVSyncRate(bool force)
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if (custom && video_mode_initialized)
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Console.WriteLn(Color_StrongGreen, " ... with user configured refresh rate: %.02f Hz", vertical_frequency);
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hsyncCounter.CycleT = (hsyncCounter.Mode == MODE_HBLANK) ? vSyncInfo.hBlank : vSyncInfo.hRender;
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vsyncCounter.CycleT = (vsyncCounter.Mode == MODE_GSBLANK) ?
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s32 hdiff = hsyncCounter.deltaCycles;
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s32 vdiff = vsyncCounter.deltaCycles;
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hsyncCounter.deltaCycles = (hsyncCounter.Mode == MODE_HBLANK) ? vSyncInfo.hBlank : vSyncInfo.hRender;
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vsyncCounter.deltaCycles = (vsyncCounter.Mode == MODE_GSBLANK) ?
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vSyncInfo.GSBlank :
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((vsyncCounter.Mode == MODE_VSYNC) ? vSyncInfo.Blank : vSyncInfo.Render);
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((vsyncCounter.Mode == MODE_VBLANK) ? vSyncInfo.Blank : vSyncInfo.Render);
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hsyncCounter.startCycle += hdiff - hsyncCounter.deltaCycles;
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vsyncCounter.startCycle += vdiff - vsyncCounter.deltaCycles;
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cpuRcntSet();
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VMManager::Internal::FrameRateChanged();
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@@ -504,15 +499,17 @@ static __fi void VSyncStart(u32 sCycle)
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if (EmuConfig.Trace.Enabled && EmuConfig.Trace.EE.m_EnableAll)
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SysTrace.EE.Counters.Write(" ================ EE COUNTER VSYNC START (frame: %d) ================", g_FrameCount);
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hwIntcIrq(INTC_VBLANK_S);
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psxVBlankStart();
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// Memcard auto ejection - Uses a tick system timed off of real time, decrementing one tick per frame.
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AutoEject::CountDownTicks();
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// Memcard IO detection - Uses a tick system to determine when memcards are no longer being written.
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MemcardBusy::Decrement();
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rcntStartGate(true, sCycle); // Counters Start Gate code
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if (!GSSMODE1reg.SINT)
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{
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hwIntcIrq(INTC_VBLANK_S);
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rcntStartGate(true, sCycle); // Counters Start Gate code
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psxVBlankStart();
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}
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// INTC - VB Blank Start Hack --
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// Hack fix! This corrects a freezeup in Granda 2 where it decides to spin
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@@ -546,6 +543,8 @@ static __fi void VSyncStart(u32 sCycle)
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static __fi void GSVSync()
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{
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// CSR is swapped and GS vBlank IRQ is triggered roughly 3.5 hblanks after VSync Start
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if (GSSMODE1reg.SINT)
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return;
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if (IsProgressiveVideoMode())
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CSRreg.SetField();
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@@ -566,15 +565,12 @@ static __fi void VSyncEnd(u32 sCycle)
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SysTrace.EE.Counters.Write(" ================ EE COUNTER VSYNC END (frame: %d) ================", g_FrameCount);
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g_FrameCount++;
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hwIntcIrq(INTC_VBLANK_E); // HW Irq
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psxVBlankEnd(); // psxCounters vBlank End
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rcntEndGate(true, sCycle); // Counters End Gate Code
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// FolderMemoryCard needs information on how much time has passed since the last write
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// Call it every 60 frames
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if (!(g_FrameCount % 60))
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sioNextFrame();
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if (!GSSMODE1reg.SINT)
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{
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hwIntcIrq(INTC_VBLANK_E); // HW Irq
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psxVBlankEnd(); // psxCounters vBlank End
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rcntEndGate(true, sCycle); // Counters End Gate Code
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}
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// This doesn't seem to be needed here. Games only seem to break with regard to the
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// vsyncstart irq.
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@@ -587,76 +583,39 @@ static u32 hsc = 0;
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static int vblankinc = 0;
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#endif
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__fi void rcntUpdate_hScanline()
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{
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if (!cpuTestCycle(hsyncCounter.sCycle, hsyncCounter.CycleT))
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return;
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//iopEventAction = 1;
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if (hsyncCounter.Mode == MODE_HBLANK)
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{ //HBLANK End / HRENDER Begin
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rcntEndGate(false, hsyncCounter.sCycle + hsyncCounter.CycleT);
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psxHBlankEnd();
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// Setup the hRender's start and end cycle information:
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hsyncCounter.sCycle += vSyncInfo.hBlank; // start (absolute cycle value)
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hsyncCounter.CycleT = vSyncInfo.hRender; // endpoint (delta from start value)
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hsyncCounter.Mode = MODE_HRENDER;
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}
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else
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{ //HBLANK START / HRENDER End
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if (!CSRreg.HSINT)
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{
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CSRreg.HSINT = true;
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if (!GSIMR.HSMSK)
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gsIrq();
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}
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rcntStartGate(false, hsyncCounter.sCycle + hsyncCounter.CycleT);
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psxHBlankStart();
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// set up the hblank's start and end cycle information:
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hsyncCounter.sCycle += vSyncInfo.hRender; // start (absolute cycle value)
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hsyncCounter.CycleT = vSyncInfo.hBlank; // endpoint (delta from start value)
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hsyncCounter.Mode = MODE_HBLANK;
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#ifdef VSYNC_DEBUG
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hsc++;
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#endif
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}
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}
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__fi void rcntUpdate_vSync()
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{
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if (!cpuTestCycle(vsyncCounter.sCycle, vsyncCounter.CycleT))
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if (!cpuTestCycle(vsyncCounter.startCycle, vsyncCounter.deltaCycles))
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return;
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if (vsyncCounter.Mode == MODE_VSYNC)
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if (vsyncCounter.Mode == MODE_VBLANK)
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{
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VSyncEnd(vsyncCounter.sCycle + vsyncCounter.CycleT);
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vsyncCounter.startCycle += vSyncInfo.Blank;
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vsyncCounter.deltaCycles = vSyncInfo.Render;
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VSyncEnd(vsyncCounter.startCycle);
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vsyncCounter.sCycle += vSyncInfo.Blank;
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vsyncCounter.CycleT = vSyncInfo.Render;
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vsyncCounter.Mode = MODE_VRENDER; // VSYNC END - Render begin
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}
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else if (vsyncCounter.Mode == MODE_GSBLANK) // GS CSR Swap and interrupt
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{
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GSVSync();
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vsyncCounter.Mode = MODE_VSYNC;
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vsyncCounter.Mode = MODE_VBLANK;
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// Don't set the start cycle, makes it easier to calculate the correct Vsync End time
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vsyncCounter.CycleT = vSyncInfo.Blank;
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vsyncCounter.deltaCycles = vSyncInfo.Blank;
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}
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else // VSYNC Start
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{
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VSyncStart(vsyncCounter.sCycle + vsyncCounter.CycleT);
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vsyncCounter.startCycle += vSyncInfo.Render;
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vsyncCounter.deltaCycles = vSyncInfo.GSBlank;
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VSyncStart(vsyncCounter.startCycle);
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vsyncCounter.sCycle += vSyncInfo.Render;
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vsyncCounter.CycleT = vSyncInfo.GSBlank;
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vsyncCounter.Mode = MODE_GSBLANK;
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// Accumulate hsync rounding errors:
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hsyncCounter.sCycle += vSyncInfo.hSyncError;
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hsyncCounter.deltaCycles += vSyncInfo.hSyncError;
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#ifdef VSYNC_DEBUG
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vblankinc++;
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@@ -671,6 +630,53 @@ __fi void rcntUpdate_vSync()
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}
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}
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__fi void rcntUpdate_hScanline()
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{
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if (!cpuTestCycle(hsyncCounter.startCycle, hsyncCounter.deltaCycles))
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return;
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//iopEventAction = 1;
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if (hsyncCounter.Mode == MODE_HBLANK)
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{ //HBLANK End / HRENDER Begin
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// Setup the hRender's start and end cycle information:
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hsyncCounter.startCycle += vSyncInfo.hBlank; // start (absolute cycle value)
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hsyncCounter.deltaCycles = vSyncInfo.hRender; // endpoint (delta from start value)
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if (!GSSMODE1reg.SINT)
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{
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rcntEndGate(false, hsyncCounter.startCycle);
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psxHBlankEnd();
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}
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hsyncCounter.Mode = MODE_HRENDER;
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}
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else
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{ //HBLANK START / HRENDER End
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// set up the hblank's start and end cycle information:
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hsyncCounter.startCycle += vSyncInfo.hRender; // start (absolute cycle value)
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hsyncCounter.deltaCycles = vSyncInfo.hBlank; // endpoint (delta from start value)
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if (!GSSMODE1reg.SINT)
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{
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if (!CSRreg.HSINT)
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{
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CSRreg.HSINT = true;
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if (!GSIMR.HSMSK)
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gsIrq();
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}
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rcntStartGate(false, hsyncCounter.startCycle);
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psxHBlankStart();
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}
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hsyncCounter.Mode = MODE_HBLANK;
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#ifdef VSYNC_DEBUG
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hsc++;
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#endif
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}
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}
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static __fi void _cpuTestTarget(int i)
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{
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if (counters[i].count < counters[i].target)
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@@ -726,7 +732,23 @@ __fi bool rcntCanCount(int i)
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(counters[i].mode.GateSource == 1 && (vsyncCounter.Mode == MODE_VRENDER || counters[i].mode.GateMode != 0)));
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}
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// forceinline note: this method is called from two locations, but one
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__fi void rcntSyncCounter(int i)
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{
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if (counters[i].mode.ClockSource != 0x3) // don't count hblank sources
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{
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const u32 change = (cpuRegs.cycle - counters[i].startCycle) / counters[i].rate;
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counters[i].startCycle += change * counters[i].rate;
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counters[i].startCycle &= ~(counters[i].rate - 1);
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if (rcntCanCount(i))
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counters[i].count += change;
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}
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else
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counters[i].startCycle = cpuRegs.cycle;
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}
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// forceinline note: this method is called from two locations, but one
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// of them is the interpreter, which doesn't count. ;) So might as
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// well forceinline it!
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__fi void rcntUpdate()
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@@ -739,22 +761,13 @@ __fi void rcntUpdate()
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for (int i = 0; i <= 3; i++)
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{
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if (!rcntCanCount(i))
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continue;
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rcntSyncCounter(i);
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if (counters[i].mode.ClockSource != 0x3) // don't count hblank sources
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{
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const u32 change = (cpuRegs.cycle - counters[i].sCycleT) / counters[i].rate;
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counters[i].count += change;
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counters[i].sCycleT += change * counters[i].rate;
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if (counters[i].mode.ClockSource == 0x3 || !rcntCanCount(i)) // don't count hblank sources
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continue;
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// Check Counter Targets and Overflows:
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// Check Overflow first, in case the target is 0
|
||||
_cpuTestOverflow(i);
|
||||
_cpuTestTarget(i);
|
||||
}
|
||||
else
|
||||
counters[i].sCycleT = cpuRegs.cycle;
|
||||
_cpuTestOverflow(i);
|
||||
_cpuTestTarget(i);
|
||||
}
|
||||
|
||||
cpuRcntSet();
|
||||
@@ -784,10 +797,8 @@ static __fi void rcntStartGate(bool isVblank, u32 sCycle)
|
||||
// Update counters using the hblank as the clock. This keeps the hblank source
|
||||
// nicely in sync with the counters and serves as an optimization also, since these
|
||||
// counter won't receive special rcntUpdate scheduling.
|
||||
|
||||
// Note: Target and overflow tests must be done here since they won't be done
|
||||
// currectly by rcntUpdate (since it's not being scheduled for these counters)
|
||||
|
||||
counters[i].count += HBLANK_COUNTER_SPEED;
|
||||
_cpuTestOverflow(i);
|
||||
_cpuTestTarget(i);
|
||||
@@ -803,11 +814,10 @@ static __fi void rcntStartGate(bool isVblank, u32 sCycle)
|
||||
{
|
||||
case 0x0: //Count When Signal is low (V_RENDER ONLY)
|
||||
|
||||
// Just set the start cycle (sCycleT) -- counting will be done as needed
|
||||
// Just set the start cycle -- counting will be done as needed
|
||||
// for events (overflows, targets, mode changes, and the gate off below)
|
||||
|
||||
counters[i].count = rcntRcount(i);
|
||||
counters[i].sCycleT = sCycle;
|
||||
rcntSyncCounter(i);
|
||||
counters[i].startCycle = sCycle & ~(counters[i].rate - 1);
|
||||
EECNT_LOG("EE Counter[%d] %s StartGate Type0, count = %x", i,
|
||||
isVblank ? "vblank" : "hblank", counters[i].count);
|
||||
break;
|
||||
@@ -816,14 +826,12 @@ static __fi void rcntStartGate(bool isVblank, u32 sCycle)
|
||||
break;
|
||||
case 0x1: // Reset on Vsync start
|
||||
case 0x3: // Reset on Vsync start and end
|
||||
{
|
||||
rcntSyncCounter(i);
|
||||
counters[i].count = 0;
|
||||
counters[i].target &= 0xffff;
|
||||
const u32 change = (sCycle - counters[i].sCycleT) / counters[i].rate;
|
||||
counters[i].sCycleT = sCycle - ((sCycle - counters[i].sCycleT) - (change * counters[i].rate));
|
||||
counters[i].startCycle = sCycle & ~(counters[i].rate - 1);
|
||||
EECNT_LOG("EE Counter[%d] %s StartGate Type%d, count = %x", i,
|
||||
isVblank ? "vblank" : "hblank", counters[i].mode.GateMode, counters[i].count);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -850,7 +858,7 @@ static __fi void rcntEndGate(bool isVblank, u32 sCycle)
|
||||
switch (counters[i].mode.GateMode)
|
||||
{
|
||||
case 0x0: //Count When Signal is low (V_RENDER ONLY)
|
||||
counters[i].sCycleT = sCycle;
|
||||
counters[i].startCycle = sCycle & ~(counters[i].rate - 1);
|
||||
|
||||
EECNT_LOG("EE Counter[%d] %s EndGate Type0, count = %x", i,
|
||||
isVblank ? "vblank" : "hblank", counters[i].count);
|
||||
@@ -862,14 +870,12 @@ static __fi void rcntEndGate(bool isVblank, u32 sCycle)
|
||||
|
||||
case 0x2: // Reset on Vsync end
|
||||
case 0x3: // Reset on Vsync start and end
|
||||
{
|
||||
rcntSyncCounter(i);
|
||||
EECNT_LOG("EE Counter[%d] %s EndGate Type%d, count = %x", i,
|
||||
isVblank ? "vblank" : "hblank", counters[i].mode.GateMode, counters[i].count);
|
||||
counters[i].count = 0;
|
||||
counters[i].target &= 0xffff;
|
||||
const u32 change = (sCycle - counters[i].sCycleT) / counters[i].rate;
|
||||
counters[i].sCycleT = sCycle - ((sCycle - counters[i].sCycleT) - (change * counters[i].rate));
|
||||
}
|
||||
counters[i].startCycle = sCycle & ~(counters[i].rate - 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@@ -879,14 +885,7 @@ static __fi void rcntEndGate(bool isVblank, u32 sCycle)
|
||||
|
||||
static __fi void rcntWmode(int index, u32 value)
|
||||
{
|
||||
if (rcntCanCount(index) && counters[index].mode.ClockSource != 0x3)
|
||||
{
|
||||
const u32 change = (cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate;
|
||||
counters[index].count += change;
|
||||
counters[index].sCycleT += change * counters[index].rate;
|
||||
}
|
||||
else
|
||||
counters[index].sCycleT = cpuRegs.cycle;
|
||||
rcntSyncCounter(index);
|
||||
|
||||
// Clear OverflowReached and TargetReached flags (0xc00 mask), but *only* if they are set to 1 in the
|
||||
// given value. (yes, the bits are cleared when written with '1's).
|
||||
@@ -902,6 +901,8 @@ static __fi void rcntWmode(int index, u32 value)
|
||||
case 3: counters[index].rate = vSyncInfo.hBlank+vSyncInfo.hRender; break;
|
||||
}
|
||||
|
||||
// In case the rate has changed we need to set the start cycle to the previous tick.
|
||||
counters[index].startCycle = cpuRegs.cycle & ~(counters[index].rate - 1);
|
||||
_rcntSetGate(index);
|
||||
_rcntSet(index);
|
||||
}
|
||||
@@ -911,13 +912,7 @@ static __fi void rcntWcount(int index, u32 value)
|
||||
EECNT_LOG("EE Counter[%d] writeCount = %x, oldcount=%x, target=%x", index, value, counters[index].count, counters[index].target);
|
||||
|
||||
// re-calculate the start cycle of the counter based on elapsed time since the last counter update:
|
||||
if (rcntCanCount(index) && counters[index].mode.ClockSource != 0x3)
|
||||
{
|
||||
const u32 change = (cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate;
|
||||
counters[index].sCycleT += change * counters[index].rate;
|
||||
}
|
||||
else
|
||||
counters[index].sCycleT = cpuRegs.cycle;
|
||||
rcntSyncCounter(index);
|
||||
|
||||
counters[index].count = value & 0xffff;
|
||||
|
||||
@@ -940,14 +935,7 @@ static __fi void rcntWtarget(int index, u32 value)
|
||||
// If the target is behind the current count, set it up so that the counter must
|
||||
// overflow first before the target fires:
|
||||
|
||||
if (rcntCanCount(index) && counters[index].mode.ClockSource != 0x3)
|
||||
{
|
||||
const u32 change = (cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate;
|
||||
counters[index].count += change;
|
||||
counters[index].sCycleT += change * counters[index].rate;
|
||||
}
|
||||
else
|
||||
counters[index].sCycleT = cpuRegs.cycle;
|
||||
rcntSyncCounter(index);
|
||||
|
||||
if (counters[index].target <= counters[index].count)
|
||||
counters[index].target |= EECNT_FUTURE_TARGET;
|
||||
@@ -965,11 +953,9 @@ __fi u32 rcntRcount(int index)
|
||||
{
|
||||
u32 ret;
|
||||
|
||||
// only count if the counter is turned on (0x80) and is not an hsync gate (!0x03)
|
||||
if (rcntCanCount(index) && (counters[index].mode.ClockSource != 0x3))
|
||||
ret = counters[index].count + ((cpuRegs.cycle - counters[index].sCycleT) / counters[index].rate);
|
||||
else
|
||||
ret = counters[index].count;
|
||||
rcntSyncCounter(index);
|
||||
|
||||
ret = counters[index].count;
|
||||
|
||||
// Spams the Console.
|
||||
EECNT_LOG("EE Counter[%d] readCount32 = %x", index, ret);
|
||||
@@ -984,24 +970,25 @@ __fi u16 rcntRead32(u32 mem)
|
||||
// are all fixed to 0, so we always truncate everything in these two pages using a u16
|
||||
// return value! --air
|
||||
|
||||
switch( mem ) {
|
||||
case(RCNT0_COUNT): return (u16)rcntRcount(0);
|
||||
case(RCNT0_MODE): return (u16)counters[0].modeval;
|
||||
case(RCNT0_TARGET): return (u16)counters[0].target;
|
||||
case(RCNT0_HOLD): return (u16)counters[0].hold;
|
||||
switch( mem )
|
||||
{
|
||||
case(RCNT0_COUNT): return (u16)rcntRcount(0);
|
||||
case(RCNT0_MODE): return (u16)counters[0].modeval;
|
||||
case(RCNT0_TARGET): return (u16)counters[0].target;
|
||||
case(RCNT0_HOLD): return (u16)counters[0].hold;
|
||||
|
||||
case(RCNT1_COUNT): return (u16)rcntRcount(1);
|
||||
case(RCNT1_MODE): return (u16)counters[1].modeval;
|
||||
case(RCNT1_TARGET): return (u16)counters[1].target;
|
||||
case(RCNT1_HOLD): return (u16)counters[1].hold;
|
||||
case(RCNT1_COUNT): return (u16)rcntRcount(1);
|
||||
case(RCNT1_MODE): return (u16)counters[1].modeval;
|
||||
case(RCNT1_TARGET): return (u16)counters[1].target;
|
||||
case(RCNT1_HOLD): return (u16)counters[1].hold;
|
||||
|
||||
case(RCNT2_COUNT): return (u16)rcntRcount(2);
|
||||
case(RCNT2_MODE): return (u16)counters[2].modeval;
|
||||
case(RCNT2_TARGET): return (u16)counters[2].target;
|
||||
case(RCNT2_COUNT): return (u16)rcntRcount(2);
|
||||
case(RCNT2_MODE): return (u16)counters[2].modeval;
|
||||
case(RCNT2_TARGET): return (u16)counters[2].target;
|
||||
|
||||
case(RCNT3_COUNT): return (u16)rcntRcount(3);
|
||||
case(RCNT3_MODE): return (u16)counters[3].modeval;
|
||||
case(RCNT3_TARGET): return (u16)counters[3].target;
|
||||
case(RCNT3_COUNT): return (u16)rcntRcount(3);
|
||||
case(RCNT3_MODE): return (u16)counters[3].modeval;
|
||||
case(RCNT3_TARGET): return (u16)counters[3].target;
|
||||
}
|
||||
|
||||
return psHu16(mem);
|
||||
@@ -1016,24 +1003,25 @@ __fi bool rcntWrite32(u32 mem, mem32_t& value)
|
||||
// count, mode, target, and hold. This will allow for a simplified handler for register
|
||||
// reads.
|
||||
|
||||
switch( mem ) {
|
||||
case(RCNT0_COUNT): return rcntWcount(0, value), false;
|
||||
case(RCNT0_MODE): return rcntWmode(0, value), false;
|
||||
case(RCNT0_TARGET): return rcntWtarget(0, value), false;
|
||||
case(RCNT0_HOLD): return rcntWhold(0, value), false;
|
||||
switch( mem )
|
||||
{
|
||||
case(RCNT0_COUNT): return rcntWcount(0, value), false;
|
||||
case(RCNT0_MODE): return rcntWmode(0, value), false;
|
||||
case(RCNT0_TARGET): return rcntWtarget(0, value), false;
|
||||
case(RCNT0_HOLD): return rcntWhold(0, value), false;
|
||||
|
||||
case(RCNT1_COUNT): return rcntWcount(1, value), false;
|
||||
case(RCNT1_MODE): return rcntWmode(1, value), false;
|
||||
case(RCNT1_TARGET): return rcntWtarget(1, value), false;
|
||||
case(RCNT1_HOLD): return rcntWhold(1, value), false;
|
||||
case(RCNT1_COUNT): return rcntWcount(1, value), false;
|
||||
case(RCNT1_MODE): return rcntWmode(1, value), false;
|
||||
case(RCNT1_TARGET): return rcntWtarget(1, value), false;
|
||||
case(RCNT1_HOLD): return rcntWhold(1, value), false;
|
||||
|
||||
case(RCNT2_COUNT): return rcntWcount(2, value), false;
|
||||
case(RCNT2_MODE): return rcntWmode(2, value), false;
|
||||
case(RCNT2_TARGET): return rcntWtarget(2, value), false;
|
||||
case(RCNT2_COUNT): return rcntWcount(2, value), false;
|
||||
case(RCNT2_MODE): return rcntWmode(2, value), false;
|
||||
case(RCNT2_TARGET): return rcntWtarget(2, value), false;
|
||||
|
||||
case(RCNT3_COUNT): return rcntWcount(3, value), false;
|
||||
case(RCNT3_MODE): return rcntWmode(3, value), false;
|
||||
case(RCNT3_TARGET): return rcntWtarget(3, value), false;
|
||||
case(RCNT3_COUNT): return rcntWcount(3, value), false;
|
||||
case(RCNT3_MODE): return rcntWmode(3, value), false;
|
||||
case(RCNT3_TARGET): return rcntWtarget(3, value), false;
|
||||
}
|
||||
|
||||
// unhandled .. do memory writeback.
|
||||
@@ -1051,8 +1039,8 @@ bool SaveStateBase::rcntFreeze()
|
||||
Freeze(counters);
|
||||
Freeze(hsyncCounter);
|
||||
Freeze(vsyncCounter);
|
||||
Freeze(nextCounter);
|
||||
Freeze(nextsCounter);
|
||||
Freeze(nextDeltaCounter);
|
||||
Freeze(nextStartCounter);
|
||||
Freeze(vSyncInfo);
|
||||
Freeze(gsVideoMode);
|
||||
Freeze(gsIsInterlaced);
|
||||
|
||||
Reference in new issue
Block a user