diff --git a/pcsx2/HwWrite.cpp b/pcsx2/HwWrite.cpp index 772da76505..706847cba5 100644 --- a/pcsx2/HwWrite.cpp +++ b/pcsx2/HwWrite.cpp @@ -63,9 +63,9 @@ static __forceinline void DmaExec16( void (*func)(), u32 mem, u16 value ) //It's invalid for the hardware to write a DMA while it is active, not without Suspending the DMAC if (chcr.STR && reg->chcr.STR && dmacRegs->ctrl.DMAE) { - if((reg->chcr._u32 & 0xff) == (chcr._u32 & 0xff)) //Tried to start another DMA in the same mode + if((reg->chcr._u32 & 0xff) == (chcr._u32 & 0xff) && psHu8(DMAC_ENABLER+2) == 0) //Tried to start another DMA in the same mode DevCon.Warning(L"DMAExec32 Attempt to run DMA while one is already active in %s(%x)", ChcrName(mem), mem); - else if(psHu8(DMAC_ENABLER+2) != 0)//Just trying to change mode without stopping the DMA, so we dont care really :P + else //Just trying to change mode without stopping the DMA, so we dont care really :P { HW_LOG("Attempted to change modes while DMA active, ignoring"); // When DMA is active only STR field is writable, so we just @@ -104,9 +104,9 @@ static void DmaExec( void (*func)(), u32 mem, u32 value ) //It's invalid for the hardware to write a DMA while it is active, not without Suspending the DMAC if (chcr.STR && reg->chcr.STR && dmacRegs->ctrl.DMAE) { - if((reg->chcr._u32 & 0xff) == (chcr._u32 & 0xff)) //Tried to start another DMA in the same mode + if((reg->chcr._u32 & 0xff) == (chcr._u32 & 0xff) && psHu8(DMAC_ENABLER+2) == 0) //Tried to start another DMA in the same mode DevCon.Warning(L"DMAExec32 Attempt to run DMA while one is already active in %s(%x)", ChcrName(mem), mem); - else if(psHu8(DMAC_ENABLER+2) != 0)//Just trying to change mode without stopping the DMA, so we dont care really :P + else //Just trying to change mode without stopping the DMA, so we dont care really :P { HW_LOG("Attempted to change modes while DMA active, ignoring"); // When DMA is active only STR field is writable, so we just diff --git a/pcsx2/IPU/IPU.cpp b/pcsx2/IPU/IPU.cpp index ccea2e9bc2..5ba8b7a26e 100644 --- a/pcsx2/IPU/IPU.cpp +++ b/pcsx2/IPU/IPU.cpp @@ -42,7 +42,7 @@ # define IPU_INT_FROM( cycles ) ipu0Interrupt() # define IPU_FORCEINLINE #else -# define IPU_INT_TO( cycles ) CPU_INT( DMAC_TO_IPU, cycles ) +# define IPU_INT_TO( cycles ) if(!(cpuRegs.interrupt & (1<<4))) CPU_INT( DMAC_TO_IPU, cycles ) # define IPU_INT_FROM( cycles ) CPU_INT( DMAC_FROM_IPU, cycles ) # define IPU_FORCEINLINE __forceinline #endif @@ -1372,7 +1372,7 @@ int IPU1dma() { if(!WaitGSPaths()) { // legacy WaitGSPaths() for now - if(totalqwc == 0)IPU_INT_TO(4); //Give it a short wait. + IPU_INT_TO(4); //Give it a short wait. return totalqwc; } DMA_LOG("Processing Normal QWC left %x Finished %d In Progress %d", ipu1dma->qwc, IPU1Status.DMAFinished, IPU1Status.InProgress); @@ -1386,7 +1386,7 @@ int IPU1dma() { if(!WaitGSPaths()) { // legacy WaitGSPaths() for now - if(totalqwc == 0)IPU_INT_TO(4); //Give it a short wait. + IPU_INT_TO(4); //Give it a short wait. return totalqwc; } DMA_LOG("Processing Chain QWC left %x Finished %d In Progress %d", ipu1dma->qwc, IPU1Status.DMAFinished, IPU1Status.InProgress); @@ -1475,7 +1475,7 @@ int IPU1dma() if(!WaitGSPaths() && ipu1dma->qwc > 0) { // legacy WaitGSPaths() for now - if(totalqwc == 0)IPU_INT_TO(4); //Give it a short wait. + IPU_INT_TO(4); //Give it a short wait. return totalqwc; } DMA_LOG("Processing Start Chain QWC left %x Finished %d In Progress %d", ipu1dma->qwc, IPU1Status.DMAFinished, IPU1Status.InProgress); diff --git a/pcsx2/ps2/GIFpath.cpp b/pcsx2/ps2/GIFpath.cpp index b74e08f5d0..da4b3c7783 100644 --- a/pcsx2/ps2/GIFpath.cpp +++ b/pcsx2/ps2/GIFpath.cpp @@ -455,7 +455,9 @@ __forceinline int GIFPath::ParseTag(GIF_PATH pathidx, const u8* pMem, u32 size) if (pathidx == GIF_PATH_3) { gif->madr += size * 16; gif->qwc -= size; - } + } else if (pathidx == GIF_PATH_2 && !nloop) { //Path2 is odd, but always provides the correct size + GSTransferStatus.PTH2 = STOPPED_MODE; + } return size; }