mirror of
https://github.com/gopher64/gopher64.git
synced 2026-07-11 01:25:20 +02:00
Logan McNaughton
500 lines
16 KiB
Rust
500 lines
16 KiB
Rust
use crate::device;
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use crate::ui;
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const SP_MEM_ADDR_REG: usize = 0;
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const SP_DRAM_ADDR_REG: usize = 1;
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const SP_RD_LEN_REG: usize = 2;
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const SP_WR_LEN_REG: usize = 3;
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pub const SP_STATUS_REG: usize = 4;
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const SP_DMA_FULL_REG: usize = 5;
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const SP_DMA_BUSY_REG: usize = 6;
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const SP_SEMAPHORE_REG: usize = 7;
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pub const SP_REGS_COUNT: usize = 8;
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pub const SP_PC_REG: usize = 0;
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//const SP_IBIST_REG: usize = 1;
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pub const SP_REGS2_COUNT: usize = 2;
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/* SP_STATUS - read */
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pub const SP_STATUS_HALT: u32 = 1 << 0;
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const SP_STATUS_BROKE: u32 = 1 << 1;
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const SP_STATUS_DMA_BUSY: u32 = 1 << 2;
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const SP_STATUS_DMA_FULL: u32 = 1 << 3;
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//const SP_STATUS_IO_FULL: u32 = 1 << 4;
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const SP_STATUS_SSTEP: u32 = 1 << 5;
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const SP_STATUS_INTR_BREAK: u32 = 1 << 6;
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const SP_STATUS_SIG0: u32 = 1 << 7;
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const SP_STATUS_SIG1: u32 = 1 << 8;
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const SP_STATUS_SIG2: u32 = 1 << 9;
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const SP_STATUS_SIG3: u32 = 1 << 10;
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const SP_STATUS_SIG4: u32 = 1 << 11;
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const SP_STATUS_SIG5: u32 = 1 << 12;
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const SP_STATUS_SIG6: u32 = 1 << 13;
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const SP_STATUS_SIG7: u32 = 1 << 14;
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/* SP_STATUS - write */
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const SP_CLR_HALT: u32 = 1 << 0;
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pub const SP_SET_HALT: u32 = 1 << 1;
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const SP_CLR_BROKE: u32 = 1 << 2;
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const SP_CLR_INTR: u32 = 1 << 3;
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const SP_SET_INTR: u32 = 1 << 4;
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const SP_CLR_SSTEP: u32 = 1 << 5;
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const SP_SET_SSTEP: u32 = 1 << 6;
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const SP_CLR_INTR_BREAK: u32 = 1 << 7;
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const SP_SET_INTR_BREAK: u32 = 1 << 8;
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const SP_CLR_SIG0: u32 = 1 << 9;
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const SP_SET_SIG0: u32 = 1 << 10;
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const SP_CLR_SIG1: u32 = 1 << 11;
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const SP_SET_SIG1: u32 = 1 << 12;
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const SP_CLR_SIG2: u32 = 1 << 13;
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const SP_SET_SIG2: u32 = 1 << 14;
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const SP_CLR_SIG3: u32 = 1 << 15;
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const SP_SET_SIG3: u32 = 1 << 16;
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const SP_CLR_SIG4: u32 = 1 << 17;
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const SP_SET_SIG4: u32 = 1 << 18;
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const SP_CLR_SIG5: u32 = 1 << 19;
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const SP_SET_SIG5: u32 = 1 << 20;
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const SP_CLR_SIG6: u32 = 1 << 21;
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const SP_SET_SIG6: u32 = 1 << 22;
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const SP_CLR_SIG7: u32 = 1 << 23;
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const SP_SET_SIG7: u32 = 1 << 24;
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const RSP_MEM_MASK: usize = 0x1FFF;
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#[derive(PartialEq, Copy, Clone, serde::Serialize, serde::Deserialize)]
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pub enum DmaDir {
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None,
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Write,
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Read,
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}
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#[derive(Copy, Clone, serde::Serialize, serde::Deserialize)]
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pub struct RspDma {
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pub dir: DmaDir,
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pub length: u32,
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pub memaddr: u32,
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pub dramaddr: u32,
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}
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#[derive(Clone, serde::Serialize, serde::Deserialize)]
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pub struct Rsp {
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pub cpu: device::rsp_cpu::Cpu,
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pub regs: [u32; SP_REGS_COUNT],
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pub regs2: [u32; SP_REGS2_COUNT],
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#[serde(with = "serde_big_array::BigArray")]
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pub mem: [u8; 0x2000],
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pub fifo: [RspDma; 2],
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pub last_status_value: u32,
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pub run_after_dma: bool,
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}
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pub fn read_mem_fast(
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device: &device::Device,
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address: u64,
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_access_size: device::memory::AccessSize,
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) -> u32 {
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let masked_address = address as usize & RSP_MEM_MASK;
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u32::from_be_bytes(
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device.rsp.mem[masked_address..masked_address + 4]
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.try_into()
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.unwrap(),
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)
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}
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pub fn read_mem(
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device: &mut device::Device,
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address: u64,
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access_size: device::memory::AccessSize,
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) -> u32 {
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device::cop0::add_cycles(device, access_size as u64 / 4);
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let masked_address = address as usize & RSP_MEM_MASK;
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u32::from_be_bytes(
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device.rsp.mem[masked_address..masked_address + 4]
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.try_into()
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.unwrap(),
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)
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}
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pub fn write_mem(device: &mut device::Device, address: u64, value: u32, _mask: u32) {
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let masked_address = address as usize & RSP_MEM_MASK;
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let mut data = u32::from_be_bytes(
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device.rsp.mem[masked_address..masked_address + 4]
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.try_into()
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.unwrap(),
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);
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device::memory::masked_write_32(&mut data, value, 0xFFFFFFFF);
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device.rsp.mem[masked_address..masked_address + 4].copy_from_slice(&data.to_be_bytes());
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if masked_address & 0x1000 != 0 {
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// imem being updated
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device.rsp.cpu.instructions[(masked_address & 0xFFF) / 4].func =
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device::rsp_cpu::decode_opcode(device, data);
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device.rsp.cpu.instructions[(masked_address & 0xFFF) / 4].opcode = data;
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}
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// SH/SB are broken: They overwrite the whole 32 bit, filling everything that isn't written with zeroes
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}
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fn do_dma(device: &mut device::Device, dma: RspDma) {
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let l = dma.length;
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let length = ((l & 0xfff) | 7) + 1;
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let count = ((l >> 12) & 0xff) + 1;
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let skip = (l >> 20) & 0xff8;
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let mut mem_addr = dma.memaddr & 0xff8;
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let mut dram_addr = dma.dramaddr & 0xfffff8;
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let offset = dma.memaddr & 0x1000;
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ui::video::check_framebuffers(dram_addr, count * (length + skip) - skip);
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if dma.dir == DmaDir::Read {
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let mut j = 0;
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while j < count {
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let mut i = 0;
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while i < length {
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let data = u32::from_be_bytes(
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device.rsp.mem[(offset + (mem_addr & 0xFFF)) as usize
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..(offset + (mem_addr & 0xFFF)) as usize + 4]
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.try_into()
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.unwrap(),
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);
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device
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.rdram
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.mem
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.get_mut(dram_addr as usize..dram_addr as usize + 4)
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.unwrap_or(&mut [0; 4])
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.copy_from_slice(&data.to_ne_bytes());
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mem_addr += 4;
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dram_addr += 4;
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i += 4;
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}
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dram_addr += skip;
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j += 1;
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}
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} else {
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let mut j = 0;
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while j < count {
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let mut i = 0;
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while i < length {
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let data = u32::from_ne_bytes(
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device
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.rdram
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.mem
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.get(dram_addr as usize..dram_addr as usize + 4)
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.unwrap_or(&[0; 4])
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.try_into()
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.unwrap_or_default(),
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);
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if offset != 0 {
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// imem being updated
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device.rsp.cpu.instructions[((mem_addr & 0xFFF) / 4) as usize].func =
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device::rsp_cpu::decode_opcode(device, data);
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device.rsp.cpu.instructions[((mem_addr & 0xFFF) / 4) as usize].opcode = data;
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}
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device.rsp.mem[(offset + (mem_addr & 0xFFF)) as usize
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..(offset + (mem_addr & 0xFFF)) as usize + 4]
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.copy_from_slice(&data.to_be_bytes());
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mem_addr += 4;
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dram_addr += 4;
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i += 4;
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}
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dram_addr += skip;
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j += 1;
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}
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}
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device.rsp.regs[SP_MEM_ADDR_REG] = (mem_addr & 0xfff) + (dma.memaddr & 0x1000);
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device.rsp.regs[SP_DRAM_ADDR_REG] = dram_addr;
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device.rsp.regs[SP_RD_LEN_REG] = 0xff8;
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device.rsp.regs[SP_WR_LEN_REG] = 0xff8;
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device::events::create_event(
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device,
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device::events::EVENT_TYPE_SPDMA,
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device::rdram::rdram_calculate_cycles((count * length) as u64) + 9,
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);
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}
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fn fifo_push(device: &mut device::Device, dir: DmaDir) {
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if device.rsp.regs[SP_DMA_FULL_REG] != 0 {
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panic!("RSP DMA already full")
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}
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device.rsp.cpu.sync_point = true;
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if device.rsp.regs[SP_DMA_BUSY_REG] != 0 {
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device.rsp.fifo[1].dir = dir;
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if dir == DmaDir::Read {
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device.rsp.fifo[1].length = device.rsp.regs[SP_WR_LEN_REG]
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} else {
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device.rsp.fifo[1].length = device.rsp.regs[SP_RD_LEN_REG]
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}
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device.rsp.fifo[1].memaddr = device.rsp.regs[SP_MEM_ADDR_REG];
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device.rsp.fifo[1].dramaddr = device.rsp.regs[SP_DRAM_ADDR_REG];
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device.rsp.regs[SP_DMA_FULL_REG] = 1;
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device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_DMA_FULL
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} else {
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device.rsp.fifo[0].dir = dir;
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if dir == DmaDir::Read {
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device.rsp.fifo[0].length = device.rsp.regs[SP_WR_LEN_REG]
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} else {
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device.rsp.fifo[0].length = device.rsp.regs[SP_RD_LEN_REG]
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}
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device.rsp.fifo[0].memaddr = device.rsp.regs[SP_MEM_ADDR_REG];
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device.rsp.fifo[0].dramaddr = device.rsp.regs[SP_DRAM_ADDR_REG];
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device.rsp.regs[SP_DMA_BUSY_REG] = 1;
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device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_DMA_BUSY;
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do_dma(device, device.rsp.fifo[0])
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}
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}
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pub fn fifo_pop(device: &mut device::Device) {
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if device.rsp.regs[SP_DMA_FULL_REG] != 0 {
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device.rsp.fifo[0].dir = device.rsp.fifo[1].dir;
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device.rsp.fifo[0].length = device.rsp.fifo[1].length;
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device.rsp.fifo[0].memaddr = device.rsp.fifo[1].memaddr;
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device.rsp.fifo[0].dramaddr = device.rsp.fifo[1].dramaddr;
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device.rsp.regs[SP_DMA_FULL_REG] = 0;
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device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_DMA_FULL;
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do_dma(device, device.rsp.fifo[0])
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} else {
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device.rsp.regs[SP_DMA_BUSY_REG] = 0;
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device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_DMA_BUSY;
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if device.rsp.run_after_dma {
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device.rsp.run_after_dma = false;
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do_task(device);
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}
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}
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}
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pub fn read_regs(
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device: &mut device::Device,
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address: u64,
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_access_size: device::memory::AccessSize,
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) -> u32 {
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if !device.rsp.cpu.running {
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device::cop0::add_cycles(device, 20);
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}
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let reg = (address & 0xFFFF) >> 2;
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match reg as usize {
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SP_STATUS_REG => {
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let value = device.rsp.regs[reg as usize]
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& (SP_STATUS_SIG0
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| SP_STATUS_SIG1
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| SP_STATUS_SIG2
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| SP_STATUS_SIG3
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| SP_STATUS_SIG4
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| SP_STATUS_SIG5
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| SP_STATUS_SIG6
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| SP_STATUS_SIG7);
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if value == device.rsp.last_status_value && value != 0 {
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device.rsp.cpu.sync_point = true;
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}
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device.rsp.last_status_value = value;
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device.rsp.regs[reg as usize]
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}
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SP_SEMAPHORE_REG => {
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let value = device.rsp.regs[reg as usize];
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if value == 1 {
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device.rsp.cpu.sync_point = true;
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}
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device.rsp.regs[reg as usize] = 1;
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value
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}
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_ => device.rsp.regs[reg as usize],
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}
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}
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pub fn write_regs(device: &mut device::Device, address: u64, value: u32, mask: u32) {
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let reg = (address & 0xFFFF) >> 2;
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match reg as usize {
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SP_STATUS_REG => update_sp_status(device, value),
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SP_RD_LEN_REG => {
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device::memory::masked_write_32(&mut device.rsp.regs[reg as usize], value, mask);
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fifo_push(device, DmaDir::Write)
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}
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SP_WR_LEN_REG => {
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device::memory::masked_write_32(&mut device.rsp.regs[reg as usize], value, mask);
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fifo_push(device, DmaDir::Read)
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}
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SP_SEMAPHORE_REG => {
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device::memory::masked_write_32(&mut device.rsp.regs[reg as usize], 0, mask)
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}
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_ => device::memory::masked_write_32(&mut device.rsp.regs[reg as usize], value, mask),
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}
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}
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pub fn read_regs2(
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device: &mut device::Device,
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address: u64,
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_access_size: device::memory::AccessSize,
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) -> u32 {
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device::cop0::add_cycles(device, 20);
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device.rsp.regs2[((address & 0xFFFF) >> 2) as usize]
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}
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pub fn write_regs2(device: &mut device::Device, address: u64, value: u32, mask: u32) {
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let reg = (address & 0xFFFF) >> 2;
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match reg as usize {
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SP_PC_REG => {
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device::memory::masked_write_32(
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&mut device.rsp.regs2[reg as usize],
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value & 0xFFC,
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mask,
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);
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}
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_ => device::memory::masked_write_32(&mut device.rsp.regs2[reg as usize], value, mask),
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}
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}
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fn update_sp_status(device: &mut device::Device, w: u32) {
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let was_halted = device.rsp.regs[SP_STATUS_REG] & SP_STATUS_HALT != 0;
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/* clear / set halt */
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if w & SP_CLR_HALT != 0 && w & SP_SET_HALT == 0 {
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device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_HALT
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}
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if w & SP_SET_HALT != 0 && w & SP_CLR_HALT == 0 {
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device::events::remove_event(device, device::events::EVENT_TYPE_SP);
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device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_HALT
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}
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/* clear broke */
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if w & SP_CLR_BROKE != 0 {
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device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_BROKE
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}
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/* clear SP interrupt */
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if (w & SP_CLR_INTR) != 0 && (w & SP_SET_INTR) == 0 {
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device::mi::clear_rcp_interrupt(device, device::mi::MI_INTR_SP)
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}
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/* set SP interrupt */
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if (w & SP_SET_INTR) != 0 && (w & SP_CLR_INTR) == 0 {
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device::mi::set_rcp_interrupt(device, device::mi::MI_INTR_SP);
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}
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/* clear / set single step */
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if w & SP_CLR_SSTEP != 0 && w & SP_SET_SSTEP == 0 {
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device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_SSTEP
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}
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if w & SP_SET_SSTEP != 0 && w & SP_CLR_SSTEP == 0 {
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device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_SSTEP
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}
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/* clear / set interrupt on break */
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if w & SP_CLR_INTR_BREAK != 0 && w & SP_SET_INTR_BREAK == 0 {
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device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_INTR_BREAK
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}
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if w & SP_SET_INTR_BREAK != 0 && w & SP_CLR_INTR_BREAK == 0 {
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device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_INTR_BREAK
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}
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/* clear / set signal 0 */
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if w & SP_CLR_SIG0 != 0 && w & SP_SET_SIG0 == 0 {
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device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_SIG0
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}
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if w & SP_SET_SIG0 != 0 && w & SP_CLR_SIG0 == 0 {
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device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_SIG0
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}
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/* clear / set signal 1 */
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if w & SP_CLR_SIG1 != 0 && w & SP_SET_SIG1 == 0 {
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device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_SIG1
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}
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if w & SP_SET_SIG1 != 0 && w & SP_CLR_SIG1 == 0 {
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device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_SIG1
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}
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/* clear / set signal 2 */
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if w & SP_CLR_SIG2 != 0 && w & SP_SET_SIG2 == 0 {
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device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_SIG2
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}
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if w & SP_SET_SIG2 != 0 && w & SP_CLR_SIG2 == 0 {
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device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_SIG2
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}
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/* clear / set signal 3 */
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if w & SP_CLR_SIG3 != 0 && w & SP_SET_SIG3 == 0 {
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device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_SIG3
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}
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if w & SP_SET_SIG3 != 0 && w & SP_CLR_SIG3 == 0 {
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device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_SIG3
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}
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/* clear / set signal 4 */
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if w & SP_CLR_SIG4 != 0 && w & SP_SET_SIG4 == 0 {
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device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_SIG4
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}
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if w & SP_SET_SIG4 != 0 && w & SP_CLR_SIG4 == 0 {
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device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_SIG4
|
|
}
|
|
|
|
/* clear / set signal 5 */
|
|
if w & SP_CLR_SIG5 != 0 && w & SP_SET_SIG5 == 0 {
|
|
device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_SIG5
|
|
}
|
|
if w & SP_SET_SIG5 != 0 && w & SP_CLR_SIG5 == 0 {
|
|
device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_SIG5
|
|
}
|
|
|
|
/* clear / set signal 6 */
|
|
if w & SP_CLR_SIG6 != 0 && w & SP_SET_SIG6 == 0 {
|
|
device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_SIG6
|
|
}
|
|
if w & SP_SET_SIG6 != 0 && w & SP_CLR_SIG6 == 0 {
|
|
device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_SIG6
|
|
}
|
|
|
|
/* clear / set signal 7 */
|
|
if w & SP_CLR_SIG7 != 0 && w & SP_SET_SIG7 == 0 {
|
|
device.rsp.regs[SP_STATUS_REG] &= !SP_STATUS_SIG7
|
|
}
|
|
if w & SP_SET_SIG7 != 0 && w & SP_CLR_SIG7 == 0 {
|
|
device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_SIG7
|
|
}
|
|
|
|
if device.rsp.regs[SP_STATUS_REG] & SP_STATUS_HALT == 0 && was_halted {
|
|
device.rsp.cpu.broken = false;
|
|
device.rsp.cpu.halted = false;
|
|
do_task(device);
|
|
}
|
|
}
|
|
|
|
fn do_task(device: &mut device::Device) {
|
|
device.rsp.cpu.sync_point = false;
|
|
device.rsp.last_status_value = 0;
|
|
device.rdp.last_status_value = 0;
|
|
if device.rsp.regs[SP_DMA_BUSY_REG] == 1 {
|
|
device.rsp.run_after_dma = true
|
|
} else {
|
|
let timer = device::rsp_cpu::run(device);
|
|
|
|
device::events::create_event(device, device::events::EVENT_TYPE_SP, timer)
|
|
}
|
|
}
|
|
|
|
pub fn rsp_event(device: &mut device::Device) {
|
|
if device.rsp.cpu.broken {
|
|
device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_HALT | SP_STATUS_BROKE;
|
|
|
|
if device.rsp.regs[SP_STATUS_REG] & SP_STATUS_INTR_BREAK != 0 {
|
|
device::mi::set_rcp_interrupt(device, device::mi::MI_INTR_SP)
|
|
}
|
|
return;
|
|
}
|
|
if device.rsp.cpu.halted {
|
|
device.rsp.regs[SP_STATUS_REG] |= SP_STATUS_HALT;
|
|
return;
|
|
}
|
|
do_task(device)
|
|
}
|
|
|
|
pub fn init(device: &mut device::Device) {
|
|
device.rsp.regs[SP_STATUS_REG] = 1;
|
|
device::rsp_cpu::init(device);
|
|
}
|