mirror of
https://github.com/gopher64/gopher64.git
synced 2026-07-11 01:25:20 +02:00
Logan McNaughton
430 lines
19 KiB
Rust
430 lines
19 KiB
Rust
use crate::device;
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pub struct BranchState {
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pub state: device::cpu::State,
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pub pc: u32,
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}
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pub struct Cpu {
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pub branch_state: BranchState,
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pub broken: bool,
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pub halted: bool,
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pub sync_point: bool,
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pub gpr: [u32; 32],
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pub vpr: [u128; 32],
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pub reciprocals: [u16; 512],
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pub inverse_square_roots: [u16; 512],
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pub vcol: std::arch::x86_64::__m128i,
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pub vcoh: std::arch::x86_64::__m128i,
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pub vccl: std::arch::x86_64::__m128i,
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pub vcch: std::arch::x86_64::__m128i,
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pub vce: std::arch::x86_64::__m128i,
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pub accl: std::arch::x86_64::__m128i,
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pub accm: std::arch::x86_64::__m128i,
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pub acch: std::arch::x86_64::__m128i,
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pub divdp: bool,
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pub divin: i16,
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pub divout: i16,
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pub special_instrs: [fn(&mut device::Device, u32); 48],
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pub regimm_instrs: [fn(&mut device::Device, u32); 18],
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pub cop0_instrs: [fn(&mut device::Device, u32); 5],
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pub cop2_instrs: [fn(&mut device::Device, u32); 32],
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pub lwc2_instrs: [fn(&mut device::Device, u32); 12],
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pub swc2_instrs: [fn(&mut device::Device, u32); 12],
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pub instrs: [fn(&mut device::Device, u32); 64],
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pub vec_instrs: [fn(&mut device::Device, u32); 64],
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}
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pub fn in_delay_slot(device: &mut device::Device) -> bool {
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return device.rsp.cpu.branch_state.state == device::cpu::State::DelaySlotTaken
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|| device.rsp.cpu.branch_state.state == device::cpu::State::DelaySlotNotTaken;
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}
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pub fn in_delay_slot_taken(device: &mut device::Device) -> bool {
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return device.rsp.cpu.branch_state.state == device::cpu::State::DelaySlotTaken;
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}
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pub fn run(device: &mut device::Device) -> u64 {
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device.rsp.cpu.broken = false;
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let mut cycle_counter = 0;
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while !device.rsp.cpu.halted && !device.rsp.cpu.sync_point {
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device.rsp.cpu.gpr[0] = 0; // gpr 0 is read only
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let offset = 0x1000 + device.rsp.regs2[device::rsp_interface::SP_PC_REG as usize] as usize;
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let opcode = u32::from_be_bytes(device.rsp.mem[offset..offset + 4].try_into().unwrap());
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execute_opcode(device, opcode)(device, opcode);
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match device.rsp.cpu.branch_state.state {
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device::cpu::State::Step => {
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device.rsp.regs2[device::rsp_interface::SP_PC_REG as usize] += 4
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}
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device::cpu::State::Take => {
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device.rsp.regs2[device::rsp_interface::SP_PC_REG as usize] += 4;
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device.rsp.cpu.branch_state.state = device::cpu::State::DelaySlotTaken
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}
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device::cpu::State::NotTaken => {
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device.rsp.regs2[device::rsp_interface::SP_PC_REG as usize] += 4;
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device.rsp.cpu.branch_state.state = device::cpu::State::DelaySlotNotTaken
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}
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device::cpu::State::DelaySlotTaken => {
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device.rsp.regs2[device::rsp_interface::SP_PC_REG as usize] =
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device.rsp.cpu.branch_state.pc;
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device.rsp.cpu.branch_state.state = device::cpu::State::Step
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}
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device::cpu::State::DelaySlotNotTaken => {
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device.rsp.regs2[device::rsp_interface::SP_PC_REG as usize] += 4;
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device.rsp.cpu.branch_state.state = device::cpu::State::Step
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}
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device::cpu::State::Discard => {
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device.rsp.regs2[device::rsp_interface::SP_PC_REG as usize] += 8;
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device.rsp.cpu.branch_state.state = device::cpu::State::Step
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}
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device::cpu::State::Exception => {
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device.rsp.cpu.branch_state.state = device::cpu::State::Step
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}
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}
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device.rsp.regs2[device::rsp_interface::SP_PC_REG as usize] &= 0xFFC;
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cycle_counter += 1;
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if device.rsp.cpu.broken && device.rsp.cpu.branch_state.state == device::cpu::State::Step {
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break;
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}
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}
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return (cycle_counter as f64 * 1.5) as u64; // converting RCP clock to CPU clock
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}
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pub fn execute_opcode(device: &mut device::Device, opcode: u32) -> fn(&mut device::Device, u32) {
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match opcode >> 26 {
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0 => {
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// SPECIAL
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return device.rsp.cpu.special_instrs[(opcode & 0x3F) as usize];
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}
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1 => {
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// REGIMM
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return device.rsp.cpu.regimm_instrs[((opcode >> 16) & 0x1F) as usize];
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}
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16 => {
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// COP0
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return device.rsp.cpu.cop0_instrs[((opcode >> 21) & 0x1F) as usize];
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}
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18 => {
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// COP2
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return device.rsp.cpu.cop2_instrs[((opcode >> 21) & 0x1F) as usize];
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}
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50 => {
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// LWC2
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return device.rsp.cpu.lwc2_instrs[((opcode >> 11) & 0x1F) as usize];
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}
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58 => {
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// SWC2
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return device.rsp.cpu.swc2_instrs[((opcode >> 11) & 0x1F) as usize];
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}
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_ => return device.rsp.cpu.instrs[(opcode >> 26) as usize],
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}
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}
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pub fn init(device: &mut device::Device) {
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device.rsp.cpu.reciprocals[0] = !0 as u16;
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let mut index = 1;
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while index < 512 {
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let a = (index + 512) as u64;
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let b = ((1 as u64) << 34) / a;
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device.rsp.cpu.reciprocals[index] = ((b + 1) >> 8) as u16;
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index += 1;
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}
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index = 0;
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while index < 512 {
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let mut shift = 0;
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if index % 2 == 1 {
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shift = 1
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}
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let a = ((index + 512) >> shift) as u64;
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let mut b = (1 << 17) as u64;
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//find the largest b where b < 1.0 / sqrt(a)
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while a * (b + 1) * (b + 1) < ((1 as u64) << 44) {
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b += 1;
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}
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device.rsp.cpu.inverse_square_roots[index] = (b >> 1) as u16;
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index += 1;
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}
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device.rsp.cpu.instrs = [
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device::rsp_su_instructions::reserved, // SPECIAL
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device::rsp_su_instructions::reserved, // REGIMM
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device::rsp_su_instructions::j, // 2
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device::rsp_su_instructions::jal, // 3
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device::rsp_su_instructions::beq, // 4
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device::rsp_su_instructions::bne, // 5
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device::rsp_su_instructions::blez, // 6
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device::rsp_su_instructions::bgtz, // 7
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device::rsp_su_instructions::addi, // 8
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device::rsp_su_instructions::addiu, // 9
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device::rsp_su_instructions::slti, // 10
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device::rsp_su_instructions::sltiu, // 11
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device::rsp_su_instructions::andi, // 12
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device::rsp_su_instructions::ori, // 13
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device::rsp_su_instructions::xori, // 14
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device::rsp_su_instructions::lui, // 15
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device::rsp_su_instructions::reserved, // COP0
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device::rsp_su_instructions::reserved, // COP1
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device::rsp_su_instructions::reserved, // COP2
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device::rsp_su_instructions::reserved, // 19
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device::rsp_su_instructions::reserved, // 20
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device::rsp_su_instructions::reserved, // 21
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device::rsp_su_instructions::reserved, // 22
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device::rsp_su_instructions::reserved, // 23
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device::rsp_su_instructions::reserved, // 24
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device::rsp_su_instructions::reserved, // 25
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device::rsp_su_instructions::reserved, // 26
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device::rsp_su_instructions::reserved, // 27
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device::rsp_su_instructions::reserved, // 28
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device::rsp_su_instructions::reserved, // 29
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device::rsp_su_instructions::reserved, // 30
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device::rsp_su_instructions::reserved, // 31
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device::rsp_su_instructions::lb, // 32
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device::rsp_su_instructions::lh, // 33
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device::rsp_su_instructions::reserved, // 34
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device::rsp_su_instructions::lw, // 35
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device::rsp_su_instructions::lbu, // 36
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device::rsp_su_instructions::lhu, // 37
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device::rsp_su_instructions::reserved, // 38
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device::rsp_su_instructions::lwu, // 39
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device::rsp_su_instructions::sb, // 40
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device::rsp_su_instructions::sh, // 41
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device::rsp_su_instructions::reserved, // 42
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device::rsp_su_instructions::sw, // 43
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device::rsp_su_instructions::reserved, // 44
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device::rsp_su_instructions::reserved, // 45
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device::rsp_su_instructions::reserved, // 46
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device::rsp_su_instructions::reserved, // 47
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device::rsp_su_instructions::reserved, // 48
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device::rsp_su_instructions::reserved, // 49
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device::rsp_su_instructions::reserved, // lwc2
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device::rsp_su_instructions::reserved, // 51
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device::rsp_su_instructions::reserved, // 52
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device::rsp_su_instructions::reserved, // 53
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device::rsp_su_instructions::reserved, // 54
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device::rsp_su_instructions::reserved, // 55
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device::rsp_su_instructions::reserved, // 56
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device::rsp_su_instructions::reserved, // 57
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device::rsp_su_instructions::reserved, // swc2
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device::rsp_su_instructions::reserved, // 59
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device::rsp_su_instructions::reserved, // 60
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device::rsp_su_instructions::reserved, // 61
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device::rsp_su_instructions::reserved, // 62
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device::rsp_su_instructions::reserved, // 63
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];
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device.rsp.cpu.special_instrs = [
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device::rsp_su_instructions::sll, // 0
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device::rsp_su_instructions::reserved, // 1
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device::rsp_su_instructions::srl, // 2
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device::rsp_su_instructions::sra, // 3
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device::rsp_su_instructions::sllv, // 4
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device::rsp_su_instructions::reserved, // 5
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device::rsp_su_instructions::srlv, // 6
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device::rsp_su_instructions::srav, // 7
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device::rsp_su_instructions::jr, // 8
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device::rsp_su_instructions::jalr, // 9
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device::rsp_su_instructions::reserved, // 10
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device::rsp_su_instructions::reserved, // 11
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device::rsp_su_instructions::reserved, // 12
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device::rsp_su_instructions::break_, // 13
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device::rsp_su_instructions::reserved, // 14
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device::rsp_su_instructions::reserved, // 15
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device::rsp_su_instructions::reserved, // 16
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device::rsp_su_instructions::reserved, // 17
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device::rsp_su_instructions::reserved, // 18
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device::rsp_su_instructions::reserved, // 19
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device::rsp_su_instructions::reserved, // 20
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device::rsp_su_instructions::reserved, // 21
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device::rsp_su_instructions::reserved, // 22
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device::rsp_su_instructions::reserved, // 23
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device::rsp_su_instructions::reserved, // 24
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device::rsp_su_instructions::reserved, // 25
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device::rsp_su_instructions::reserved, // 26
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device::rsp_su_instructions::reserved, // 27
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device::rsp_su_instructions::reserved, // 28
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device::rsp_su_instructions::reserved, // 29
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device::rsp_su_instructions::reserved, // 30
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device::rsp_su_instructions::reserved, // 31
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device::rsp_su_instructions::add, // 32
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device::rsp_su_instructions::addu, // 33
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device::rsp_su_instructions::sub, // 34
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device::rsp_su_instructions::subu, // 35
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device::rsp_su_instructions::and, // 36
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device::rsp_su_instructions::or, // 37
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device::rsp_su_instructions::xor, // 38
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device::rsp_su_instructions::nor, // 39
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device::rsp_su_instructions::reserved, // 40
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device::rsp_su_instructions::reserved, // 41
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device::rsp_su_instructions::slt, // 42
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device::rsp_su_instructions::sltu, // 43
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device::rsp_su_instructions::reserved, // 44
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device::rsp_su_instructions::reserved, // 45
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device::rsp_su_instructions::reserved, // 46
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device::rsp_su_instructions::reserved, // 47
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];
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device.rsp.cpu.regimm_instrs = [
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device::rsp_su_instructions::bltz, // 0
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device::rsp_su_instructions::bgez, // 1
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device::rsp_su_instructions::reserved, // 2
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device::rsp_su_instructions::reserved, // 3
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device::rsp_su_instructions::reserved, // 4
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device::rsp_su_instructions::reserved, // 5
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device::rsp_su_instructions::reserved, // 6
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device::rsp_su_instructions::reserved, // 7
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device::rsp_su_instructions::reserved, // 8
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device::rsp_su_instructions::reserved, // 9
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device::rsp_su_instructions::reserved, // 10
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device::rsp_su_instructions::reserved, // 11
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device::rsp_su_instructions::reserved, // 12
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device::rsp_su_instructions::reserved, // 13
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device::rsp_su_instructions::reserved, // 14
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device::rsp_su_instructions::reserved, // 15
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device::rsp_su_instructions::bltzal, // 16
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device::rsp_su_instructions::bgezal, // 17
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];
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device.rsp.cpu.cop0_instrs = [
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device::rsp_su_instructions::mfc0, // 0
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device::rsp_su_instructions::reserved, // 1
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device::rsp_su_instructions::reserved, // 2
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device::rsp_su_instructions::reserved, // 3
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device::rsp_su_instructions::mtc0, // 4
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];
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device.rsp.cpu.cop2_instrs = [
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device::rsp_su_instructions::mfc2, // 0
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device::rsp_su_instructions::reserved, // 1
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device::rsp_su_instructions::cfc2, // 2
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device::rsp_su_instructions::reserved, // 3
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device::rsp_su_instructions::mtc2, // 4
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device::rsp_su_instructions::reserved, // 5
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device::rsp_su_instructions::ctc2, // 6
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device::rsp_su_instructions::reserved, // 7
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device::rsp_su_instructions::reserved, // 8
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device::rsp_su_instructions::reserved, // 9
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device::rsp_su_instructions::reserved, // 10
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device::rsp_su_instructions::reserved, // 11
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device::rsp_su_instructions::reserved, // 12
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device::rsp_su_instructions::reserved, // 13
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device::rsp_su_instructions::reserved, // 14
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device::rsp_su_instructions::reserved, // 15
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device::rsp_vu_instructions::execute_vec, // 16
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device::rsp_vu_instructions::execute_vec, // 17
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device::rsp_vu_instructions::execute_vec, // 18
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device::rsp_vu_instructions::execute_vec, // 19
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device::rsp_vu_instructions::execute_vec, // 20
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device::rsp_vu_instructions::execute_vec, // 21
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device::rsp_vu_instructions::execute_vec, // 22
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device::rsp_vu_instructions::execute_vec, // 23
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device::rsp_vu_instructions::execute_vec, // 24
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device::rsp_vu_instructions::execute_vec, // 25
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device::rsp_vu_instructions::execute_vec, // 26
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device::rsp_vu_instructions::execute_vec, // 27
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device::rsp_vu_instructions::execute_vec, // 28
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device::rsp_vu_instructions::execute_vec, // 29
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device::rsp_vu_instructions::execute_vec, // 30
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device::rsp_vu_instructions::execute_vec, // 31
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];
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device.rsp.cpu.lwc2_instrs = [
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device::rsp_su_instructions::lbv, // 0
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device::rsp_su_instructions::lsv, // 1
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device::rsp_su_instructions::llv, // 2
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device::rsp_su_instructions::ldv, // 3
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device::rsp_su_instructions::lqv, // 4
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device::rsp_su_instructions::lrv, // 5
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device::rsp_su_instructions::lpv, // 6
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device::rsp_su_instructions::luv, // 7
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device::rsp_su_instructions::lhv, // 8
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device::rsp_su_instructions::lfv, // 9
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device::rsp_su_instructions::lwv, // 10
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device::rsp_su_instructions::ltv, // 11
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];
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device.rsp.cpu.swc2_instrs = [
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device::rsp_su_instructions::sbv, // 0
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device::rsp_su_instructions::ssv, // 1
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device::rsp_su_instructions::slv, // 2
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device::rsp_su_instructions::sdv, // 3
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device::rsp_su_instructions::sqv, // 4
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device::rsp_su_instructions::srv, // 5
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device::rsp_su_instructions::spv, // 6
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device::rsp_su_instructions::suv, // 7
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device::rsp_su_instructions::shv, // 8
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device::rsp_su_instructions::sfv, // 9
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device::rsp_su_instructions::swv, // 10
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device::rsp_su_instructions::stv, // 11
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];
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device.rsp.cpu.vec_instrs = [
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device::rsp_vu_instructions::vmulf, // 0
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device::rsp_vu_instructions::vmulu, // 1
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device::rsp_vu_instructions::vrndp, // 2
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device::rsp_vu_instructions::vmulq, // 3
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device::rsp_vu_instructions::vmudl, // 4
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device::rsp_vu_instructions::vmudm, // 5
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device::rsp_vu_instructions::vmudn, // 6
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device::rsp_vu_instructions::vmudh, // 7
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device::rsp_vu_instructions::vmacf, // 8
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device::rsp_vu_instructions::vmacu, // 9
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device::rsp_vu_instructions::vrndn, // 10
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device::rsp_vu_instructions::vmacq, // 11
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device::rsp_vu_instructions::vmadl, // 12
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device::rsp_vu_instructions::vmadm, // 13
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device::rsp_vu_instructions::vmadn, // 14
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device::rsp_vu_instructions::vmadh, // 15
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device::rsp_vu_instructions::vadd, // 16
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device::rsp_vu_instructions::vsub, // 17
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device::rsp_vu_instructions::vzero, // 18
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device::rsp_vu_instructions::vabs, // 19
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device::rsp_vu_instructions::vaddc, // 20
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device::rsp_vu_instructions::vsubc, // 21
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device::rsp_vu_instructions::vzero, // 22
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device::rsp_vu_instructions::vzero, // 23
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device::rsp_vu_instructions::vzero, // 24
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device::rsp_vu_instructions::vzero, // 25
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device::rsp_vu_instructions::vzero, // 26
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device::rsp_vu_instructions::vzero, // 27
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device::rsp_vu_instructions::vzero, // 28
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device::rsp_vu_instructions::vsar, // 29
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device::rsp_vu_instructions::vzero, // 30
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device::rsp_vu_instructions::vzero, // 31
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device::rsp_vu_instructions::vlt, // 32
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device::rsp_vu_instructions::veq, // 33
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device::rsp_vu_instructions::vne, // 34
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device::rsp_vu_instructions::vge, // 35
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device::rsp_vu_instructions::vcl, // 36
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device::rsp_vu_instructions::vch, // 37
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device::rsp_vu_instructions::vcr, // 38
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device::rsp_vu_instructions::vmrg, // 39
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device::rsp_vu_instructions::vand, // 40
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device::rsp_vu_instructions::vnand, // 41
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device::rsp_vu_instructions::vor, // 42
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device::rsp_vu_instructions::vnor, // 43
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device::rsp_vu_instructions::vxor, // 44
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device::rsp_vu_instructions::vnxor, // 45
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device::rsp_vu_instructions::vzero, // 46
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device::rsp_vu_instructions::vzero, // 47
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device::rsp_vu_instructions::vrcp, // 48
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device::rsp_vu_instructions::vrcpl, // 49
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device::rsp_vu_instructions::vrcph, // 50
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device::rsp_vu_instructions::vmov, // 51
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device::rsp_vu_instructions::vrsq, // 52
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device::rsp_vu_instructions::vrsql, // 53
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device::rsp_vu_instructions::vrsqh, // 54
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device::rsp_vu_instructions::vnop, // 55
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device::rsp_vu_instructions::vzero, // 56
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device::rsp_vu_instructions::vzero, // 57
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device::rsp_vu_instructions::vzero, // 58
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device::rsp_vu_instructions::vzero, // 59
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device::rsp_vu_instructions::vzero, // 60
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device::rsp_vu_instructions::vzero, // 61
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device::rsp_vu_instructions::vzero, // 62
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device::rsp_vu_instructions::vnop, // 63
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]
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}
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