mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2026-10-05 02:25:28 +02:00
skidau
d485acdb51
Updated PTE.R bit on Write and Instruction fetch. Added code to read the PTE from MEM2 if the PTE is stored there. Refactored the two hash functions to reduce code duplication. Updated save state version.
537 lines
12 KiB
C++
537 lines
12 KiB
C++
// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#include "Common/Atomic.h"
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#include "Common/ChunkFile.h"
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#include "Common/CommonTypes.h"
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#include "Common/FPURoundMode.h"
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#include "Common/MathUtil.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/Host.h"
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#include "Core/HW/CPU.h"
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#include "Core/HW/EXI.h"
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#include "Core/HW/Memmap.h"
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#include "Core/HW/SystemTimers.h"
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#include "Core/PowerPC/CPUCoreBase.h"
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#include "Core/PowerPC/JitInterface.h"
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#include "Core/PowerPC/PowerPC.h"
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#include "Core/PowerPC/PPCTables.h"
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#include "Core/PowerPC/Interpreter/Interpreter.h"
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CPUCoreBase *cpu_core_base;
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namespace PowerPC
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{
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// STATE_TO_SAVE
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PowerPCState GC_ALIGNED16(ppcState);
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static volatile CPUState state = CPU_POWERDOWN;
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Interpreter * const interpreter = Interpreter::getInstance();
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static CoreMode mode;
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Watches watches;
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BreakPoints breakpoints;
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MemChecks memchecks;
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PPCDebugInterface debug_interface;
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u32 CompactCR()
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{
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u32 new_cr = 0;
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for (int i = 0; i < 8; i++)
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{
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new_cr |= GetCRField(i) << (28 - i * 4);
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}
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return new_cr;
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}
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void ExpandCR(u32 cr)
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{
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for (int i = 0; i < 8; i++)
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{
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SetCRField(i, (cr >> (28 - i * 4)) & 0xF);
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}
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}
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void DoState(PointerWrap &p)
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{
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// some of this code has been disabled, because
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// it changes registers even in MODE_MEASURE (which is suspicious and seems like it could cause desyncs)
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// and because the values it's changing have been added to CoreTiming::DoState, so it might conflict to mess with them here.
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// rSPR(SPR_DEC) = SystemTimers::GetFakeDecrementer();
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// *((u64 *)&TL) = SystemTimers::GetFakeTimeBase(); //works since we are little endian and TL comes first :)
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p.DoPOD(ppcState);
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// SystemTimers::DecrementerSet();
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// SystemTimers::TimeBaseSet();
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JitInterface::DoState(p);
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}
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static void ResetRegisters()
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{
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memset(ppcState.ps, 0, sizeof(ppcState.ps));
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memset(ppcState.gpr, 0, sizeof(ppcState.gpr));
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memset(ppcState.spr, 0, sizeof(ppcState.spr));
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/*
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0x00080200 = lonestar 2.0
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0x00088202 = lonestar 2.2
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0x70000100 = gekko 1.0
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0x00080100 = gekko 2.0
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0x00083203 = gekko 2.3a
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0x00083213 = gekko 2.3b
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0x00083204 = gekko 2.4
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0x00083214 = gekko 2.4e (8SE) - retail HW2
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*/
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ppcState.spr[SPR_PVR] = 0x00083214;
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ppcState.spr[SPR_HID1] = 0x80000000; // We're running at 3x the bus clock
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ppcState.spr[SPR_ECID_U] = 0x0d96e200;
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ppcState.spr[SPR_ECID_M] = 0x1840c00d;
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ppcState.spr[SPR_ECID_L] = 0x82bb08e8;
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ppcState.fpscr = 0;
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ppcState.pc = 0;
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ppcState.npc = 0;
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ppcState.Exceptions = 0;
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for (auto& v : ppcState.cr_val)
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v = 0x8000000000000001;
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TL = 0;
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TU = 0;
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SystemTimers::TimeBaseSet();
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// MSR should be 0x40, but we don't emulate BS1, so it would never be turned off :}
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ppcState.msr = 0;
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rDEC = 0xFFFFFFFF;
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SystemTimers::DecrementerSet();
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}
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void Init(int cpu_core)
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{
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FPURoundMode::SetPrecisionMode(FPURoundMode::PREC_53);
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memset(ppcState.sr, 0, sizeof(ppcState.sr));
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ppcState.pagetable_base = 0;
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ppcState.pagetable_hashmask = 0;
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for (int tlb = 0; tlb < 2; tlb++)
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{
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for (int set = 0; set < 64; set++)
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{
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for (int way = 0; way < 2; way++)
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{
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ppcState.tlb[tlb][set][way].flags = TLB_FLAG_INVALID;
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ppcState.tlb[tlb][set][way].paddr = 0;
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ppcState.tlb[tlb][set][way].pte = 0;
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ppcState.tlb[tlb][set][way].tag = 0;
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}
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}
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}
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ResetRegisters();
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PPCTables::InitTables(cpu_core);
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// We initialize the interpreter because
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// it is used on boot and code window independently.
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interpreter->Init();
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switch (cpu_core)
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{
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case 0:
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{
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cpu_core_base = interpreter;
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break;
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}
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default:
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cpu_core_base = JitInterface::InitJitCore(cpu_core);
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if (!cpu_core_base) // Handle Situations where JIT core isn't available
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{
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WARN_LOG(POWERPC, "Jit core %d not available. Defaulting to interpreter.", cpu_core);
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cpu_core_base = interpreter;
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}
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break;
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}
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if (cpu_core_base != interpreter)
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{
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mode = MODE_JIT;
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}
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else
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{
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mode = MODE_INTERPRETER;
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}
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state = CPU_STEPPING;
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ppcState.iCache.Init();
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if (SConfig::GetInstance().m_LocalCoreStartupParameter.bEnableDebugging)
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breakpoints.ClearAllTemporary();
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}
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void Shutdown()
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{
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JitInterface::Shutdown();
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interpreter->Shutdown();
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cpu_core_base = nullptr;
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state = CPU_POWERDOWN;
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}
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CoreMode GetMode()
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{
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return mode;
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}
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void SetMode(CoreMode new_mode)
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{
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if (new_mode == mode)
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return; // We don't need to do anything.
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mode = new_mode;
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switch (mode)
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{
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case MODE_INTERPRETER: // Switching from JIT to interpreter
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cpu_core_base = interpreter;
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break;
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case MODE_JIT: // Switching from interpreter to JIT.
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// Don't really need to do much. It'll work, the cache will refill itself.
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cpu_core_base = JitInterface::GetCore();
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if (!cpu_core_base) // Has a chance to not get a working JIT core if one isn't active on host
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cpu_core_base = interpreter;
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break;
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}
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}
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void SingleStep()
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{
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cpu_core_base->SingleStep();
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}
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void RunLoop()
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{
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state = CPU_RUNNING;
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cpu_core_base->Run();
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Host_UpdateDisasmDialog();
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}
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CPUState GetState()
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{
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return state;
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}
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volatile CPUState *GetStatePtr()
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{
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return &state;
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}
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void Start()
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{
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state = CPU_RUNNING;
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Host_UpdateDisasmDialog();
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}
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void Pause()
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{
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state = CPU_STEPPING;
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Host_UpdateDisasmDialog();
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}
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void Stop()
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{
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state = CPU_POWERDOWN;
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Host_UpdateDisasmDialog();
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}
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void UpdatePerformanceMonitor(u32 cycles, u32 num_load_stores, u32 num_fp_inst)
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{
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switch (MMCR0.PMC1SELECT)
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{
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case 0: // No change
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break;
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case 1: // Processor cycles
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PowerPC::ppcState.spr[SPR_PMC1] += cycles;
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break;
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default:
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break;
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}
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switch (MMCR0.PMC2SELECT)
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{
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case 0: // No change
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break;
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case 1: // Processor cycles
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PowerPC::ppcState.spr[SPR_PMC2] += cycles;
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break;
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case 11: // Number of loads and stores completed
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PowerPC::ppcState.spr[SPR_PMC2] += num_load_stores;
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break;
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default:
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break;
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}
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switch (MMCR1.PMC3SELECT)
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{
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case 0: // No change
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break;
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case 1: // Processor cycles
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PowerPC::ppcState.spr[SPR_PMC3] += cycles;
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break;
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case 11: // Number of FPU instructions completed
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PowerPC::ppcState.spr[SPR_PMC3] += num_fp_inst;
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break;
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default:
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break;
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}
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switch (MMCR1.PMC4SELECT)
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{
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case 0: // No change
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break;
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case 1: // Processor cycles
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PowerPC::ppcState.spr[SPR_PMC4] += cycles;
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break;
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default:
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break;
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}
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if ((MMCR0.PMC1INTCONTROL && (PowerPC::ppcState.spr[SPR_PMC1] & 0x80000000) != 0) ||
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(MMCR0.PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC2] & 0x80000000) != 0) ||
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(MMCR0.PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC3] & 0x80000000) != 0) ||
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(MMCR0.PMCINTCONTROL && (PowerPC::ppcState.spr[SPR_PMC4] & 0x80000000) != 0))
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PowerPC::ppcState.Exceptions |= EXCEPTION_PERFORMANCE_MONITOR;
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}
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void CheckExceptions()
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{
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// Read volatile data once
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u32 exceptions = ppcState.Exceptions;
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// Example procedure:
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// set SRR0 to either PC or NPC
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//SRR0 = NPC;
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// save specified MSR bits
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//SRR1 = MSR & 0x87C0FFFF;
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// copy ILE bit to LE
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//MSR |= (MSR >> 16) & 1;
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// clear MSR as specified
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//MSR &= ~0x04EF36; // 0x04FF36 also clears ME (only for machine check exception)
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// set to exception type entry point
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//NPC = 0x00000x00;
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// TODO(delroth): Exception priority is completely wrong here: depending on
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// the instruction class, exceptions should be executed in a given order,
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// which is very different from the one arbitrarily chosen here. See §6.1.5
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// in 6xx_pem.pdf.
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if (exceptions & EXCEPTION_ISI)
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{
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SRR0 = NPC;
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// Page fault occurred
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SRR1 = (MSR & 0x87C0FFFF) | (1 << 30);
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000400;
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INFO_LOG(POWERPC, "EXCEPTION_ISI");
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_ISI);
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}
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else if (exceptions & EXCEPTION_PROGRAM)
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{
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SRR0 = PC;
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// say that it's a trap exception
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SRR1 = (MSR & 0x87C0FFFF) | 0x20000;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000700;
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INFO_LOG(POWERPC, "EXCEPTION_PROGRAM");
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_PROGRAM);
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}
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else if (exceptions & EXCEPTION_SYSCALL)
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{
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SRR0 = NPC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000C00;
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INFO_LOG(POWERPC, "EXCEPTION_SYSCALL (PC=%08x)", PC);
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_SYSCALL);
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}
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else if (exceptions & EXCEPTION_FPU_UNAVAILABLE)
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{
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//This happens a lot - GameCube OS uses deferred FPU context switching
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SRR0 = PC; // re-execute the instruction
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000800;
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INFO_LOG(POWERPC, "EXCEPTION_FPU_UNAVAILABLE");
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_FPU_UNAVAILABLE);
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}
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else if (exceptions & EXCEPTION_DSI)
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{
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SRR0 = PC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000300;
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//DSISR and DAR regs are changed in GenerateDSIException()
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INFO_LOG(POWERPC, "EXCEPTION_DSI");
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_DSI);
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}
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else if (exceptions & EXCEPTION_ALIGNMENT)
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{
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//This never happens ATM
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// perhaps we can get dcb* instructions to use this :p
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SRR0 = PC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000600;
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//TODO crazy amount of DSISR options to check out
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INFO_LOG(POWERPC, "EXCEPTION_ALIGNMENT");
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_ALIGNMENT);
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}
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// EXTERNAL INTERRUPT
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else if (MSR & 0x0008000) // Handling is delayed until MSR.EE=1.
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{
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if (exceptions & EXCEPTION_EXTERNAL_INT)
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{
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// Pokemon gets this "too early", it hasn't a handler yet
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SRR0 = NPC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000500;
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INFO_LOG(POWERPC, "EXCEPTION_EXTERNAL_INT");
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_EXTERNAL_INT);
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_dbg_assert_msg_(POWERPC, (SRR1 & 0x02) != 0, "EXTERNAL_INT unrecoverable???");
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}
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else if (exceptions & EXCEPTION_PERFORMANCE_MONITOR)
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{
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SRR0 = NPC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000F00;
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INFO_LOG(POWERPC, "EXCEPTION_PERFORMANCE_MONITOR");
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_PERFORMANCE_MONITOR);
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}
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else if (exceptions & EXCEPTION_DECREMENTER)
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{
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SRR0 = NPC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000900;
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INFO_LOG(POWERPC, "EXCEPTION_DECREMENTER");
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_DECREMENTER);
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}
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}
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}
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void CheckExternalExceptions()
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{
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// Read volatile data once
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u32 exceptions = ppcState.Exceptions;
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// EXTERNAL INTERRUPT
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if (exceptions && (MSR & 0x0008000)) // Handling is delayed until MSR.EE=1.
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{
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if (exceptions & EXCEPTION_EXTERNAL_INT)
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{
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// Pokemon gets this "too early", it hasn't a handler yet
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SRR0 = NPC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000500;
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INFO_LOG(POWERPC, "EXCEPTION_EXTERNAL_INT");
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_EXTERNAL_INT);
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_dbg_assert_msg_(POWERPC, (SRR1 & 0x02) != 0, "EXTERNAL_INT unrecoverable???");
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}
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else if (exceptions & EXCEPTION_PERFORMANCE_MONITOR)
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{
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SRR0 = NPC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000F00;
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INFO_LOG(POWERPC, "EXCEPTION_PERFORMANCE_MONITOR");
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_PERFORMANCE_MONITOR);
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}
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else if (exceptions & EXCEPTION_DECREMENTER)
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{
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SRR0 = NPC;
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SRR1 = MSR & 0x87C0FFFF;
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MSR |= (MSR >> 16) & 1;
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MSR &= ~0x04EF36;
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PC = NPC = 0x00000900;
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INFO_LOG(POWERPC, "EXCEPTION_DECREMENTER");
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Common::AtomicAnd(ppcState.Exceptions, ~EXCEPTION_DECREMENTER);
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}
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else
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{
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_dbg_assert_msg_(POWERPC, 0, "Unknown EXT interrupt: Exceptions == %08x", exceptions);
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ERROR_LOG(POWERPC, "Unknown EXTERNAL INTERRUPT exception: Exceptions == %08x", exceptions);
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}
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}
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}
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void CheckBreakPoints()
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{
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if (PowerPC::breakpoints.IsAddressBreakPoint(PC))
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{
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PowerPC::Pause();
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if (PowerPC::breakpoints.IsTempBreakPoint(PC))
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PowerPC::breakpoints.Remove(PC);
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|
}
|
|
}
|
|
|
|
void OnIdle(u32 _uThreadAddr)
|
|
{
|
|
u32 nextThread = Memory::Read_U32(_uThreadAddr);
|
|
//do idle skipping
|
|
if (nextThread == 0)
|
|
CoreTiming::Idle();
|
|
}
|
|
|
|
void OnIdleIL()
|
|
{
|
|
CoreTiming::Idle();
|
|
}
|
|
|
|
} // namespace
|
|
|
|
|
|
// FPSCR update functions
|
|
|
|
void UpdateFPRF(double dvalue)
|
|
{
|
|
FPSCR.FPRF = MathUtil::ClassifyDouble(dvalue);
|
|
//if (FPSCR.FPRF == 0x11)
|
|
// PanicAlert("QNAN alert");
|
|
}
|